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MMFT5P03HD
Preferred Device
Power MOSFET
5 Amps, 30 Volts
P−Channel SOT−223
This miniature surface mount MOSFET features ultra low RDS(on)
and true logic level performance. It is capable of withstanding high
energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MMFT5P03HD devices are designed for use in low voltage, high
speed switching applications where power efficiency is important.
Typical applications are dc−dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SOT−223 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
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5 AMPERES
30 VOLTS
RDS(on) = 100 mΩ
P−Channel
D
G
S
MARKING
DIAGRAM
4
1
2
TO−261AA
CASE 318E
STYLE 3
5P03H
LWW
3
L
WW
= Location Code
= Work Week
PIN ASSIGNMENT
4 Drain
1
2
Gate
Drain
3
Source
ORDERING INFORMATION
Device
Package
MMFT5P03HDT3
SOT−223
Shipping
4000 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 4
1
Publication Order Number:
MMFT5P03HD/D
MMFT5P03HD
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Negative sign for P−Channel devices omitted for clarity
Symbol
Max
Unit
Drain−to−Source Voltage
Rating
VDSS
30
V
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
VDGR
30
V
Gate−to−Source Voltage − Continuous
VGS
± 20
V
Thermal Resistance − Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current − Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (Note 1)
RTHJA
PD
40
3.13
25
5.2
4.1
26
°C/W
Watts
mW/°C
A
A
A
Thermal Resistance − Junction to Ambient
Total Power Dissipation @ TA = 25°C
Linear Derating Factor
Drain Current − Continuous @ TA = 25°C
Continuous @ TA = 70°C
Pulsed Drain Current (Note 1)
RTHJA
PD
80
1.56
12.5
3.7
2.9
19
°C/W
Watts
mW/°C
A
A
A
− 55 to
150
°C
1″ SQ.
FR−4 or G−10 PCB
10 seconds
Minimum
FR−4 or G−10 PCB
10 seconds
Operating and Storage Temperature Range
ID
ID
IDM
ID
ID
IDM
TJ, Tstg
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc, Peak IL = 12 Apk, L = 3.5 mH, RG = 25 W)
1. Repetitive rating; pulse width limited by maximum junction temperature.
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2
EAS
mJ
250
MMFT5P03HD
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
30
−
−
28
−
−
−
−
−
−
1.0
25
−
−
100
1.0
−
1.75
3.5
3.0
−
−
−
79
119
100
150
gFS
2.0
4.0
−
Mhos
Ciss
−
475
950
pF
Coss
−
220
440
Crss
−
70
140
td(on)
−
12
24
tr
−
24
48
td(off)
−
47
94
tf
−
46
92
td(on)
−
19
38
tr
−
55
110
td(off)
−
30
60
tf
−
40
80
QT
−
17
24
Q1
−
1.7
−
Q2
−
6.3
−
Q3
−
4.6
−
−
−
1.1
0.89
1.5
−
trr
−
39
−
ta
−
20
−
tb
−
19
−
QRR
−
0.042
−
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0)
(Notes 2 & 4)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 24 Vdc, VGS = 0 Vdc)
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
ON
Vdc
mV/°C
μAdc
nAdc
CHARACTERISTICS(1)
Gate Threshold Voltage
(Cpk ≥ 2.0)
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
(Notes 2 & 4)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 5.2 Adc)
(VGS = 4.5 Vdc, ID = 2.6 Adc)
(Notes 2 & 4)
(Cpk ≥ 2.0)
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 Adc)
(Note 2)
VGS(th)
RDS(on)
Vdc
mV/°C
mΩ
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 4.0 Adc,
VGS = 10 Vdc,
RG = 6.0 Ω) (Note 2)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 15 Vdc, ID = 2.0 Adc,
VGS = 4.5 Vdc,
RG = 6.0 Ω) (Note 2)
Fall Time
Gate Charge
(VDS = 24 Vdc, ID = 4.0 Adc,
VGS = 10 Vdc) (Note 2)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 2)
(IS = 4.0 Adc, VGS = 0 Vdc) (Note 2)
(IS = 4.0 Adc, VGS = 0 Vdc,
TJ = 125°C)
Reverse Recovery Time
(IS = 4.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs) (Note 2)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
4. Reflects typical values.
Max limit − Typ
Cpk =
3 x SIGMA
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3
VSD
Vdc
ns
μC
MMFT5P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
8V
6V
8
10
4.5 V
4.3 V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
10
4.1 V
TJ = 25°C
6
3.9 V
3.7 V
4
3.5 V
3.3 V
3.1 V
2
VDS ≥ 10 V
8
6
4
TJ = 100°C
2
25°C
2.7 V
0
0.4
0.8
1.2
1.6
2.5
3
3.5
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID = 4 A
TJ = 25°C
0.2
0.1
2
6
4
10
8
4.5
0.3
TJ = 25°C
0.2
VGS = 4.5 V
0.1
0
10 V
0
2
1
4
3
5
6
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
8
1000
2
VGS = 0 V
VGS = 10 V
ID = 2 A
TJ = 125°C
100
1.5
1
0.5
0
−50
2
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.3
0
−55 °C
0
2
I DSS, LEAKAGE (nA)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
100°C
10
25°C
1
0.1
−25
0
25
50
75
100
125
150
00.1
0
6
12
18
24
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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4
30
MMFT5P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1500
C, CAPACITANCE (pF)
1200
900
VGS = 0 V
VDS = 0 V
TJ = 25°C
Ciss
Crss
600
Ciss
300
Coss
Crss
0
−10
0
VGS
10
20
VDS
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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5
30
12
24
QT
VGS
VDS
VDD = 15 V
ID = 4 A
VGS = 10 V
TJ = 25°C
16
Q1
Q2
4
8
ID = 4 A
TJ = 25°C
Q3
0
1000
0
4
8
12
16
20
0
t, TIME (ns)
8
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MMFT5P03HD
td(off)
tf
100
tr
td(on)
10
1
10
QG, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
IS , SOURCE CURRENT (AMPS)
4
VGS = 0 V
TJ = 25°C
3
2
1
0
0.5
0.6
0.7
0.8
0.9
1
1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
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6
MMFT5P03HD
di/dt = 300 A/μs
Standard Cell Density
trr
I S , SOURCE CURRENT
High Cell Density
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded, and that the
transition time (tr, tf) does not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
10
250
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
dc
1 ms
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
100 μs
1
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
200
150
100
50
0
25
100
VDD = 30 V
VGS = 10 V
IL = 12 Apk
L = 3.5 mH
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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7
150
MMFT5P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (° C/W)
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
SINGLE PULSE
0.0001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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8
1.0E+02
1.0E+03
MMFT5P03HD
INFORMATION FOR USING THE SOT−223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.15
3.8
0.079
2.0
0.091
2.3
0.248
6.3
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
inches
0.059
1.5
mm
SOT−223 POWER DISSIPATION
The power dissipation of the SOT−223 is a function of
the drain pad size. This can vary from the minimum pad
size for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT−223 package, PD can be calculated as
follows:
PD =
PD =
150°C − 25°C = 3.13 watts
40°C/W
The 40°C/W for the SOT−223 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 3.13 watts.
There are other alternatives to achieving higher power
dissipation from the SOT−223 package. One is to increase
the area of the drain pad. By increasing the area of the drain
pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
one will be giving up area on the printed circuit board
which can defeat the purpose of using surface mount
technology.
Another alternative would be to use a ceramic substrate
or an aluminum core board such as Thermal Cladt. Using
a board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 3.13 watts.
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9
MMFT5P03HD
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177−189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
“SPIKE”
205° TO 219°C
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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10
MMFT5P03HD
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE K
A
F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
S
1
2
3
B
D
L
G
J
C
0.08 (0003)
M
H
K
INCHES
DIM MIN
MAX
A
0.249
0.263
B
0.130
0.145
C
0.060
0.068
D
0.024
0.035
F
0.115
0.126
G
0.087
0.094
H 0.0008 0.0040
J
0.009
0.014
K
0.060
0.078
L
0.033
0.041
M
0_
10 _
S
0.264
0.287
STYLE 3:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
6.30
6.70
3.30
3.70
1.50
1.75
0.60
0.89
2.90
3.20
2.20
2.40
0.020
0.100
0.24
0.35
1.50
2.00
0.85
1.05
0_
10 _
6.70
7.30
GATE
DRAIN
SOURCE
DRAIN
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