MPSW45, MPSW45A
One Watt Darlington
Transistors
NPN Silicon
http://onsemi.com
Features
• Pb−Free Packages are Available*
COLLECTOR 3
BASE
2
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector −Emitter Voltage
MPSW45
MPSW45A
VCES
40
50
Vdc
Collector −Base Voltage
MPSW45
MPSW45A
VCBO
50
60
Vdc
VEBO
12
Vdc
Collector Current − Continuous
IC
1.0
Adc
Total Device Dissipation @ TA = 25°C
Derate above 25°C
PD
1.0
8.0
W
mW/°C
Total Device Dissipation @ TC = 25°C
Derate above 25°C
PD
2.5
20
W
mW/°C
TJ, Tstg
−55 to +150
°C
Characteristic
Symbol
Max
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
125
°C/W
Thermal Resistance, Junction−to−Case
RqJC
50
°C/W
Emitter −Base Voltage
Operating and Storage Junction
Temperature Range
THERMAL CHARACTERISTICS
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
EMITTER 1
12
1
3
STRAIGHT LEAD
BULK PACK
2
3
BENT LEAD
TAPE & REEL
AMMO PACK
TO−92 1 WATT
(TO−226)
CASE 29−10
STYLE 1
MARKING DIAGRAM
MPS
W45x
AYWW G
G
MPSW45x = Device Code
x = 45A Devices
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
August, 2010 − Rev. 4
1
Publication Order Number:
MPSW45/D
MPSW45, MPSW45A
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
40
50
−
−
50
60
−
−
12
−
−
−
100
100
−
100
25,000
15,000
4,000
150,000
−
−
Unit
OFF CHARACTERISTICS
Collector −Emitter Breakdown Voltage
(IC = 100 mAdc, VBE = 0)
MPSW45
MPSW45A
Collector −Base Breakdown Voltage
(IC = 100 mAdc, IE = 0)
MPSW45
MPSW45A
Emitter −Base Breakdown Voltage
(IE = 10 mAdc, IC = 0)
V(BR)CES
V(BR)CBO
V(BR)EBO
Collector Cutoff Current
(VCB = 30 Vdc, IE = 0)
(VCB = 40 Vdc, IE = 0)
MPSW45
MPSW45A
Emitter Cutoff Current
(VEB = 10 Vdc, IC = 0)
ICBO
IEBO
Vdc
Vdc
Vdc
nAdc
nAdc
ON CHARACTERISTICS (Note 1)
DC Current Gain
(IC = 200 mAdc, VCE = 5.0 Vdc)
(IC = 500 mAdc, VCE = 5.0 Vdc)
(IC = 1.0 Adc, VCE = 5.0 Vdc)
hFE
−
Collector −Emitter Saturation Voltage
(IC = 1.0 Adc, IB = 2.0 mAdc)
VCE(sat)
−
1.5
Vdc
Base−Emitter Saturation Voltage
(IC = 1.0 Adc, IB = 2.0 mAdc)
VBE(sat)
−
2.0
Vdc
Base −Emitter On Voltage
(IC = 1.0 Adc, VCE = 5.0 Vdc)
VBE(on)
−
2.0
Vdc
fT
100
−
MHz
Ccb
−
6.0
pF
SMALL−SIGNAL CHARACTERISTICS
Current−Gain − Bandwidth Product
(IC = 200 mAdc, VCE = 5.0 Vdc, f = 100 MHz)
Collector−Base Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz)
1. Pulse Test: Pulse Width v 300 ms; Duty Cycle v 2.0%.
RS
in
en
IDEAL
TRANSISTOR
Figure 1. Transistor Noise Model
http://onsemi.com
2
MPSW45, MPSW45A
NOISE CHARACTERISTICS
(VCE = 5.0 Vdc, TA = 25°C)
500
2.0
BANDWIDTH = 1.0 Hz
RS ≈ 0
i n, NOISE CURRENT (pA)
en, NOISE VOLTAGE (nV)
200
BANDWIDTH = 1.0 Hz
100
10 mA
50
100 mA
20
IC = 1.0 mA
10
1.0
0.7
0.5
IC = 1.0 mA
0.3
0.2
100 mA
0.1
0.07
0.05
10 mA
0.03
0.02
10 20
5.0
10 20
50 100 200
500 1k 2k 5k 10k 20k
f, FREQUENCY (Hz)
50k 100k
50 100 200
Figure 3. Noise Current
14
200
BANDWIDTH = 10 Hz TO 15.7 kHz
12
BANDWIDTH = 10 Hz TO 15.7 kHz
100
NF, NOISE FIGURE (dB)
VT, TOTAL WIDEBAND NOISE VOLTAGE (nV)
Figure 2. Noise Voltage
500 1k 2k 5k 10k 20k 50k 100k
f, FREQUENCY (Hz)
IC = 10 mA
70
50
100 mA
30
20
1.0 mA
10
1.0
2.0
10
10 mA
8.0
100 mA
6.0
4.0
IC = 1.0 mA
2.0
5.0
10
20
50 100 200
RS, SOURCE RESISTANCE (kΩ)
500
1000
0
1.0
Figure 4. Total Wideband Noise Voltage
2.0
5.0
10
20
50 100 200
RS, SOURCE RESISTANCE (kΩ)
Figure 5. Wideband Noise Figure
http://onsemi.com
3
500
1000
MPSW45, MPSW45A
SMALL−SIGNAL CHARACTERISTICS
20
|h fe |, SMALL-SIGNAL CURRENT GAIN
4.0
TJ = 25°C
C, CAPACITANCE (pF)
10
7.0
Cibo
Cobo
5.0
3.0
2.0
0.04
0.1
0.2
0.4
1.0 2.0 4.0
VR, REVERSE VOLTAGE (VOLTS)
10
20
VCE = 5.0 V
f = 100 MHz
TJ = 25°C
2.0
1.0
0.8
0.6
0.4
0.2
0.5
40
1.0
200k
hFE, DC CURRENT GAIN
TJ = 125°C
100k
70k
50k
25°C
30k
20k
10k
7.0k
5.0k
-55°C
VCE = 5.0 V
3.0k
2.0k
5.0 7.0
10
20 30
50 70 100
200 300
IC, COLLECTOR CURRENT (mA)
500
TJ = 25°C
2.5
IC = 10 mA
RθV, TEMPERATURE COEFFICIENTS (mV/°C)
TJ = 25°C
1.4
V, VOLTAGE (VOLTS)
50 mA
250 mA
500 mA
2.0
1.5
1.0
0.5
0.1 0.2
0.5 1.0 2.0 5.0 10 20 50
IB, BASE CURRENT (mA)
100 200
500 1000
Figure 9. Collector Saturation Region
1.6
VBE(sat) @ IC/IB = 1000
1.2
VBE(on) @ VCE = 5.0 V
1.0
0.8
VCE(sat) @ IC/IB = 1000
0.6
10
500
3.0
Figure 8. DC Current Gain
5.0 7.0
0.5 10 20
50
100 200
IC, COLLECTOR CURRENT (mA)
Figure 7. High Frequency Current Gain
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 6. Capacitance
2.0
20 30
50 70 100 200 300
IC, COLLECTOR CURRENT (mA)
500
-1.0
-2.0
*APPLIES FOR IC/IB ≤ hFE/3.0
25°C TO 125°C
*RqVC FOR VCE(sat)
-55°C TO 25°C
-3.0
25°C TO 125°C
-4.0
qVB FOR VBE
-5.0
-55°C TO 25°C
-6.0
5.0 7.0 10
Figure 10. “On” Voltages
20 30
50 70 100
200 300
IC, COLLECTOR CURRENT (mA)
Figure 11. Temperature Coefficients
http://onsemi.com
4
500
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
MPSW45, MPSW45A
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
0.05
0.1
SINGLE PULSE
0.1
0.07
0.05
SINGLE PULSE
ZθJC(t) = r(t) • RθJCTJ(pk) - TC = P(pk) ZθJC(t)
ZθJA(t) = r(t) • RθJATJ(pk) - TA = P(pk) ZθJA(t)
0.03
0.02
0.01
0.1
0.2
0.5
1.0
2.0
10
5.0
20
50
t, TIME (ms)
100
200
500
1.0k
2.0k
5.0k
10k
Figure 12. Thermal Response
IC, COLLECTOR CURRENT (mA)
1.0k
700
500
FIGURE A
1.0 ms
tP
300
TC = 25°C
TA = 25°C
200
100 ms
PP
1.0 s
100
70
50
PP
t1
30
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
20
10
0.4 0.6
1/f
t
DUTYCYCLE + t1f + 1
tP
PEAK PULSE POWER = PP
40
1.0
2.0
4.0 6.0
10
20
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 13. Active Region Safe Operating Area
Design Note: Use of Transient Thermal Resistance Data
ORDERING INFORMATION
Package
Shipping†
MPSW45G
TO−92
(Pb−Free)
5,000 Units / Box
MPSW45RLREG
TO−92
(Pb−Free)
2,000 / Tape & Reel
TO−92
5,000 Units / Box
TO−92
(Pb−Free)
5,000 Units / Box
TO−92
2,000 / Tape & Reel
TO−92
(Pb−Free)
2,000 / Tape & Reel
TO−92
2,000 / Ammo Pack
TO−92
(Pb−Free)
2,000 / Ammo Pack
Device
MPSW45A
MPSW45AG
MPSW45ARLRA
MPSW45ARLRAG
MPSW45AZL1
MPSW45AZL1G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
SCALE 1:1
12
3
STRAIGHT LEAD
1
DATE 05 MAR 2021
2
3
BENT LEAD
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
TO−92 (TO−226) 1 WATT
CASE 29−10
ISSUE D
DATE 05 MAR 2021
STYLE 1:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 2:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 3:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 6:
PIN 1. GATE
2. SOURCE & SUBSTRATE
3. DRAIN
STYLE 7:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 8:
PIN 1. DRAIN
2. GATE
3. SOURCE & SUBSTRATE
STYLE 9:
PIN 1. BASE 1
2. EMITTER
3. BASE 2
STYLE 10:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 11:
PIN 1. ANODE
2. CATHODE & ANODE
3. CATHODE
STYLE 12:
PIN 1. MAIN TERMINAL 1
2. GATE
3. MAIN TERMINAL 2
STYLE 13:
PIN 1. ANODE 1
2. GATE
3. CATHODE 2
STYLE 14:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
STYLE 15:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
STYLE 16:
PIN 1. ANODE
2. GATE
3. CATHODE
STYLE 17:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
STYLE 18:
PIN 1. ANODE
2. CATHODE
3. NOT CONNECTED
STYLE 19:
PIN 1. GATE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. NOT CONNECTED
2. CATHODE
3. ANODE
STYLE 21:
PIN 1. COLLECTOR
2. EMITTER
3. BASE
STYLE 22:
PIN 1. SOURCE
2. GATE
3. DRAIN
STYLE 23:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 24:
PIN 1. EMITTER
2. COLLECTOR/ANODE
3. CATHODE
STYLE 25:
PIN 1. MT 1
2. GATE
3. MT 2
STYLE 26:
PIN 1.
2.
3.
STYLE 27:
PIN 1. MT
2. SUBSTRATE
3. MT
STYLE 28:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 29:
PIN 1. NOT CONNECTED
2. ANODE
3. CATHODE
STYLE 30:
PIN 1. DRAIN
2. GATE
3. SOURCE
STYLE 32:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
STYLE 33:
PIN 1. RETURN
2. INPUT
3. OUTPUT
STYLE 34:
PIN 1. INPUT
2. GROUND
3. LOGIC
STYLE 35:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
VCC
GROUND 2
OUTPUT
STYLE 31:
PIN 1. GATE
2. DRAIN
3. SOURCE
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON52857E
TO−92 (TO−226) 1 WATT
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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