MPSW56RLRPG

MPSW55, MPSW56 One Watt Amplifier Transistors PNP Silicon http://onsemi.com Features • Pb−Free Packages are Available* COLLECTOR 3 2 BASE MAXIMUM RATINGS Rating Symbol Value Unit Collector −Emitter Voltage MPSW55 MPSW56 VCEO −60 −80 Vdc Collector −Base Voltage MPSW55 MPSW56 VCBO −60 −80 Vdc VEBO −4.0 Vdc Collector Current − Continuous IC −500 mAdc Total Device Dissipation @ TA = 25°C Derate above 25°C PD 1.0 8.0 W mW/°C Total Device Dissipation @ TC = 25°C Derate above 25°C PD 2.5 20 W mW/°C TJ, Tstg −55 to +150 °C Characteristic Symbol Max Unit Thermal Resistance, Junction−to−Ambient RqJA 125 °C/W Thermal Resistance, Junction−to−Case RqJC 50 °C/W Emitter −Base Voltage Operating and Storage Junction Temperature Range 1 EMITTER 1 12 3 STRAIGHT LEAD BULK PACK 2 3 BENT LEAD TAPE & REEL AMMO PACK TO−92 1 WATT (TO−226) CASE 29−10 STYLE 1 MARKING DIAGRAM THERMAL CHARACTERISTICS Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MPS W5x AYWW G G x = 5 or 6 A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† MPSW55G TO−92 (Pb−Free) 5000 Units/Bulk MPSW55RLRAG TO−92 (Pb−Free) 2000/Tape & Reel TO−92 2000/Ammo Pack TO−92 (Pb−Free) 2000/Ammo Pack MPSW56RLRP MPSW56RLRPG *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 August, 2010 − Rev. 4 1 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MPSW55/D MPSW55, MPSW56 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max −60 −80 − − −4.0 − − − −0.5 −0.5 − − −0.1 −0.1 − −0.1 100 50 − − − −0.5 − −1.2 50 − − 15 Unit OFF CHARACTERISTICS Collector −Emitter Breakdown Voltage (Note 1) (IC = −1.0 mAdc, IB = 0) MPSW55 MPSW56 Emitter −Base Breakdown Voltage (IE = −100 mAdc, IC = 0) V(BR)CEO V(BR)EBO Collector Cutoff Current (VCE = −40 Vdc, IB = 0) (VCE = −60 Vdc, IB = 0) MPSW55 MPSW56 Collector Cutoff Current (VCB = −40 Vdc, IE = 0) (VCB = −60 Vdc, IE = 0) MPSW55 MPSW56 ICES ICBO Emitter Cutoff Current (VEB = −3.0 Vdc, IC = 0) IEBO Vdc Vdc mAdc mAdc mAdc ON CHARACTERISTICS(1) DC Current Gain (IC = −50 mAdc, VCE = −1.0 Vdc) (IC = −250 mAdc, VCE = −1.0 Vdc) hFE Collector −Emitter Saturation Voltage (IC = −250 mAdc, IB = −10 mAdc) VCE(sat) Base−Emitter On Voltage (IC = −250 mAdc, VCE = −5.0 Vdc) VBE(on) − Vdc Vdc SMALL−SIGNAL CHARACTERISTICS fT Current −Gain — Bandwidth Product (IC = −250 mAdc, VCE = −5.0 Vdc, f = 20 MHz) Output Capacitance (VCB = −10 Vdc, f = 1.0 MHz) Cobo MHz pF 1. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%. 400 hFE, DC CURRENT GAIN TJ = 125°C VCE = -1.0 V 200 25°C -55°C 100 80 60 40 -0.5 -0.7 -1.0 -2.0 -3.0 -5.0 -7.0 -10 -20 -30 IC, COLLECTOR CURRENT (mA) Figure 1. DC Current Gain http://onsemi.com 2 -50 -70 -100 -200 -300 -500 -1.0 -1.0 TJ = 25°C TJ = 25°C -0.8 -0.8 -0.6 IC = -10 mA -50 mA -100 mA -250 mA V, VOLTAGE (VOLTS) VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) MPSW55, MPSW56 -500 mA -0.4 -0.2 VBE(sat) @ IC/IB = 10 -0.6 VBE(on) @ VCE = -1.0 V -0.4 -0.2 VCE(sat) @ IC/IB = 10 0 -0.05 -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 IB, BASE CURRENT (mA) -10 -20 0 -0.5 -1.0 -50 -2.0 100 -0.8 70 -1.2 TJ = 25°C Cibo 50 -1.6 qVB for VBE -2.0 30 20 10 -2.4 Cobo 7.0 -2.8 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100 -200 IC, COLLECTOR CURRENT (mA) 5.0 -0.1 -500 -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 VR, REVERSE VOLTAGE (VOLTS) Figure 4. Base−Emitter Temperature Coefficient -50 -100 Figure 5. Capacitance 200 VCE = -2.0 V TJ = 25°C IC, COLLECTOR CURRENT (mA) f, T CURRENT-GAIN — BANDWIDTH PRODUCT (MHz) -500 Figure 3. “On” Voltages C, CAPACITANCE (pF) θ VB, TEMPERATURE COEFFICIENT (mV/°C) Figure 2. Collector Saturation Region -5.0 -10 -20 -50 -100 -200 IC, COLLECTOR CURRENT (mA) 100 70 50 30 DUTY CYCLE ≤ 10% -2 k -5.0 -7.0 -10 -20 -30 -50 -70 -100 IC, COLLECTOR CURRENT (mA) -200 -100 -50 -10 -1.0 -200 100 ms -500 -20 20 -2.0 -3.0 1.0 ms -1 k Figure 6. Current−Gain — Bandwidth Product 1.0 s TA = 25°C TC = 25°C dc dc CURRENT LIMIT THERMAL LIMIT SECOND BREAKDOWN LIMIT MPSW55 MPSW56 -2.0 -5.0 -10 -20 -60 -80 -100 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 7. Active Region — Safe Operating Area http://onsemi.com 3 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−92 (TO−226) 1 WATT CASE 29−10 ISSUE D SCALE 1:1 12 3 STRAIGHT LEAD 1 DATE 05 MAR 2021 2 3 BENT LEAD STYLES AND MARKING ON PAGE 3 DOCUMENT NUMBER: DESCRIPTION: 98AON52857E TO−92 (TO−226) 1 WATT Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−92 (TO−226) 1 WATT CASE 29−10 ISSUE D DATE 05 MAR 2021 STYLES AND MARKING ON PAGE 3 DOCUMENT NUMBER: DESCRIPTION: 98AON52857E TO−92 (TO−226) 1 WATT Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com TO−92 (TO−226) 1 WATT CASE 29−10 ISSUE D DATE 05 MAR 2021 STYLE 1: PIN 1. EMITTER 2. BASE 3. COLLECTOR STYLE 2: PIN 1. BASE 2. EMITTER 3. COLLECTOR STYLE 3: PIN 1. ANODE 2. ANODE 3. CATHODE STYLE 4: PIN 1. CATHODE 2. CATHODE 3. ANODE STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE STYLE 6: PIN 1. GATE 2. SOURCE & SUBSTRATE 3. DRAIN STYLE 7: PIN 1. SOURCE 2. DRAIN 3. GATE STYLE 8: PIN 1. DRAIN 2. GATE 3. SOURCE & SUBSTRATE STYLE 9: PIN 1. BASE 1 2. EMITTER 3. BASE 2 STYLE 10: PIN 1. CATHODE 2. GATE 3. ANODE STYLE 11: PIN 1. ANODE 2. CATHODE & ANODE 3. CATHODE STYLE 12: PIN 1. MAIN TERMINAL 1 2. GATE 3. MAIN TERMINAL 2 STYLE 13: PIN 1. ANODE 1 2. GATE 3. CATHODE 2 STYLE 14: PIN 1. EMITTER 2. COLLECTOR 3. BASE STYLE 15: PIN 1. ANODE 1 2. CATHODE 3. ANODE 2 STYLE 16: PIN 1. ANODE 2. GATE 3. CATHODE STYLE 17: PIN 1. COLLECTOR 2. BASE 3. EMITTER STYLE 18: PIN 1. ANODE 2. CATHODE 3. NOT CONNECTED STYLE 19: PIN 1. GATE 2. ANODE 3. CATHODE STYLE 20: PIN 1. NOT CONNECTED 2. CATHODE 3. ANODE STYLE 21: PIN 1. COLLECTOR 2. EMITTER 3. BASE STYLE 22: PIN 1. SOURCE 2. GATE 3. DRAIN STYLE 23: PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 24: PIN 1. EMITTER 2. COLLECTOR/ANODE 3. CATHODE STYLE 25: PIN 1. MT 1 2. GATE 3. MT 2 STYLE 26: PIN 1. 2. 3. STYLE 27: PIN 1. MT 2. SUBSTRATE 3. MT STYLE 28: PIN 1. CATHODE 2. ANODE 3. GATE STYLE 29: PIN 1. NOT CONNECTED 2. ANODE 3. CATHODE STYLE 30: PIN 1. DRAIN 2. GATE 3. SOURCE STYLE 32: PIN 1. BASE 2. COLLECTOR 3. EMITTER STYLE 33: PIN 1. RETURN 2. INPUT 3. OUTPUT STYLE 34: PIN 1. INPUT 2. GROUND 3. LOGIC STYLE 35: PIN 1. GATE 2. COLLECTOR 3. EMITTER VCC GROUND 2 OUTPUT STYLE 31: PIN 1. GATE 2. DRAIN 3. SOURCE GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON52857E TO−92 (TO−226) 1 WATT Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 3 OF 3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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