MT9D115
MT9D115 1/5‐inch
System‐On‐a‐Chip (SOC)
CMOS Digital Image Sensor
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Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Typical Value
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Pixel Size
1.75 mm × 1.75 mm
Optical Format
1/5-inch
Array Format (Active)
1600 (H) × 1200 (V) = 1.92 Mp
Imaging Area
2.8 mm × 2.10 mm,
3.50 mm Diagonal (4:3 Aspect Ratio)
CRA
25°
Color Filter Array
RGB Bayer
Scan Mode
Progressive
Shutter
Electronic Rolling Shutter (ERS)
Input Clock Range
6–54 MHz
Output Pixel Clock Maximum
85 MHz
Output MIPI Data Rate Maximum
512 Mb/s
Max. Frame Rate
15 fps Full Res
30 fps 800 x 600
Responsivity
0.65 V/Lux−sec (550 nm)
Signal-to-Noise Ratio
39 dB (MAX)
Dynamic Range
63.9 dB (Pixel)
Supply Voltage
Digital
Analog
I/O
MIPI
1.8 V (Nominal)
2.8 V (Nominal)
1.8 V or 2.8 V (Nominal)
1.7−1.95 V
Power Consumption
196 mW (Note 1)
Operating Temperature Range
–30°C to 70°C (at Junction)
Package
Bare Die, CSP
•
•
•
•
•
•
•
1. Power consumption for typical voltages at 800 × 600 video mode.
•
Features
•
•
•
•
•
2 Mp Resolution (1600 (H) × 1200 (V))
1/5-inch Optical Format
Same or Better Image Quality Compared to MT9D112
Individual Module ID Support Through One-time Programmable
(OTP) Memory
Surface Fit Lens Correction (LC) to Compensate for Lens/Small
Pixel Vignetting and Corner Color Variations
© Semiconductor Components Industries, LLC, 2010
January, 2017 − Rev. 5
• Automatic Functions: Exposure, White
1
•
Balance, Black Level Offset Correction,
Flicker Detection and Avoidance, Color
Saturation Control, Defect Identification and
Correction, Aperture Correction, and GPIO
Programmable Controls: Exposure, White
Balance, Horizontal and Vertical Blanking,
Color, Sharpness, Gamma, Lens Shading
Correction, Horizontal and Vertical Image
Flip, Zoom, Windowing, Sampling Rates,
and GPIO
15 Frames per Second (fps) at
1600(H) × 1200 (V) with Moderate Pixel
Clock Frequency (≤ 64 MHz) to Minimize
Baseband Reception Interference and 30 fps
at 800 (H) × 600 (V)
2 × 2 Pixel Binning to Improve Low-light
Image Quality
Support for External LED or Xenon Flash
On-chip Phase-locked Loop (PLL) to
Minimize the Number of System Clocks
Low Power Modes to Prolong Battery Life
of Portable Devices
Fail-safe I/Os with Programmable Output
Slew Rate
Industry Standard Two-wire Serial Interface
for Controls
10-bit Parallel or MIPI Serial Interfaces for
Image Data
Applications
• Cellular Phones
• PC Cameras
• PDAs
Publication Order Number:
MT9D115/D
MT9D115
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
MT9D115EB3STC−CR
MT9D115W00STCK25AC1−750
Orderable Product Attribute Description
Die Sales, 200 mm Thickness
2 MP 1/5″ SOC
2 MP 1/5″ CIS SOC
Chip Tray without Protective Film
2 MP 1/5″ SOC
Wafer Sales, 750 mm Thickness
FUNCTIONAL DESCRIPTION
The ON Semiconductor MT9D115 is a 1/5-inch 2 Mp
CMOS digital image sensor with an integrated advanced
camera system. This camera system features
a microcontroller (MCU), a sophisticated image flow
processor (IFP), MIPI and parallel output ports (only one
output port can be used at a time). The microcontroller
manages all functions of the camera system and sets key
operation parameters for the sensor core to optimize the
quality of raw image data entering the IFP. The IFP will be
responsible for processing and enhancing the image.
The entire system-on-a-chip (SOC) has superior low-light
performance that is particularly suitable for PC camera
applications. The MT9D115 features ON Semiconductor’s
breakthrough low-noise CMOS imaging technology that
achieves near-CCD image quality (based on signal-to-noise
ratio and low-light sensitivity) while maintaining the
inherent size, cost, and integration advantages of CMOS.
The ON Semiconductor MT9D115 can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is
a 800 × 600 image size at 30 frames per second (fps),
assuming a 24 MHz input clock. It outputs 8-bit data, using
the parallel output port.
ARCHITECTURE OVERVIEW
The MT9D115 combines a 2 Mp sensor core with an IFP
to form a stand-alone solution for both image acquisition
and processing. Both the sensor core and the IFP have
internal registers that can be controlled by the user. In
normal operation, an integrated microcontroller
Sensor Core
autonomously controls most aspects of operation.
The processed image data is transmitted to the host system
either through the parallel or MIPI interface.
Figure 1 shows the major functional blocks of the
MT9D115.
Image Flow Processor (IFP)
Pixel Array
Color Pipeline
Output Interface
Formatter
MT9D115D00STCK25AC1−200
Product Description
FIFO
Part Number
Stats Engine
Internal Register Bus
POR
ROM
Microcontroller
Two-wire Serial IF
Microcontroller Unit (MCU)
System Control
Figure 1. MT9D155 Block Diagram
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SRAM
MIPI
Parallel
MT9D115
TYPICAL CONNECTION
RPULL-Up5
Slave
Two-wire
Serial
Interface
I/O
Power
MIPI
Power
TX
PLL
Power
Digital
Core
Power
Analog
Power
VDD_IO
VDDIO_TX8
VDD_PLL
VDD
VAA6
SDATA
VAA_PIX6
DOUT[7:0]
SCLK
SADDR
PIXCLK
Active LOW Reset
Standby Mode
External Clock In
(6−54 MHz)
General Purpose
I/Os (FLASH,
OE_BAR,
DOUT_LSB[1:0])
RESET_BAR
LINE_VALID
FRAME_VALID
STANDBY
OR4
EXTCLK
DOUT_N
DOUT_P
GPIO[3:0]3
VPP
CLK_N
CLK_P
7
DGND
To
Parallel
Camera
Port
GND_PLL
AGND
VDDIO_TX/VDD
VAA_PIX/
VDD_PLL/
VAA
GND_IO
VDD_IO
0.1 mF
0.1 mF
To
Serial
Camera
Port2
0.1 mF
Notes:
1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.
2. If a MIPI Interface is not required, the following pads must be left floating: DOUT_P, DOUT_N, CLK_P, and CLK_N.
3. The general purpose input/output (GPIO) pads can serve multiple features that can be reconfigured. The function and direction will vary
by applications.
4. Only one of the output modes (serial or parallel) can be used at any time.
5. ON Semiconductor recommends a resistor value of 1.5 kW to VDD_IO for the two-wire serial interface RPULL-UP; however, greater values
may be used for slower transmission speed.
6. VAA and VAA_PIX may be tied together. Although separate decoupling capacitors are recommended for VAA and VAA_PIX, decoupling
capacitors can be shared if one would like to reduce module size.
7. VPP is the one-time programmable memory (OTPM) programming voltage and should be left floating during normal operation.
8. 1.8 V supply shared by MIPI interface and VDD to reduce number of decoupling caps, hence, module size. VDDIO_TX must be connected
to a 1.8 V power supply source even though MIPI interface is not used.
9. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as possible to
the pad and that a 10 mF capacitor be placed nearby off-module. Actual values and results may vary depending on layout and design
considerations. Please follow ON Semiconductor’s recommended capacitor Recommendations.
10. VDD_PLL and VAA can share the same power source in which case GND_PLL must be connected to GND.
11. Internal pull-up in RESET_BAR pin and can be left floating when not connected.
Figure 2. Typical Configuration (Connection)
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MT9D115
DECOUPLING CAPACITOR RECOMMENDATIONS
It is important to provide clean, well-regulated power to
each power supply. The customer is ultimately responsible
for ensuring that clean power is provided for their own
designs because hardware design is influenced by many
factors, including layout, operating conditions, and
component selection.
The recommendations for capacitor placement and values
listed below are based on the ON Semiconductor internal
demo camera design and verified in hardware.
ON Semiconductor recommends the following, in order
of preference:
1. Mount 0.1 mF and 1 mF decoupling capacitors for
each power supply as close as possible to the pad
and place a 10 mF capacitor nearby off-module.
2. If module limitations allow for only six decoupling
capacitors for a three-regulator design (VDD1V2
tied to external regulator), use a 0.1 mF and 1 mF
capacitor for each of the three regulated supplies.
ON Semiconductor also recommends placing a
10 mF capacitor for each supply off-module, but
close to each supply.
3. If module limitations allow for only three
decoupling capacitors, use a 1 mF capacitor
(preferred) or a 0.1 mF capacitor for each of the
three regulated supplies. ON Semiconductor also
recommends placing a 10 mF capacitor for each
supply off-module but close to each supply.
4. Give priority to the VAA supply for additional
decoupling capacitors.
ON Semiconductor does not recommend inductive
filtering components.
Follow best practices when performing physical layout.
Refer to the AND9503/D.
SIGNAL DESCRIPTIONS
Table 3. SIGNAL DESCRIPTION AND DIRECTION
Name
Type
Description
STANDBY
Input
Hardware standby
EXTCLK
Input
External clock input
SADDR
Input
Two-wire interface device select address
SCLK
Input
Two-wire interface serial clock
RESET_BAR (Note 4)
Input
Hardware reset
CLK_N (Note 5)
Output
MIPI differential clock N
CLK_P (Note 5)
Output
MIPI differential clock P
DOUT_N (Note 5)
Output
MIPI differential data N
DOUT_P (Note 5)
Output
MIPI differential data P
DOUT[7:0] (Note 1)
Output
Parallel image data
FRAME_VALID (Note 1)
Output
Parallel pixel bus frame valid
LINE_VALID (Note 1)
Output
Parallel pixel bus line valid
PIXCLK (Note 1)
Output
Parallel pixel bus pixel clock
Bidirectional
Two-wire interface serial data
SDATA
GPIO_0/DOUT_LSB[0] (Note 2)
Bidirectional/Output
General-purpose I/O or LSB for Raw 10 data output during SOC Bypass
GPIO_1/DOUT_LSB[1] (Note 2)
Bidirectional/Output
General-purpose I/O or LSB for Raw 10 data output during SOC Bypass
GPIO_3/OE_BAR (Note 2)
Bidirectional/Output
General-purpose I/O or output enable
GPIO_2/FLASH (Note 2)
Bidirectional/Output
General-purpose I/O or flash control
VAA
Supply
Analog core power source 2.8 V nominal
VAA_PIX
Supply
Analog core power source 2.8 V nominal
VDD
Supply
Digital core power source 1.8 V nominal
VDD_IO
Supply
Digital IO power source 1.8 V or 2.8 V nominal
VDD_PLL
Supply
Digital PLL power source 2.8 V nominal
VDDIO_TX
Supply
Digital MIPI IO power source 1.8 V nominal.
1. In serial only mode, DOUT[7:0], PIXCLK, and GPIO[3:0] can be left floating by setting R0x0026[1] =1. If GPIO signals are required, DOUT[7:0]
and PIXCLK must be tied to DGND and OE_BAR must be tied to VDD_IO. GPIO_3 should be configured as an input for OE_BAR function
and set R0x001A[8] = 1.
2. GPIO can be left floating if not used and must be programmed as outputs.
3. Must be connected to VDD_IO, internal 100 kW typical at 2.8 V VDDIO used.
4. Can be left floating if not used.
5. Must be connected to VDD, even in designs where the MIPI interface is not used.
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MT9D115
ARCHITECTURE
The MT9D115 from ON Semiconductor is the
third-generation, two-megapixel camera SOC. It is
a microprocessor-based camera system that combines
a sensor core with an image flow processor (IFP) to form
a standalone solution that includes image acquisition and
processing. Both the sensor core and IFP have internal
registers that can be accessed by an external host. In normal
operation, the integrated system microprocessor
autonomously controls most aspects of operation.
The image data is transmitted to the external host system
either through a parallel bus or a serial MIPI interface (see
Figure 3).
To External Host
Always ON
Two-wire
Serial I/F
Slave
GPIO
Sensor
Core
Memory Data Bus
1 kB
Patch
RAM
Input to
IFP
Interface
Register Bus Master
DMA
MCU
Register Bus (ICB)
1 kB
Data
RAM
Peripheral Bus (SFR)
Instruction Bus
IFP
Math Coprocessor
Sleep Unit
24 kB
Code
ROM
Output
from IFP
Interface
Parallel
Figure 3. SOC Block Diagram
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5
Serial
MT9D115
The external host and the integrated microprocessor
(MCU) can both access all the internal resources (RAM and
registers). The external host always has higher priority. The
following sections briefly describe the functionality of each
key component of the system.
flicker detection/avoidance (FD), as well as control
functions such as sequencer, mode/context, and histogram
(see Table 4). The firmware consists of drivers, generally
one driver for each major automatic or control function (see
Figure 4).
Firmware
The firmware implements all automatic camera functions,
such as auto exposure (AE), auto white balance (AWB), and
Table 4. LIST OF DRIVERS
Name
Type
ID = 1
Sequencer
ID = 2
AE
ID = 3
AWB
ID = 4
Flicker Detection
ID = 7
Mode/Context
ID = 11
Histogram
Operation
Driver
Controls of camera main function
Auto exposure
Auto white balance
Flicker detection and avoidance
Context variables
Reduce image flare and analyze image histogram
Monitor
RAM
Mode
Control
Sequencer
Auto
White
Balance
Auto Function
Driver
Hardware
Description
STAT
Flicker
Avoidance
IFP
Auto
Exposure
Core
Figure 4. Firmware Architecture
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Output
MT9D115
External Host Interface (Two-wire Slave-only Interface)
There are 32K addressable 16-bit registers (that is, the
starting address of each register always falls into even
addresses) within the MT9D115 but not all of them are being
used (see Figure 5).
The MT9D115 will appear as a two-wire serial interface
slave to the external host. Its base address is selectable by the
external SADDR pin input (when SADDR = 0 then base
address = 0x78; when SADDR = 1 then base address = 0x7A).
SOC2 Regs
0x3400
SOC1 Regs
0x3210
CORE Regs
0x3012
GPIO Regs
0x1070
XDMA Regs
0x098C
RX_SS Regs
0x0102
SYSCTL Regs
0x0000
0x0000
1 KB
User-loadable Memory
1 KB
Driver Variables
Internal Memory Resource
16-bit
Figure 5. External Host Register Map
Serial Interface 2 (CSI−2) 1.0, which uses the electrical
characteristics and transfer protocols of the two-wire serial
interface specifications.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device to the external host which acts as a master
device. The master generates a clock (SCLK) that is an input
to the sensor and used to synchronize the transactions at the
interface.
Data is transferred between the master and the slave on
a bidirectional serial data bus (SDATA). Both SCLK and
SDATA are pulled up to VDD_IO off-chip by a 1.5 kW resistor.
Either the slave or master device can drive SDATA to LOW
− the interface determines which device is allowed to drive
SDATA at any given time.
The MT9D115 register reference provides detailed
register explanations. Although most registers are
self-explanatory, the next paragraphs contain enhanced
information about XDMA registers are worth explaining
here.
The XDMA registers allow the external host to indirectly
access the internal memory resources of the MT9D115,
which include the firmware driver variables. To access the
variables, use logical accesses provided by the XDMA
registers.
The external host interface is implemented through
a two-wire interface that enables direct read/write access to
hardware registers and indirect access to firmware variables
within the MT9D115. The interface is designed to be
compatible with the MIPI alliance standard for Camera
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7
MT9D115
Write Sequence
t SRTS
t SDS
t SCLK
t SRTH
SCLK
t STPS
t SHAW
t STPH
t AHSW
t SDH
SDATA
Write Start
Write
Address
Bit 7
Write
Address
Bit 0
Read Sequence
Register
Value
Bit 7
Ack
Register
Value
Bit 0
Ack
Stop
t SDSR
t SHAR
t SDHR
t AHSR
SCLK
SDATA
Read Start
Read
Address
Bit 7
Read
Address
Bit 0
Ack
Register
Value
Bit 7
Register
Value
Bit 0
Figure 6. Two-wire Serial Control Bus Timing
Table 5. TWO-WIRE SERIAL INTERFACE TIMING DATA
(fEXTCLK = 14 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; VDD_PHY = NA; TJ = 70°C;
CLOAD = 68.5 pF)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCLK
Serial Interface Input Clock
Frequency
100
–
400
kHz
tSCLK
Serial Interface Input Clock
Period
2.5
–
10
ms
SCLK Duty Cycle
33
50
50
%
–
–
300
ns
tSRTS
tr
Start Setup Time
Master Write to Slave
600
–
–
ns
tSRTH
Start Hold Time
Master Write to Slave
300
–
–
ns
tSDH
SDATA Hold
Master Write to Slave
5
–
900
ns
tSDS
SDATA Setup
Master Write to Slave
100
–
–
ns
SCLK/SDATA Rise Time
tSHAW
SDATA Hold to Ack
Master Write to Slave
150
–
–
ns
tAHSW
Ack Hold to SDATA
Master Write to Slave
150
–
–
ns
tSTPS
Stop Setup Time
Master Write to Slave
300
–
–
ns
tSTPH
Stop Hold Time
Master Write to Slave
600
–
–
ns
tSHAR
SDATA Hold to Ack
Master Read from Slave
300
–
–
ns
tAHSR
Ack Hold to SDATA
Master Read from Slave
300
–
–
ns
tSDHR
SDATA Hold
Master Read from Slave
300
–
650
ns
tSDSR
SDATA Setup
Master Read from Slave
300
–
–
ns
NOTE:
tR and tF are dependent on system-level parameters such as the value of pull-up resistor used, how the two-wire serial bus is routed,
whether there are other devices on the serial bus, and the strength of the supply used to pull-up the serial bus.
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MT9D115
Always-On Power Domain
varying the time interval between reset and readout. After
a row is read, data from the columns are sequenced through
an analog signal chain that provides offset correction and
gain, and then through an ADC. The output from the ADC
is a 10-bit value for each pixel in the array.
The pixel array contains optically active and
light-shielded (dark) pixels. The dark pixels provide data for
the offset-correction algorithms (black level control).
The sensor core contains a set of control and status
registers that can be used to control many aspects of the
sensor behavior including the frame size, exposure, and gain
settings. These registers are controlled by the firmware and
can be accessed through a two-wire serial interface. Register
values written to the sensor core can be overwritten by
firmware.
The output from the core is a Bayer pattern, where
alternate rows are a sequence of either green and red pixels
or blue and green pixels. The offset and gain stages of the
analog signal chain provide per-color control of the pixel
data.
A flash strobe output signal is provided to allow an
external xenon or LED light source to synchronize with the
sensor exposure time.
The always-on power domain (AOPD) provides an area
of functionality that will always be active while power is
applied to the MT9D115. The external host interface is
located in the AOPD. The domain also includes
miscellaneous clock and reset controls as well as
configuration registers for the sensor core, processor core,
clock configuration, and clock reset control. The
user-loadable patch memory is also included in this domain.
This memory will remain powered when the main core
power is shut down using the standby command.
Sensor Core
The sensor core of the MT9D115 is a progressive-scan
sensor that generates a stream of pixel data at a constant
frame rate, qualified by LINE_VALID (LV) and
FRAME_VALID (FV). The maximum pixel rate is 30 Mp/s,
corresponding to a pixel clock rate of 63.25 MHz. See
Figure 7 for a block diagram of the sensor core. It includes
a 2.0 Mp active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then
reading each row in turn. In the time interval between
resetting a row and reading that row, the pixels in the row
integrate incident light. The exposure is controlled by
Control Registers
PLL
Timing
and
Control
Active-pixel
Sensor ( APS )
Array
Gr and Gb
Channel
Analog
Processing
Gr and Gb
Red and Blue
ADC
Red and Blue
Channel
Sensor Core
Figure 7. Sensor Core Block Diagram
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9
Gr and Gb
Red and Blue
Digital
Processing
10-bit
Data Out
MT9D115
odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels.
Odd-numbered columns contain red and green pixels.
Pixel Array
The sensor core uses a Bayer color pattern (see Figure 8).
The even-numbered rows contain green and red pixels. The
Row Readout Direction
…
Column Readout Direction
Black Pixels
First Clear Pixel
…
Gr R
Gr R Gr
B Gb B Gb B
Gr R
Gr R Gr
B Gb B Gb B
Figure 8. Pixel Color Pattern Detail (Top Right Corner)
Default Readout Order
By convention, the sensor core pixel array is shown with
pixel (0,0) in the top right corner. This reflects the actual
layout of the array on the die. When the sensor is operating
in a system, the active surface of the sensor faces the scene
(see Figure 9).
When the image is read out of the sensor, it is read one row
at a time, with the rows and columns sequenced. By
convention, data from the sensor is shown with the first pixel
read out in the case of the sensor core in the top left corner.
Lens
Scene
Sensor (Rear View)
Row
Readout
Order
Column Readout Order
Pixel (0,0)
Figure 9. Imaging a Scene
Analog Processing
a global gain register is aliased as a WRITE of the same data
to the four associated color-dependent gain registers.
Integer digital gains in the range 0–7 can be programmed.
A digital gain of 0 sets all pixel values to 0 (the pixel data will
simply represent the value applied by the pedestal block).
Gain settings are updated in every frame by the MCU auto
functions such as AWB, AE, and FD. To make manual
adjustments to gain settings, the MCU automatic exposure
and automatic white balance adjustment features must be
disabled.
Analog Readout Channel
The sensor core features an analog readout channel, (see
Figure 7). The readout channel consists of a gain stage,
a sample-and-hold stage with black level calibration
capability, and a 10-bit ADC.
Gain Options
The MT9D115 provides per-color gain control as well as
the option of global gain control. The per-color and global
gain control can be used interchangeably. A WRITE to
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10
MT9D115
Integration Time
The integration time (exposure) of the MT9D115 is
controlled by variables. While coarse integration time
controls the integration duration in terms of row times, fine
integration time allows for sub-row times accuracy in terms
of pixel clocks. Integration time is updated in every frame by
the MCU auto feature. Disable the MCU auto features to
make manual adjustments to integration time.
Because of the basic operation of the Electronic Roller
Shutter (ERS), it is not advisable to set an integration time
that is greater than the frame time.
It is not necessary to reprogram the frame time on the
MT9D115 to make longer integration times available
because the frame time adjusts automatically. However,
long integration times increase the likelihood of image
degradation because of increased accumulation of dark
current.
If the integration time is changed while FV is asserted for
frame n, the first frame output using the new integration time
is frame (n + 2). The sequence is as follows:
1. During frame n, the new integration time is held in
the pending register.
2. At the start of frame (n + 1), the new integration
time is transferred to the live register. Integration
for each row of frame (n + 1) has been completed
using the old integration time.
3. The earliest time that a row can start integrating
using the new integration time is immediately after
that row has been read for frame (n + 1).
4. When frame (n + 2) is read out, it will have been
integrated using the new integration time.
PLL-Generated Master Clock
The PLL can generate a master clock signal whose
frequency is up to 85 MHz (input clock from 6 MHz through
54 MHz).
PLL Setup
Because the input clock frequency is unknown, the sensor
starts up with the PLL disabled. The PLL takes time to power
up. During this time, the behavior of its output clock signal
is not guaranteed. The PLL output frequency is determined
by two constants, M and N, and the input clock frequency.
VCO +
F in
2
M
N)1
PLL Output Frequency +
VCO
P1 ) 1
(eq. 1)
(eq. 2)
Digital Processing
Readout Options
The sensor core supports different readout options to
modify the image before it is sent to the IFP. The readout can
be limited to a specific window of the original pixel array.
For preview modes, the sensor core supports both
skipping and pixel averaging in x and y directions.
By changing the readout direction the image can be
flipped in the vertical direction and/or mirrored in the
horizontal direction.
Window Size
The image output size is set with registers x_addr_start,
x_addr_end, y_addr_start, and y_addr_end. The edge pixels
in the 1600 × 1200 array are present to avoid edge defects
and should not be included in the visible window. Binning
will change the image output size.
If the integration time is changed on successive frames,
each value written will be applied for a single frame; the
latency between writing a value and it affecting the frame
readout remains at two frames.
When the integration time and the gain are changed at the
same time, the gain update is held off by one frame so that
the first frame output with the new integration time also has
the new gain applied.
Readout Modes
Horizontal Mirror
When the sensor is configured to mirror the image
horizontally, the order of pixel readout within a row is
reversed, so that readout starts from x_addr_end and ends at
x_addr_start. Figure 10 shows a sequence of 6 pixels being
read out with normal readout and reverse readout. The SOC
corrects for this change in sensor core output.
External Generated Master Clock
If application does not use PLL, then the clock bypass bit
in R0x0014 must be set before exiting soft standby state as
follows:
1. Write 0x25F9 to R0x0014 to set clock bypass bit.
2. Delay min. of 100 ms.
3. Write 0x4028 to R0x0018 to exit from soft
standby state.
4. After successful exit from soft standby state,
disable the clock bypass bit by writing 0x21F9 to
R0x0014.
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MT9D115
LINE_VALID
Normal Readout
DOUT[9:0]
G0
(9:0)
R0
(9:0)
G1
(9:0)
R1
(9:0)
G2
(9:0)
R2
(9:0)
R2
(9:0)
G2
(9:0)
R1
(9:0)
G1
(9:0)
R0
(9:0)
G0
(9:0)
Reverse Readout
DOUT[9:0]
Figure 10. Six Pixels in Normal and Column Mirror Readout Modes
Vertical Flip
When the sensor is configured to flip the image vertically,
the order in which pixel rows are read out is reversed, so that
row readout starts from y_addr_end and ends at
y_addr_start. Figure 11 shows a sequence of six rows being
read out with normal readout and reverse readout. The SOC
corrects for this change in sensor core output.
FRAME_VALID
Normal Readout
DOUT[9:0]
Row0
(9:0)
Row1
(9:0)
Row2
(9:0)
Row3
(9:0)
Row4
(9:0)
Row5
(9:0)
Row5
(9:0)
Row4
(9:0)
Row3
(9:0)
Row2
(9:0)
Row1
(9:0)
Row0
(9:0)
Reverse Readout
DOUT[9:0]
Figure 11. Six Rows in Normal and Row Mirror Readout Modes
Column and Row Skip
The sensor core supports subsampling. Subsampling
reduces the amount of data processed by the analog signal
chain in the sensor and thereby allows the frame rate to be
increased. This reduces the amount of row and column data
processed and is equivalent to the skip2 readout mode
provided by earlier ON Semiconductor image sensors. Set
the proper image output and crop sizes before enabling
subsampling.
LINE_VALID
Normal Readout
DOUT[9:0]
G0
(9:0)
R0
(9:0)
G1
(9:0)
R1
(9:0)
G0
(9:0)
R0
(9:0)
G2
(9:0)
R2
(9:0)
G2
(9:0)
R2
(9:0)
G3
(9:0)
R3
(9:0)
LINE_VALID
Column Skip
Readout
DOUT[9:0]
Figure 12. Eight Pixels in Normal and Column Skip 2X Readout Modes
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MT9D115
Pixel Readouts
Figure 13 through Figure 16 show a sequence of data
being read out with no skipping, with x_odd_inc = 3 and
y_odd_inc = 1, with x_odd_inc = 1 and y_odd_inc = 3, and
with x_odd_inc = 3 and y_odd_inc = 3.
Y Incrementing
X Incrementing
Figure 13. Pixel Readout (No Skipping)
Y Incrementing
X Incrementing
Figure 14. Pixel Readout (x_odd_inc = 3, y_odd_inc = 1)
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MT9D115
Y Incrementing
X Incrementing
Figure 15. Pixel Readout (x_odd_inc = 1, y_odd_inc = 3)
Y Incrementing
X Incrementing
Figure 16. Pixel Readout (x_odd_inc = 3, y_odd_inc = 3)
Programming Restrictions when Skipping
When skipping is enabled as a viewfinder mode, and the
sensor is switched back and forth between full resolution and
skipping, keep line_length_pck constant. This allows the
same integration times to be used in each mode.
When subsampling is enabled, it might be necessary to
adjust the x_addr_end and y_addr_end settings. The values
for these registers must correspond with rows/ columns that
form part of the subsampling sequence. Use the following
rules to make the adjustment.
remainder + (addr_end * addr_start ) 1) AND 4
(eq. 3)
if (remainder ++ 0) addr_end + addr_end * 2
(eq. 4)
Table 6 shows the row address sequencing for normal and
subsampled (with y_odd_inc = 3) readout. The same
sequencing applies to column addresses for subsampled
readout. Because the subsampling sequence only reads half
of the rows and columns, there are two possible subsampling
sequences, depending upon the alignment of the start
address.
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MT9D115
Table 6. ROW ADDRESS SEQUENCING (SAMPLING)
Normal
Subsampled Sequence 1
Subsampled Sequence 2
0
0
No Data
1
1
No Data
2
No Data
2
3
No Data
3
4
4
No Data
5
5
No Data
6
No Data
6
7
No Data
7
Binning
The MT9D115 sensor core supports 2 × 1 and 2 × 2
analog binning (column binning, also called x-binning and
row/column binning, also called xy-binning). Binning has
many of the same characteristics as subsampling. However,
because binning gathers image data from all pixels in the
active window, rather than from a subset of pixels, it
achieves superior image quality and avoids the aliasing
artifacts that can be a characteristic side effect of
subsampling.
Enable binning by selecting the appropriate subsampling
settings (x_odd_inc = 3 and y_odd_inc = 1 for x-binning,
x_odd_inc = 3 and y_odd_inc = 3 for xy-binning) and
setting the appropriate binning bit in read_mode register. As
for subsampling, x_addr_end and y_addr_end might require
adjustment when binning is enabled.
The effect of the different subsampling settings is shown
in Figure 17 and in Figure 18.
Y Incrementing
X Incrementing
Figure 17. Pixel Readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1)
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MT9D115
Y Incrementing
X Incrementing
Figure 18. Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, xy_bin = 1)
Binning Limitations
Binning requires a different sequencing of the pixel array
and imposes different timing limits on the operation of the
sensor. In particular, xy-binning requires two READ
operations from the pixel array for each line of output data,
which has the effect of increasing the minimum line
blanking time.
As a result, when xy-binning is enabled, some of the
programming limits declared in the parameter limit registers
are no longer valid. In addition, the default values for some
of the manufacturer-specific registers need to be
reprogrammed. None of these adjustments are required for
x-binning. The sensor must be taken out of streaming mode
before switching between binned and non-binned operation.
The row addresses for various binning modes are shown in
Table 7.
Table 7. ROW ADDRESS SEQUENCING (BINNING)
Normal
Binning Sequence 1
Binning Sequence 2
0
0, 2
No Data
1
1, 3
No Data
2
No Data
2, 4
3
No Data
3, 5
4
4, 6
No Data
5
5, 7
No Data
6
No Data
6, 8
7
No Data
7, 9
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MT9D115
Raw Data Format
The sensor core image data is read out in a progressive
scan. Valid image data is surrounded by horizontal blanking
and vertical blanking, (see Figure 19). The amount of
horizontal blanking and vertical blanking is programmable.
LV is HIGH during the shaded region of the figure.
P0,1
P0,2
…
P0,0
P0,n
00 00 00 … 00 00 00
P0,1
P1,1
P2,1
…
P1,n−1
P1,n
00 00 00 … 00 00 00
…
P0,0
Valid Image
Horizontal Blanking
Pm−1,0 Pm−1,1 Pm−1,2 …
Pm−1,n
00 00 00 … 00 00 00
Pm,n
00 00 00 … 00 00 00
00 00 00 …
00 00 00
00 00 00 … 00 00 00
00 00 00 …
00 00 00
00 00 00 … 00 00 00
Pm,1
Pm,2
…
Pm,n−1
Vertical/Horizontal
Blanking
Vertical Blanking
…
Pm,0
Pm−1,n−1
00 00 00 …
00 00 00
00 00 00 … 00 00 00
00 00 00 …
00 00 00
00 00 00 … 00 00 00
Figure 19. Valid Image Data
Raw Data Timing
The sensor core output data is synchronized with the
PIXCLK output. When LV is HIGH, one pixel’s data is
output on the 10-bit DOUT output bus every PIXCLK period.
By default, the PIXCLK signal runs at the same frequency
as the master clock, and its falling edges occur one-half of
a master clock period after transitions on LV, FV, and
DOUT[9:0] (see Figure 20). This allows PIXCLK to be used
as a clock to sample the data. PIXCLK is continuously
enabled, even during the blanking period.
LINE_VALID
PIXCLK
Blanking
DOUT0−DOUT9
Valid Image Data
P0 (9:0)
P1 (9:0)
P2 (9:0)
P3 (9:0)
Blanking
P4 (9:0)
Figure 20. Pixel Data Timing Example
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17
Pn−1 (9:0)
Pn (9:0)
MT9D115
Input Interface to Image Flow Processor
a selection of test patterns sufficient for basic testing of the
IFP. Program variable (ID = 7, Offset = 0x66) followed by
REFRESH command to the sequencer in order to access
different test patterns (see Table 8).
Depending on which test pattern has been selected, the
user might need to program additional registers in order to
see the intended effects.
The input interface to the IFP is the front end of the IFP,
in which it will choose between the sensor core output or
a test pattern generator output. During normal operation,
a stream of raw Bayer image data from the sensor is
continuously fed into the IFP. For testing purposes, the test
generator output is selected. The generator provides
Table 8. AVAILABLE TEST PATTERNS
Test Pattern
Flat Field
Registers/Variables
mode_common
settings_test_mode
(ID = 7, Offset = 0x66) = 1
test_pxl_red (R0x0102) = 0x1ff
test_pxl_g1 (R0x0104) = 0x1ff
test_pxl_g2 (R0x0106) = 0x1ff
test_pxl_blue (R0x0108) = 0x1ff
Vertical Ramp
mode_common_
mode_settings
test_mode
(ID = 7, Offset = 0x66) = 2
Color Bar
mode_common_
mode_settings
test_mode
(ID = 7, Offset = 0x66) = 3
Vertical Stripes
mode_common
settings_test_mode
(ID = 7, Offset = 0x66) = 4
test_pxl_red (R0x0102) = 0x1ff
test_pxl_g1 (R0x0104) = 0x17d
test_pxl_g2 (R0x0106) = 0x000
test_pxl_blue (R0x0108) = 0x000
Pseudo-Random
mode_common_mode
settings_test_mode
(ID = 7, Offset = 0x66) = 5
Horizontal Stripes
mode_common
settings_test_mode
(ID = 7, Offset = 0x66) = 6
test_pxl_red (R0x0102) = 0x1ff
test_pxl_g1 (R0x0104) = 0x17d
test_pxl_g2 (R0x0106) = 0x000
test_pxl_blue (R0x0108) = 0x000
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Example
MT9D115
Image Flow Processor
different phases: pixel reconstruction, color rendering/
statistics collection, and digital scaling/output format.
Figure 21 shows a simplified IFP block diagram and the
operating color space at each processing phase.
Most IFP functions can be controlled directly by the
MCU. The external host will control it indirectly through the
driver variables. IFP processing can be broken into three
Pixel
Array
ADC
Raw Data Bypass
Test
Pattern
Generator
Pixel
Reconstruction
Digital
Gain
Control,
Shading
Correction
Black
Level
Subtraction
RAW 10
Defect Correction,
Noise Reduction,
Color Interpolation
8-bit
RGB
RGB to YUV
Statistics
Engine
Color
Correction
8-bit
YUV
Color Kill
Color
Rendering/
Statistics
Collection
Aperture
Correction
Gamma
Correction
(10-to-8 Lookup)
Scaler
Output Formatting
YUV to RGB
8-bit RGB
Output
FIFO
MIPI
Serial
Output
Figure 21. IFP Block Diagram
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19
Parallel
Output
Output
Format
Digital Scaling/
Output Format
MT9D115
the incomplete color information available for each pixel
with information extracted from an appropriate set of
neighboring pixels. The algorithm used to select this set and
extract the information seeks the best compromise between
preserving edges and filtering out high frequency noise in
flat field areas. The edge threshold can be set through
register settings.
Pixel Reconstruction (Lens Shading Correction)
First Black Level Subtraction and Digital Gain
Image stream processing starts with black level
subtraction and multiplication of all pixel values by
a programmable digital gain. Both operations can be
independently set to separate values for each color channel
(R, Gr, Gb, B). Independent color channel digital gain can
be adjusted with registers. Independent color channel black
level adjustments can also be made. If the black level
subtraction produces a negative result for a particular pixel,
the value of this pixel is set to “0”.
Aperture Correction
To increase image sharpness, a programmable 2D
aperture correction (sharpening filter) is applied to
color-corrected image data. The gain and threshold for 2D
correction can be defined through variable settings.
Shading Correction (SC)
Lenses tend to produce images whose brightness is
significantly attenuated near the edges. Other factors also
cause fixed pattern signal gradients in images captured by
image sensors. The cumulative result of all factors is known
as image shading. The MT9D115 has an embedded shading
correction module that can be programmed to counter the
shading effects on each individual R, Gb, Gr, and B color
signal.
Color Rendering/Statistics Collection (Color Correction)
Color Correction
To achieve good color fidelity of the IFP output,
interpolated RGB values of all pixels are subjected to color
correction. The IFP multiplies each vector of three pixel
colors by a 3 × 3 color correction matrix. The three
components of the resulting color vector are all sums of three
10-bit numbers. Because such sums can have up to 12
significant bits, the bit width of the image data stream is
widened to 12 bits per color (36 bits per pixel). The color
correction matrix can be programmed by the user or
automatically selected by the AWB algorithm implemented
in the IFP. Ideally, color correction should produce output
colors that are independent of the spectral sensitivity and
color crosstalk characteristics of the image sensor. The
optimal values of the color correction matrix elements
depend on those sensor characteristics and on the spectrum
of light incident on the sensor. The color correction variables
can be adjusted through register settings.
The Correction Function
Color-dependent solutions are calibrated using the sensor,
lens system, and an image of an evenly illuminated,
featureless grey calibration field. The color correction
functions can be derived from the resulting image.
The correction functions can then be applied to each pixel
value to equalize the response across the image as follows:
P corrected(row, col) + P sensor(row, col)
f(row, col)
(eq. 5)
where P are the pixel values and f is the color dependent
correction functions for each color channel.
Defect Correction
The IFP performs continuous defect correction that can
mask pixel array defects such as high dark-current (hot)
pixels and pixels that are darker or brighter than their
neighbors due to photo-response non-uniformity. The
module is edge-aware with exposure that is based on
configurable thresholds. The thresholds are changed
continuously based on the brightness of the current scene.
Image Cropping
By configuring the cropped and output windows to
various sizes, different zooming levels (for example 4X, 2X,
and 1X) can be achieved. The location of the cropped
window is also configurable so that panning is also
supported. A separate cropped window is defined for
context A and context B. In both contexts, the height and
width definitions for the output window must be equal to or
smaller than the cropped image.
Noise Reduction
Noise reduction can be enabled or disabled. Thresholds
can be set through register settings.
Gamma Correction
The gamma correction curve (see Figure 22) is
implemented as a piecewise linear function with 19 knee
points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64,
128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304,
2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit
ordinates are programmable through IFP registers.
The MT9D115 IFP includes a block for gamma correction
that can adjust its shape based on brightness to enhance the
performance under certain lighting conditions. Two custom
gamma correction tables can be uploaded, one
corresponding to a brighter lighting condition, the other
corresponding to a darker lighting condition. At power-up,
Color Interpolation and Edge Detection
In the raw data stream fed by the sensor core to the IFP,
each pixel is represented by a 10-bit integer number, which
can be considered proportional to the pixel’s response to
a one-color light stimulus, red, green, or blue, depending on
the pixel’s position under the color filter array. Initial data
processing steps − up to and including the defect correction
− preserve the one-color-per-pixel nature of the data stream.
After the defect correction, the data stream must be
converted to a three-colors-per-pixel stream appropriate for
standard color processing. The conversion is done by an
edge-sensitive color interpolation module. The module pads
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MT9D115
the IFP loads the two tables with default values. The final
gamma correction table used depends on the brightness of
the scene and can take the form of either uploaded tables or
an interpolated version of the two tables. A single
(non-adjusting) table for all conditions can also be used.
Gamma Correction
300
0.45
Output RGB, 8-bit
250
200
150
100
50
0
0
1000
2000
3000
4000
Input RGB, 12-bit
Figure 22. Gamma Correction Curve
The scaler performs pixel binning − divides each input
image into rectangular bins corresponding to individual
pixels of the desired output image, averages pixel values in
these bins, and assembles the output image from the bin
averages. Pixels lying on bin boundaries contribute to more
than one bin average; their values are added to bin-wide
sums of pixel values with fractional weights. The entire
procedure preserves all image information that can be
included in the downsized output image and filters out high
frequency features that could cause aliasing.
Use the image cropping and scaler module together to
implement a digital zoom and pan. If the scaler is
programmed to output images smaller than images coming
from the sensor core, zoom effect can be produced by
cropping the latter from their maximum size down to the size
of the output images. The ratio of these two sizes determines
the maximum attainable zoom factor. For example,
a 1600 × 1200 image rendered on a 250 × 150 display can
be zoomed up to eight times, because 1280/160 =
1024/128 = 8. A panning effect can be achieved by fixing
the size of the cropping window and moving it around the
pixel array.
Color Kill
A color kill circuit is included to remove high or low light
color artifacts. It affects only pixels whose luminance
exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the
difference between their luminance and the threshold.
Digital Scaling/Output Format
Special Effects
Special effects like negative image, sepia, or black and
white can be applied to the data stream at this point. These
effects can be enabled and selected by registers.
RGB to YUV Conversion
For further processing, the data is converted from RGB
color space to YUV color space.
YUV Color Filter
As an optional processing step, noise suppression by
one-dimensional low-pass filtering of Y and/or UV signals
is possible. A 3- or 5-tap filter can be selected for each signal.
Image Scaling
The IFP includes a scaler module to ensure that the size of
images output by the MT9D115 can be tailored to the needs
of all users. When enabled, this module performs rescaling
of incoming images − shrinks them to arbitrarily selected
width and height without reducing the field of view and
without discarding any pixel values.
YUV-to-RGB/YUV Conversion and Output Formatting
The YUV data stream emerging from the scaling module
can either exit the color pipeline as-is or be converted before
exit to an alternative YUV or RGB data format.
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MT9D115
Output Interface from IFP
Color Conversion Formulas
• Y’U’V’:
This conversion is ITU−R BT.601 scaled to make YUV
range from 0 through 255. This setting is recommended
for JPEG encoding and is the most popular.
GȀ ) 0.114
The output interface contains parallel image bus, MIPI
serial bus interfaces, and walking 1s connectivity test
generator.
Parallel and MIPI Output
The user can select to use either the serial MIPI output or
the 10-bit parallel output to transmit the data. Only one of the
output modes can be used at any time.
The parallel output can be used with an output FIFO
whose memory is shared with the MIPI output FIFO to retain
a constant pixel output clock independent from the scaling
factor.
When scaling the image or skipping lines, the data would
be generated in bursts and the pixel clock would turn on and
off in intervals, which might lead to EMI problems. The
output FIFO will group all active pixel data together so the
pixel clock can be run at a constant speed.
The MIPI output transmitter implements a serial
differential sub-LVDS transmitter capable of up to
512 Mb/s. It supports multiple formats, error checking, and
custom short packets. The MIPI clock is defined as half the
data rate frequency.
The virtual channel could be used by host MIPI RX
circuits to differentiate between preview and capture image
data if the FW changes the channel number when switching
between contexts. The host cannot adequately time this
switching of contexts and so cannot use channel number in
this way without FW support.
The hardware supports a configurable MIPI virtual
channel in the MIPI Control register (R0x3400). Firmware
provides two variables that allow the MIPI virtual channel
to be changed according to context (preview/A, capture/B).
The host can specify what channel is used for which context
through these variables.
(eq. 6)
YȀ + 0.299
RȀ ) 0.587
UȀ + 0.564
(BȀ * YȀ) ) 128
(eq. 7)
VȀ + 0.713
(RȀ * YȀ) ) 128
(eq. 8)
BȀ
There is an option where 128 is not added to U’V’.
• Y’Cb’Cr’ Using sRGB Formulas:
The MT9D115 implements the sRGB standard. This
option provides YCbCr coefficients for a correct 4:2:2
transmission.
NOTE: 16 < Y’< 235; 16 < Cb < 240; 16 < Cr < 240;
and 0 ≥ RGB ≥ 255
YȀ + (0.2126
RȀ ) 0.7152
GȀ ) 0.0722
BȀ)
(219ń256) ) 16
CbȀ + 0.5389
(BȀ * YȀ)
CrȀ + 0.635
(RȀ * YȀ)
(eq. 9)
(eq. 10)
(224ń256) ) 128
(eq. 11)
(224ń256) ) 128
• Y’U’V’ Using sRGB Formulas:
Similar to the previous set of formulas, but has YUV
spanning a range of 0 through 255.
YȀ + 0.2126
RȀ ) 0.7152
UȀ + 0.5389
(BȀ * YȀ) ) 128 +
+ * 0.1146
VȀ + 0.635
+ 0.5
GȀ ) 0.0722
RȀ * 0.3854
BȀ
(eq. 13)
GȀ ) 0.5
BȀ ) 128
(RȀ * YȀ) ) 128 +
RȀ * 0.4542
GȀ * 0.0458
(eq. 12)
(eq. 14)
BȀ ) 128
There is an option to disable adding 128 to U’V’. The
reverse transform is as follows:
RȀ + Y ) 1.5748
(V * 128)
GȀ + Y * 0.1873
(U * 128) * 0.4681
BȀ + Y ) 1.8556
(U * 128)
(eq. 15)
(V * 128) (eq. 16)
(eq. 17)
Table 9. DATA FORMATS SUPPORTED BY MIPI INTERFACE
NOTE:
Data Format
Data Type
YUV 422 8-bit
0x1E
565RGB
0x22
555RGB
0x21
444RGB
0x20
RAW8
0x2A
RAW10
0x2B
Data will be packed as RAW8 if the data type specified does not match any of the above data types.
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MT9D115
Output Format and Timing
High pixel clock frequency during bursts may be
undesirable due to EMI concerns.
Figure 23 shows the output timing of a YUV/RGB scan
line when a scaled data stream is equalized by buffering or
when no scaling takes place. The pixel clock frequency
remains constant during each LV high period. Scaled data is
output at a lower frequency than full size frames, which
helps to reduce EMI.
YUV/RGB Output
YUV or RGB data can be output either directly from the
output formatting block or through a FIFO buffer with
a capacity of 1024 bytes. This size is large enough to hold
one-fourth of a scan line at full resolution. Buffering of data
is a way to equalize the data output rate when image scaling
is used. Scaling produces an intermittent data stream
consisting of short high-rate bursts separated by idle periods.
FRAME_VALID
LINE_VALID
PIXCLK
DOUT[7:0]
Figure 23. Timing of Full Frame Data or Scaled Data Passing through the FIFO
YUV/RGB Data Ordering
The MT9D115 supports swapping YCbCr mode
(see Table 10).
Table 10. YCbCr OUTPUT DATA ORDERING
Mode
Data Sequence
Default (No Swap)
Cbi
Yi
Cri
Yi+1
Swapped CrCb
Cri
Yi
Cbi
Yi+1
Swapped YC
Yi
Cbi
Yi+1
Cri
Swapped CrCb, YC
Yi
Cri
Yi+1
Cbi
The RGB output data ordering in default mode is shown
in Table 11. The odd and even bytes are swapped when
luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Table 11. RGB ORDERING IN DEFAULT MODE
Mode (Swap Disabled)
Byte
D7 D6 D5 D4 D3 D2 D1 D0
565RGB
Odd
R7 R6 R5 R4 R3 G 7 G 6 G 5
Even
G4 G3 G2 B7 B6 B5 B4 B3
555RGB
444xRGB
x444RGB
Odd
0 R7 R6 R5 R4 R3 G7 G6
Even
G4 G3 G2 B7 B6 B5 B4 B3
Odd
R7 R6 R5 R4 G 7 G 6 G 5 G 4
Even
B7 B6 B5 B4 0 0 0 0
Odd
0 0 0 0 R7 R6 R5 R4
Even
G7 G6 G5 G4 B7 B6 B5 B4
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MT9D115
10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output
in bypass mode in two ways:
1. Using eight data output signals (DOUT[7:0]) and
GPIO[1:0]. The GPIO signals are the lowest two
bits of data.
2. Using only eight signals (DOUT[7:0]) and a special
8 + 2 data format, shown in Table 12.
Table 12. 2-BYTE RGB FORMAT
Byte
Bits Used
Bit Sequence
Odd Bytes
8 Data Bits
D9 D8 D7 D6 D5 D4 D3 D2
Even Bytes
2 Data Bits + 6 Unused Bits
0 0 0 0 0 0 D1 D0
FIFO
During normal pipeline operation, the output data rate is
determined by a number of factors: input image size, degree
of scaling, and sensor operation mode. As these parameters
change during normal sensor operation, output frequency
changes. This output frequency may generate RF noise,
interfering with the mobile device. By using an output FIFO
to maintain a constant output clock frequency, noise is easily
filtered out.
The FIFO accumulates data and after a certain number of
bytes are stored, it will output them in a single burst, making
sure that the data rate within the burst remains constant. This
approach utilizes a free-running clock, thus making possible
minimal RF interference.
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24
MT9D115
CONTROL FUNCTIONS
Sequencer: Camera Operating System
Each state has its configuration; therefore, the user should
set up the state configuration to customize the camera
configuration before executing the corresponding program
such as GO TO CAPTURE. A typical camera operating
scenario is:
1. Configure mode variables after hardware reset.
2. Configure preview mode.
3. Execute sensor REFRESH program.
4. Run in preview until shutter button is pressed.
5. Capture a frame.
The sequencer is a finite state machine that controls the
general operations of the camera and switching between
operating modes. Camera operation is organized in states
such as enter preview, preview, leave preview, enter capture,
and capture. The sequencer carries out a number of
commands such as run, go preview, go capture, refresh, and
refresh mode. The current state of the sequencer is indicated
in a variable seqr.state. To execute a command, the user must
set a particular command number in the variable seqr.cmd.
ON Semiconductor recommends that the external host
monitor seqr.state to know when to change resolution or
capture frames.
Refreshor Run
PREVIEW
Go capture
ENTER
PREVIEW
0X0018[2] = 1
LEAVE
PREVIEW
0X0018[2] = 0
Refresh mode
POR
INIT
Go preview
CHG MODE
TO PREVIEW
STANDBY
STANDBY
Go preview
1
NOTE:
Any state except INIT can
transition to Standby state
by either hard standby or
soft standby.
CHG MODE
TO CAPTURE
Refresh mode
STANDBY
STANDBY
Go capture
ENTER
CAPTURE
LEAVE
CAPTURE
CAPTURE
Go preview or Go capture
Refresh or Run
Figure 24. Sequencer Finite State Machine
Mode: Context Information
image processing will take the new values at the beginning
of the next frame acquired.
To control the output image size, the user can modify the
mode driver variables such as output_width_A,
output_height_A, output_width_B, and output_height_B.
The mode driver will automatically apply any appropriate
downscaling filter to achieve this output image size as well
as update the watermark of the output FIFO. It is important
to set up the sensor core to output an image equal to or larger
than the crop window size, which in turn is equal to or larger
than the desired output image size.
The mode driver reduces integration efforts by managing
most aspects of switching the two contexts. It remembers
vital register values for each image acquisition context and
loads these values to the appropriate registers in the IFP
upon context switching.
For the mode driver variables to take effect, the user
changes the variable values in the mode driver (ID = 7).
Upon the next mode change or sequencer’s REFRESH
command, these driver variable values will be loaded to the
appropriate physical sensor core and IFP registers. The
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25
MT9D115
CAMERA FUNCTIONS
Simple Rule-based Auto Exposure
classification with respect to its brightness, contrast, and
composure and then decides to increase, decrease, or keep
the original exposure target. It makes the most difference for
backlight and bright outdoor conditions.
The AE algorithm performs automatic adjustments of the
image brightness by controlling exposure time and analog
gains of the sensor core as well as digital gains applied to the
image.
Auto exposure is implemented by a firmware (FW) driver
that analyzes image statistics collected by the exposure
measurement engine, makes a decision, and programs the
sensor core and color pipeline to achieve the desired
exposure. The measurement engine subdivides the image
into 16 windows organized as a 4 × 4 grid.
An AE algorithm mode is available: average brightness
tracking (ABT).
The ABT AE uses a constant average tracking algorithm
where a target brightness value is compared to a current
brightness value, and the gain and integration time are
adjusted accordingly to meet the target requirement.
Accelerated Settling During Overexposure
The AE speed is direction-dependent. Transitioning from
overexposure to target can take more time than transitioning
from underexposure. The AE driver has a mode that speeds
up AE for overexposed scenes.
The AE driver counts the number of AE windows whose
average brightness is equal to or greater than some value,
250 by default. For a scene that has saturated regions, the
average luma is underestimated because of signal clipping.
The driver compensates underestimation by a factor that can
be defined.
Exposure Control
To achieve the required amount of exposure, the AE driver
adjusts the sensor integration time, gains, ADC reference,
and IFP digital gains. In addition, ae_base_target (ID = 2,
offset = 0x4F) is available for the user to adjust the overall
brightness of the scene.
AE Driver
DRT exposure mode is activated during preview. This
mode can also be enabled during video capture mode. The
DRT exposure mode relies on the statistics engine to track
speed and amplitude of the change of the overall luminance
in the selected windows of the image.
Backlight compensation is achieved by weighting the
luminance in the center of the image higher than the
luminance on the periphery. Other algorithm features
include the rejection of fast fluctuations in illumination
(time averaging), control of speed of response, and control
of the sensitivity to the small changes. While the default
settings are adequate in most situations, the user can
program target brightness, measurement window, and other
parameters.
The driver calculates image brightness based on average
luma values received from 16 programmable equal-size
rectangular windows forming a 4 × 4 grid. In preview mode,
16 windows are combined in two segments: central and
peripheral. The central segment includes four central
windows. All remaining windows belong to the peripheral
segment. Scene brightness is calculated as average luma in
each segment taken with certain weights.
The driver changes AE parameters (integration time,
gains, and so on) to drive brightness to the programmable
target. The value of the single step approach to the target
value can be controlled.
To avoid unwanted reaction of AE on small fluctuations
of scene brightness or momentary scene changes, the AE
driver uses a temporal filter for luma and a threshold around
the AE luma target. The driver changes AE parameters only
if the filtered luma is larger than the AE target step and
pushes the luma beyond the threshold.
Flicker Detection and Avoidance
Flicker occurs when the integration time is not an integer
multiple of the period of the light intensity. The automatic
flicker detection block does not compensate for the flicker,
but rather avoids it by detecting the flicker frequency and
adjusting the integration time.
To reject flicker, integration time is typically adjusted in
increments of steps. The incremental step specifies the
duration in row times equal to one flicker period. Thus,
flicker is rejected if integration time is kept to an integral
factor of the flicker period.
Flicker cannot be avoided for integration times below the
light intensity period (10 ms for 50 Hz environment).
Flicker shows up in the image as horizontal bars that roll
up or down. The MCU looks for these rolling bars using
a thin horizontal window, which outputs luma average and
is applied to 48 points in the upper half of the image. The
MCU repeats the same sampling on the next frame; 48
samples from the previous frame are subtracted from
corresponding samples from the current frame. Skipping
more frames between subtraction can be set by a variable.
The MCU then smooths the 48 sampling points, applies an
amplitude threshold to avoid false detection, and looks at the
resulting waveform. If flicker is present, the waveform
should have a frequency within the search range. Assuming
the flicker power is a sine wave, subtracting two frames
results in:
sin(wt) * sin(wt ) a) + 2
Evaluative Algorithm
A scene-evaluative AE algorithm is available for use in
snapshot mode. The algorithm performs scene analysis and
ǒa2Ǔ @ cosǒwt ) ǒa2ǓǓ
sin
which is a cosine wave of the original frequency.
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26
(eq. 18)
MT9D115
Auto White Balance
Histogram: Dark Level Adjustments, Low Light and
Tonal Controls
The MT9D115 has a built-in AWB algorithm designed to
compensate for the effects of changing spectra of the scene
illumination on the quality of the color rendition. The
algorithm consists of two major parts: a measurement
engine performing statistical analysis of the image and a
driver performing the selection of the optimal color
correction matrix, digital gains, and sensor core analog
gains. While default settings of these algorithms are
adequate in most situations, the user can reprogram the base
color correction matrices, place limits on color channel
gains, and control the speed of both matrix and gain
adjustments.
The histogram driver continually works to reduce image
flare and continually analyzes input image histogram and
dynamically adjusts the black level. When flare is present
(hence, the histogram does not contain dark tones), it causes
the driver to subtract a higher black level, thus regaining the
lost contrast. In certain situations, the scene may contain no
dark tones without flare. The histogram driver cannot
distinguish this situation and alters the black level just the
same, causing the image to have more contrast, which looks
acceptable in many situations.
Besides black level adjustments and low light scene
parameters, this driver also contains variables for the
preloaded and custom gamma tables.
Flash
To take a snapshot, the user must send a command that
changes the context from preview to snapshot. The typical
sequence of events after this command is:
1. The camera might turn on its LED flash, if it has
one and is required to use it. With the flash on, the
camera exposure and white balance are
automatically adjusted to the changed illumination
of the scene.
2. The camera captures one or more frames of
desired size. A camera equipped with a xenon
flash strobes while capturing images. When the
images are captured, the camera automatically
returns to context A and resumes running in
preview mode.
NOTE: This sequence of events can take up to 10
frames.
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27
MT9D115
OPTICS
Figure 25 shows the CRA versus image height.
CRA vs. Image Height Plot
CRA (Degrees)
CRA
(%)
(mm)
(deg)
0
0
0
5
0.088
2.22
30
10
0.175
4.39
28
15
0.263
6.54
26
20
0.350
8.68
24
25
0.438
10.79
22
30
0.525
12.86
20
35
0.613
14.87
18
40
0.700
16.78
16
45
0.788
18.56
14
50
0.875
20.17
12
55
0.963
21.59
10
60
1.050
22.79
65
1.138
23.74
70
1.225
24.43
75
1.313
24.85
80
1.400
25.02
85
1.488
24.96
90
1.575
24.71
95
1.663
24.31
100
1.750
23.85
MT9D115 CRA Characteristic
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
Image Height (%)
NOTE:
Image Height
110
ON Semiconductor recommends a 670 nm IR cut filter to achieve the best image quality; however, a 650 nm IR cut filter is acceptable.
Figure 25. CRA vs. Image Height
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28
MT9D115
POWER MODES
Power Application Sequence
ON Semiconductor recommends the following sequence
to maintain low power consumption during this process:
5. De-assert RESET_BAR for a minimum of 10
EXTCLK cycles.
6. After asserting the RESET_BAR, apply analog
supplies (VAA, VAA_PIX, and VDD_PLL) to the
image sensor.
7. After 6000 EXTCLK cycles from the end of
step 6, the image sensor will be in soft standby
state.
8. Communication with the sensor thorough two-wire
serial interface can start 1 EXTCLK after step 7.
CAUTION: Applying power to analog supplies prior to
applying digital and IO supplies or any
other failure to follow the correct power up
sequence may result in high current
consumption and die heating. This can
potentially result in performance and
reliability issues.
1. Ensure that STANDBY is de-asserted and
RESET_BAR is asserted.
2. Apply IO supply (VDD_IO) to the image sensor
and wait for the IO supply to be stable.
3. Minimum of 1 ms after IO supply is stable, apply
digital supply to the image sensor and wait.
4. Enable EXTCLK and wait for the EXTCLK signal
to stabilize.
In cases where the recommended procedure cannot be
followed, the following condition would affect the sensor’s
power consumption during the power application sequence:
• When analog supplies are applied prior to the digital
and IO supplies, high current consumption on the
analog supplies may be present.
t0
STANDBY
t4
RESET_BAR
VDD_IO
t1
t3
VDD
t2
EXTCLK
t5
VAA, VAA_PIX,
VDD_PLL,
t6
t7
Two-wire
Serial Bus
Figure 26. Power Application Sequence Timing
Table 13. POWER APPLICATION SEQUENCE TIMING
Symbol
Min
Typ
Max
Unit
t0
Delay from Stable RESET_BAR, STANDBY Signals to VDDIO Power Start
Parameter
0
–
–
ns
t1
Delay from Stable VDD_IO to VDD Start
1
–
–
ms
t2
Delay from Stable VDD Power to EXTCLK Start
0
–
–
ns
t3
Delay from EXTCLK Start to Stable EXTCLK
1
–
–
EXTCLK
t4
RESET_BAR Pulse Width
10
–
–
EXTCLK
t5
Delay from RESET_BAR De-asserting to Analog Power Supplies Start
1
–
–
EXTCLK
t6
Delay from Analog Power Stable to Soft Standby Mode
6000
–
–
EXTCLK
t7
Delay from Soft Standby Mode to First Two-wire Bus Transaction
1
–
–
EXTCLK
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29
MT9D115
Power-On Reset
The POR circuit will generate an internal reset when VDD
falls below 1.25 V (typical) for 1 ms (typical) period, as
shown in Figure 27 and described in Table 14.
The POR circuit reset and external RESET_BAR signals
are gated together to generate an internal reset for
MT9D115.
The sensor includes a power-on reset feature that initiates
a reset upon power-up. Even though this feature is included
on the device, it is advised that the user still manually assert
a hard reset upon power-up.
The MT9D115’s POR circuit generates internal reset only
and it will not generate the external reset signal through
RESET_BAR.
The POR circuit requires VDD ramp time to be less than
10 ms. If the ramp time is longer than 10 ms, the POR
operation is not guaranteed and external reset must be used.
t1
VTRIG_RISING
VDD
VTRIG_FALLING
Figure 27. Internal Power-On Reset
Table 14. POR PARAMETERS
Symbol
Definition
Min
Typ
Max
Unit
t1
Minimum VDD Spike Width below VTRIG_FALLING Considered to be a Reset
–
1
–
ms
VTRIG_RISING
VDD Rising Trigger Voltage
1.15
1.4
1.55
V
VTRIG_FALLING
VDD Falling Trigger Voltage
1
1.25
1.45
V
Hard Reset
and described in Table 15. All of the output signals will be
in High-Z state except the MIPI outputs, which will be
driven LOW.
The MT9D115 enters the reset state when the external
RESET_BAR signal is asserted LOW as shown in Figure 28
t1
t2
t4
t3
EXTCLK
RESET_BAR
SDATA
All Outputs
Mode
Data Active After Programming
by Host Processor
Data Active
Internal Boot Time
Reset
Figure 28. Hard Reset Operation
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30
Entering Standby Mode and
Two−wire serial interface is Ready
MT9D115
Table 15. HARD RESET SIGNAL TIMING
Symbol
Min
Typ
Max
Unit
t1
RESET_BAR Pulse Width
Definition
100
–
–
EXTCLK Cycles
t2
Active EXTCLK Required after RESET_BAR Asserted
10
–
–
EXTCLK Cycles
t3
Active EXTCLK Required before RESET_BAR De-asserted
10
–
–
EXTCLK Cycles
t4
Maximum Internal Boot Time
–
–
6000
EXTCLK Cycles
Soft Reset
The host processor can reset the MT9D115 using the
two-wire serial interface by writing to SYSCTL 0x001A.
Two types of soft reset are available. SYSCTL 0x001A[0]
is used to reset the MT9D115, which is similar to external
RESET_BAR signal.
1. Set SYSCTL 0x001A1:0] to 0x3 to initiate internal
reset cycle.
2. Wait 6000 EXTCLK cycles.
3. Reset SYSCTL 0x001A[0] to 0x0 for normal
operation.
t1
EXTCLK
SCLK
SDATA
Mode
Write Soft
Reset Command
Registers Reset
to Default Values
Reseting Registers
Figure 29. Soft Reset Operation
Table 16. SOFT RESET SIGNAL TIMING
Symbol
t1
Definition
Maximum Soft Reset Time
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31
Min
Typ
Max
Unit
−
–
6000
EXTCLKs
MT9D115
Power Removal Sequence
ON Semiconductor recommends using the following
method to remove the power supplies from the image sensor.
1. Put the image sensor into either hard standby or
soft standby mode as described in “Standby
Modes”.
2. Remove all digital and analog supplies.
t1
t2
STANDBY
ASSERTED
STANDBY
MODE
During step 2, the digital and analog supplies can be
removed safely either one by one or at the same time,
provided that step 1 is executed previously. To achieve
a known power down state in the sensor, execute step 1
before removing any power supplies during the power
removal process.
t3
EXTCLK
STANDBY
VAA
VDD
VDD_IO
Remove Power Supplies
Figure 30. Recommended Power Down Sequence
Table 17. POWER DOWN SIGNAL TIMING
Symbol
Parameter
Typ
Max
Unit
1 Frame + 40
–
–
EXTCLKs
t1
Standby Entry Complete
t2
Active EXTCLK Required after STANDBY Asserted
10
–
–
EXTCLKs
t3
Power Supply Removal can be in any Order and
Anytime after Completion of t2
0
–
–
EXTCLKs
Standby Modes
•
•
•
Min
consumption. All the two-wire serial interface settings and
firmware variables except patch codes, PLL configuration,
parallel/MIPI IO and context selections will be lost in this
mode. Starting up from this mode is equivalent to power up
and current context selections. The two-wire serial interface
will be inactive and the sensor must be started up by
de-asserting the STANDBY signal.
The MT9D115 supports three standby modes:
Soft standby
Low leakage hard standby
High leakage hard standby
For each mode, entry can be overridden by programming
the standby_control register. Patch codes, PLL
configurations, parallel and MIPI IO selections are retained
in all standby modes.
High Leakage Hard Standby(Without Loss of Variable Data)
High leakage hard standby mode (without the loss of
variable data) can also be achieved. This mode stores the
variables and state of the sensor before entering standby
(similar to soft standby). The power consumption is lower
than that of soft standby, with EXTCLK enabled, as internal
clocks are turned off, and the two-wire serial interface will
be inactive.
Because the high leakage hard standby mode (without the
loss of variable data) is also activated by STANDBY, the
en_vdd_dis_soft register needs to be programmed to
indicate the selection of this mode before STANDBY is
asserted. De-asserting STANDBY will cause the sensor to
Soft Standby
Soft standby can be enabled by register access; it disables
the sensor core and most of the digital logic. The two-wire
serial interface is still active and the MT9D115 can be
programmed through register commands. All register
settings and RAM content will be preserved. Soft standby
can be performed in any sequencer state.
Low Leakage Hard Standby
Hard standby mode uses the STANDBY signal to shut
down digital power (VDD) and ensure the lowest power
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32
MT9D115
come out of the standby mode. This also causes the sensor
to resume operation from the state before the STANDBY
signal was asserted. By default, asserting the STANDBY
signal causes the hard standby mode described above.
during hard standby mode. Two-wire serial interface and
IFP block shut down even when EXTCLK is running during
hard standby mode.
Hard Standby Mode
Entering Standby Mode
1. Assert STANDBY signal (HIGH).
The MT9D115 can enter hard standby mode by using
external STANDBY signal, as shown in Figure 31.
EXTCLK can be stopped to reduce the power consumption
Exiting Standby Mode
1. De-assert STANDBY signal (LOW).
2. Follow “Hard Reset”.
t4
t1
t2
t3
STANDBY
ASSERTED
STANDBY
MODE
EXTCLK
STANDBY
NOTE:
EXTCLK Disabled
EXTCLK Enabled
In hard standby mode, EXTCLK is automatically gated off, and the two-wire serial interface is not active.
Figure 31. Hard Standby Mode Operation
Table 18. HARD STANDBY SIGNAL TIMING
Symbol
Parameter
Min
Typ
Max
Unit
t1
Standby Entry Complete
1 Frame + 40
–
–
EXTCLKs
t2
Active EXTCLK Required after STANDBY Asserted
10
–
–
EXTCLKs
t3
Active EXTCLK Required before STANDBY De-asserted
10
–
–
EXTCLKs
t4
STANDBY Time
1 Frame + 120
–
–
EXTCLKs
Soft Standby Mode
2. Set SYSCTL 0x0018[0] to “1” to initiate standby
mode.
3. Check until SYSCTL 0x0018[14] changes to “1”
to indicate MT9D115 is in standby mode.
The MT9D115 can enter soft standby mode by writing to
a SYSCTL register through the two-wire serial interface, as
shown in Figure 32. EXTCLK can be stopped to reduce the
power consumption during soft standby mode. However,
since two-wire serial interface requires EXTCLK to operate,
ON Semiconductor recommends that EXTCLK run
continuously. If EXTCLK needs to be stopped,
ON Semiconductor recommends using hardware standby
mode.
Exiting Standby Mode
1. Reset SYSCTL 0x0018[0] to “0”.
2. Check until SYSCTL 0x0018[14] changes to “0”
to indicate the MT9D115 is out of standby mode.
Entering Standby Mode
1. SYSCTL 0x0018[3] must be set to “1” to activate
standby mode. This will generate an interrupt to
the MCU when SYSCTL 0x0018[0] is set to “1”.
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33
MT9D115
t4
t1
t2
t3
EXTCLK
SDATA
R0x0018[0]
Poll
Standby
Set R0x0018[0] = 1 R0x0018[14]
Mode
Mode
EXTCLK Disabled
EXTCLK Enabled
R0x0018[14] = 1
Figure 32. Soft Standby Mode Operation
Table 19. SOFT STANDBY SIGNAL TIMING
Symbol
Parameter
Min
Typ
Max
Unit
1 Frame + 40
–
−
EXTCLKs
t1
Standby Entry Complete (R0x18[14] = 1)
t2
Active EXTCLK Required after Soft Standby Activates
10
–
–
EXTCLKs
t3
Active EXTCLK Required before Soft Standby De-activates
10
–
–
EXTCLKs
t4
Minimum Standby Time
1 Frame + 120
–
–
EXTCLKs
Table 20. STATUS OF SIGNALS DURING DIFFERENT STATES
Signal
Reset
Post-Reset
Software Standby
Low Power Hard Standby
Power
Down
DOUT[7:0]
High-Z
High-Z
High-Z by Default
(configurable through OE_BAR or
two-wire serial interface register)
High-Z by Default
X
PIXCLK
High-Z
High-Z
High-Z by Default (configurable)
High-Z by Default
X
LV
High-Z
High-Z
High-Z by Default (configurable)
High-Z by Default
X
FV
High-Z
High-Z
High-Z by Default (configurable)
High-Z by Default
X
DOUT_N
0
0
0
0
X
DOUT_P
0
0
0
0
X
CLK_N
0
0
0
0
X
CLK_P
0
0
0
0
X
GPIO[3:0]
High-Z
High-Z
Depending on how the system uses
them as DOUT_LSB1/DOUT_LSB0/
FLASH/OE_BAR
Depending on how the system uses
them as DOUT_LSBs/FLASH/OE_BAR
X
SADDR
Input
Input
Input
Input
SDATA
Input
I/O
Input
Input
SCLK
Input
Input
Input
Input
NOTE:
X = “Don’t Care”
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34
MT9D115
OTHER FEATURES
One-time Programmable Memory (OTPM)
Programming the OTPM
Refer to AND9507/D: Programming OTP Memory to
program the OTP Memory.
The MT9D115 contains two bytes of OTPM, suitable for
storing module identification that can be programmed
during the module manufacturing process. Programming
the OTP memory requires the use of a high voltage at the VPP
pin. During normal operation, the VPP pin should be left
floating. The OTPM can be accessed through the two-wire
serial interface.
Reading the OTPM
Reading the OTPM data requires the sensor to be fully
powered and operational with its clock input applied. The
data can be read through a register from the two-wire serial
interface.
Power Supplies
RESET_BAR
EXTCLK
SCLK/SDATA
VDD
Information to be
programmed to the register
Initiate programming
and poll status bit
Read programmed
values for status
Figure 33. Sequence of Signals for OTPM Operation
GPIO and Output Enable Controls
GPIO[3] can also be configured as an input to be used as
an OE_BAR signal for the data bus.
The general purpose inputs are enabled or disabled
through register settings. Once enabled, all four inputs must
be driven to valid logic levels by external signals. The state
of the general purpose inputs can be read from a register.
General Purpose I/Os
The four GPIOs of the MT9D115 can be configured in
multiple ways. Each of the I/Os can be used as a simple
input/output that can be programmed from the host. The
status of the GPIO is read at power up and can be used as
a module ID to identify different module suppliers. In
addition, module ID can be stored in the OTP memory of the
sensor. Information on the OTP memory can be found in
“One-time Programmable Memory (OTPM)”.
If 10-bit RAW output is required, GPIO[1:0] can be
configured as bit 1 and bit 0 (the LSBs) of a 10-bit data bus.
GPIO[2] can be configured to output a flash pulse to
trigger an external xenon or LED flash or a shutter pulse to
control an external shutter.
Output Enable Control
When the parallel pixel data interface is enabled, its
signals can be switched asynchronously between being
driven and High-Z under signal or register control.
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35
MT9D115
GPIO CONTROL
The MT9D115 has four general purpose I/O (GPIO)
signals and that can be individually programmed to perform
various functions. Table 21 describes the GPIO registers and
variables.
Overview of GPIO Signals
• Extension of two lower data bits during 10-bit output
mode
• External flash control output
• External OE_BAR control input for parallel port
signals
Table 21. GPIO RELATED REGISTERS AND VARIABLES
Map
Address
Bits
Description
SYSCTL
0x001A
[8]
SYSCTL
0x001E
[6:4]
Controls the output slew rate of GPIO signals.
“111” programs the fastest slew rate. Refer to AC/DC specification in the data sheet for the
numbers. Default value is “000” for slowest slew rate.
SYSCTL
0x0024
[3:0]
The state of GPIO signals during power on. Read-only.
GPIO
0x1070
[12:9]
GPIO data port.
State of current GPIO signals can be read through this register.
GPIO
0x1074
[12:9]
GPIO Set command.
When GPIO is configured as output, setting this register to “1” will write “1” to GPIO port.
Use GPIO Clear command to clear.
GPIO
0x1076
[12:9]
GPIO Clear command.
When GPIO is configured as output, setting this register to “1” will write “0” to GPIO port.
Use GPIO Set command to set.
GPIO
0x1078
[12:9]
GPIO direction control for each GPIO signals.
0 = Output
1 = Input
After power-on, GPIO ports are in input mode.
GPIO[3] Enable.
GPIO[3] can be configured as an Output Enable pad.
0: GPIO[3] does not function as OE.
1: GPIO[3] functions as OE.
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36
MT9D115
ELECTRICAL SPECIFICATIONS
Absolute Maximum Rating
CAUTION: Table 22 shows stress ratings only, and functional operation of the device at these or any other conditions above
those indicated in the product specification is not implied. Stresses above those listed may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 22. MAXIMUM RATINGS
Symbol
VDD
VDD_IO_MAX
VAA_MAX
Parameter
Min
Max
Unit
Digital Core Supply Voltage
1.7
1.95
V
I/O Digital Voltage
–0.3
4.0
V
Analog Voltage
–0.3
4.0
V
VAA_PIX_MAX
Pixel Supply Voltage
–0.3
4.0
V
VDD_PLL_MAX
PLL Supply Voltage
–0.3
4.0
V
VIH_MAX
Input HIGH Voltage
–0.3
VDD_IO + 0.3
V
VIL_MAX
Input LOW Voltage
–0.3
–
V
T_OP
Operating Temperature (measured at junction)
–30
75
°C
T_ST
Storage Temperature
–40
85
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
I/O Parameters
Table 23. I/O PARAMETERS
(fEXTCLK = 6–54 MHz, VDD = VDDIO_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 25°C)
Symbol
Parameter
VIH
Input Logic HIGH Threshold
VIL
Input logic LOW threshold
Min
Typ
Max
Unit
VDD_IO – 0.3
–
VDD_IO + 0.3
V
– 0.1
–
0.6
V
VDD_IO = 2.8 V
– 0.1
–
0.3
V
VDD_IO = 1.8 V
–
–
V
At Specified at IOH
VOH
Output Logic HIGH Threshold
VDD_IO – 0.3
VOL
Output Logic LOW Threshold
–
–
0.3
V
CIN
Input Pins − (SCLK, SDATA)
Capacitance
–
3.5
3.9
pF
CLOAD
Output Pins − (SDATA) Load
Capacitance
–
–
30
pF
SDATA Pull-up Resistor
–
1.5
–
kW
PUP_SDATA
NOTE:
VIH and VIL specifications apply to the over- and undershoot (ringing) present in the MCLK.
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37
Note
MT9D115
MIPI Interface AC and DC Electrical Specifications
Introduction
The MIPI interface for the MT9D115 image sensor was
designed to meet the MIPI Alliance Specification for
D−PHY Version 1.0. Please refer to this document for details
on the MIPI specification and usage.
Electrical Specifications
Table 24. MIPI HIGH-SPEED TRANSMITTER DC CHARACTERISTICS
(fEXTCLK = 48 MHz; VDD = VDD_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Ambient Temperature)
Description
Parameter
VCMTX
|DVCMTX
(1,0)|
|VOD|
HS Transmit Static Common Mode Voltage
Min
Nom
Max
Unit
150
200
250
mV
−
−
16
mV
140
200
270
mV
−
14
mV
VCMTX Mismatch when Output is Differential−1 or
Differential−0
HS Transmit Differential Voltage
|DVOD|
VOD Mismatch when Output is Differential−1 or
Differential−0
VOHHS
HS Output High Voltage
−
−
360
mV
Single-ended Output Impedance
39
50
64
W
Single-ended Output Impedance Mismatch
−
−
10
%
ZOS
DZOS
Table 25. MIPI HIGH-SPEED TRANSMITTER AC CHARACTERISTICS
(fEXTCLK = 48 MHz; VDD = VDD_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Ambient Temperature)
Parameter
tR and tF
Description
Min
Nom
Max
Unit
20%−80% Rise Time and Fall Time
150
−
−
ps
Table 26. MIPI LOW-POWER TRANSMITTER DC CHARACTERISTICS
(fEXTCLK = 48 MHz; VDD = VDD_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Ambient Temperature)
Parameter
Description
Min
Nom
Max
Unit
VOH
Thevenin Output High Level
1.1
1.2
1.4
V
VOL
Thevenin Output Low Level
−50
−
50
mV
ZOLP
Output Impedance of LP Transmitter
110
−
−
W
Table 27. MIPI LOW-POWER TRANSMITTER ADC CHARACTERISTICS
(fEXTCLK = 48 MHz; VDD = VDD_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Ambient Temperature)
Parameter
Description
TRLP/TFLP
15%−85% Rise Time and Fall Time
TREOT
DV/DtSR
CLOAD
Min
Nom
Max
Unit
−
−
25
ns
30%−85% Rise Time and Fall Time
−
−
35
ns
Slew Rate @ CLOAD = 70 pF
83
−
122
mV/ns
Load Capacitance
0
−
70
pF
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MT9D115
AC Electricals
tR
tF
90%
90%
10%
10%
tEXTCLK
EXTCLK
tCP
PIXCLK
tPD
DOUT[7:0]
tPD
Data
Data
Data
Data
Data
tPFH
tPLH
tPFL
tPLL
LINE_VALID/
FRAME_VALID
Figure 34. Output Interface Timing Waveforms
Table 28. AC ELECTRICALS
(fEXTCLK = 6–54 MHz, VDD = VDDIO_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 25°C)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
6
−
54
MHz
fEXTCLK
(Note 2)
External Input Clock Frequency
tR (Note 1)
External Input Clock Rise Time
From10% to 90% of Vp-p
−
2
5
ns
tF (Note 1)
External Input Clock Fall Time
From10% to 90% of Vp-p
−
2
5
ns
40
50
60
%
DCEXTCLK
tJITTER
External Input Clock Duty Cycle
−
−
500
ps
EXTCLK to PIXCLK Propagation
Delay
5
−
45
ns
fPIXCLK
Pixel Clock Frequency
6
−
85
MHz
tRPIXCLK
Pixel Clock Rise Time
CLOAD = 15 pF
−
2
5
ns
tFPIXCLK
Pixel Clock Fall Time
CLOAD = 15 pF
−
2
5
ns
tCP (Note 3)
External Input Clock Jitter
Peak-to-Peak
tPD (Note 4)
Pixel Clock to Data Valid
−
−
0.6 * PIXCLK
ns
tPFH (Note 4)
Pixel Clock to Frame Valid High
−
−
0.6 * PIXCLK
ns
tPLH (Note 4)
Pixel Clock to Frame Valid Low
−
−
0.6 * PIXCLK
ns
tPFL (Note 4)
Pixel Clock to Line Valid High
−
−
0.6 * PIXCLK
ns
tPLL (Note 4)
Pixel Clock to Line Valid Low
PIXCLK Pin
Slew Rate
(Note 5)
Programmable Slew = 7
Programmable Slew = 4
Programmable Slew = 0
−
−
0.6 * PIXCLK
ns
VDD_IO = 2.8 V, CLOAD = 45 pF
−
1.2
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.6
−
V/ns
VDD_IO = 2.8 V, CLOAD = 45 pF
−
1
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.5
−
V/ns
VDD_IO = 2.8 V, CLOAD = 45 pF
−
0.3
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.15
−
V/ns
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MT9D115
Table 28. AC ELECTRICALS (continued)
(fEXTCLK = 6–54 MHz, VDD = VDDIO_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 25°C)
Symbol
Output Pin
Slew Rate
(Note 5)
Parameter
Programmable Slew = 7
Programmable Slew = 4
Programmable Slew = 0
1.
2.
3.
4.
5.
Condition
Min
Typ
Max
Unit
VDD_IO = 2.8 V, CLOAD = 45 pF
−
1.6
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.8
−
V/ns
VDD_IO = 2.8 V, CLOAD = 45 pF
−
1.25
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.55
−
V/ns
VDD_IO = 2.8 V, CLOAD = 45 pF
−
0.3
−
V/ns
VDD_IO = 1.8 V, CLOAD = 45 pF
−
0.15
−
V/ns
Measured when the PLL is off. Specification not applicable when PLL is on, but input HIGH/LOW voltage should be within specification.
VIH and VIL specifications apply to the over- and undershoot (ringing) present in the MCLK.
Measurement done with PLL off.
Valid for CLOAD < 20 pF on PIXCLK, DOUT[9:0], LINE_VALID, and FRAME_VALID pads. Loads must be matched as closely as possible.
PLL is off and EXTCLK is 24 MHz.
Table 29. DC ELECTRICALS
(fEXTCLK = 6–54 MHz, VDD = VDDIO_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 25°C, unless stated otherwise)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDD
Digital Core Supply
Voltage
1.7
1.8
1.95
V
VDD_PLL
PLL Supply Voltage
2.5
2.8
3.1
V
Analog Supply Voltage
2.5
2.8
3.1
V
VAA_PIX
VAA
Pixel Supply Voltage
2.5
2.8
3.1
V
VDD_IO
Digital IO Supply
Voltage
For VDD_IO = 1.8 V
1.7
1.8
1.95
V
For VDD_IO = 2.8 V
2.5
2.8
3.1
V
1.7
1.8
1.95
V
VDDIO_TX
VPP
IDD_IO
(Note 1)
MIPI Supply Voltage
OTPM Supply Voltage
Digital IO Supply
Current
−
8
−
V
VDD_IO =1.8 V
−
10
−
mA
VDD_IO = 2.8 V
−
15
−
mA
VDD_IO = 1.8 V
−
12
−
mA
VDD_IO = 2.8 V
−
20
−
mA
PLL is OFF
−
N/A
−
mA
PLL is ON (Note 2)
−
13
18
mA
−
15
30
mA
Context A
Context B
IDD_PLL
PLL Supply Current
IDD
Digital Core Supply
Current
IAA
Operating in Parallel Mode
Context A
Analog Supply Current
−
40
50
mA
IAA_PIX
Pixel Supply Current
−
1.5
3
mA
IDDIO_TX
MIPI Supply Current
(Note 3)
−
N/A
−
mA
IDD
Digital Core Supply
Current
−
25
52
mA
IAA
Analog Supply Current
−
40
52
mA
IAA_PIX
Pixel Supply Current
−
0.8
3
mA
IDDIO_TX
MIPI Supply Current
(Note 3)
−
N/A
−
mA
Context B
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MT9D115
Table 29. DC ELECTRICALS (continued)
(fEXTCLK = 6–54 MHz, VDD = VDDIO_TX = VDD_IO = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 25°C, unless stated otherwise)
Symbol
Parameter
Condition
Operating in Serial Mode
(Note 4)
Context A
Min
Typ
Max
Unit
−
23
50
mA
IDD
Digital Core Supply
Current
IAA
Analog Supply Current
−
40
50
mA
IAA_PIX
Pixel Supply Current
−
1.5
3
mA
IDDIO_TX
MIPI Supply Current
−
5
3
mA
IDD
Digital Core Supply
Current
−
35
70
mA
IAA
Analog Supply Current
−
40
70
mA
IAA_PIX
Pixel Supply Current
−
0.8
3
mA
IDDIO_TX
MIPI Supply Current
−
8
10
mA
Context B
STANDBY Pin Asserted, R0x0028 = 1 (Note 5)
−
−
20
mA
IHARDSTANDBY
STANDBY Pin Asserted, R0x0028 = 0 (Note 7)
−
−
90
mA
ISOFTSTANDBY
R0x0018[0] = 1 (Note 6)
−
−
90
mA
ISOFTSTANDBY
R0x0018[0] = 1, R0x0028 = 0 (Note 7)
−
−
2
mA
ISOFTSTANDBY
R0x0018[0] = 1, R0x0028 = 1 (Note 7)
−
−
3
mA
IHARDSTANDBY
1.
2.
3.
4.
5.
6.
7.
Total Standby Current
VDD_IO current is dependent on the output data rate.
PLL is on with 85 MHz output frequency setting.
VDD_IO_TX current is only applicable in serial output mode.
PLL is on with 480 MHz VCO frequency settings.
Either with EXTCLK running or EXTCLK stopped and EXCLK pin is either pulled up or pulled down. Measured at Tj = 70°C.
EXTCLK is stopped and EXCLK pin is either pulled up or pulled down.
EXTCLK running at 27 MHz.
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41
MT9D115
APPENDIX A − VDD_IO CURRENT ADDITION
Introduction
To achieve the lowest VDD_IO current, it is critical to
match VDD_IO level in the sensor and the controller.
Otherwise, there can be elevated current drawn on the
VDD_IO due to mismatch in termination voltage level on the
sensor pins. In ON Semiconductor system design, the IO
voltage between the sensor and the controller is matched by
using the same voltage regulator, as shown in Figure 35.
This is recommended for both the system design and setup
to measure the VDD_IO power consumption.
This appendix describes the system requirements to
achieve lowest power consumption in the VDD_IO domain
during low power hardware standby mode in
ON Semiconductor’s MT9D115 CMOS digital image
sensor.
VDD_IO Current
VDD_IO current is used to measure the power
consumption of the IO pad ring of our sensor. Therefore, it
is extremely system-dependent and greatly affected by the
external conditions as current can flow out of the chip
through the IO ring and into the system. In this document, we
outline requirements at the system level to achieve
minimum power consumption during low power hardware
standby mode.
Voltage
Regulator
VREG
MT9D115
Controller
2.2 kW
VIO_Controller
VDD_IO
SCLK
High-Z
SDATA
High-Z
RESET_BAR,
STANDBY
Drive HIGH
SADDR, EXTCLK
Drive LOW
PIXCLK, FRAME_VALID,
LINE_VALID, DOUT[7:0],
GPIO[1:0]
Input
GPIO[3:2]
GND
GND
Figure 35. Recommended System and Test Setup for Minimum VDD_IO Power Consumption
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42
GND
MT9D115
IO Pin States
states recommended to achieve minimum VDD_IO current
during hardware standby mode.
It is always a good practice to measure the pin voltage
during hard standby and try to match the recommended pin
state.
In addition to matching VDD_IO levels between the
controller chip and the sensor, the control signals to the input
pins of the sensor must be at a specified level to achieve
minimal VDD_IO current draw. Table 30 shows the pin
Table 30. STATUS OF SIGNALS DURING STANDBY STATE
Signal
DOUT[7:0]
ON Semiconductor Test System
High-Z by Default (configurable through OE_BAR or two-wire serial
interface register)
PIXCLK
High-Z by Default (configurable)
LINE_VALID
High-Z by Default (configurable)
FRAME_VALID
High-Z by Default (configurable)
GPIO[3:0]
1.
2.
3.
4.
5.
6.
7.
8.
9.
State on Sensor Pin
Depending on how the system uses them as
DOUT_LSB1/DOUT_LSB0/FLASH/OE_BAR
DOUT_N
0
DOUT_P
0
CLK_N
0
CLK_P
0
SADDR
Input
EXTCLK
Input
SDATA
Input
SCLK
Input
RESET_BAR
Input
STANDBY
Input
No Control
(Note 4)
Pulled to GND
(Note 8, 9)
Float
(Note 7)
Pulled to GND
(Note 1, 6)
High-Z
(Note 3)
Pulled to VDD_IO Level
(Notes 2, 5)
VIL specification for input signal applies. Refer to Table 21, “GPIO Related Registers and Variables”.
VIH specification for input signal applies. Refer to Table 21, “GPIO Related Registers and Variables”.
These pins are not directly connected to VDD_IO supply but through a voltage follower to the controller.
The pins on the controller connected to these sensor pins are input pins.
These pins are not directly connected to VDD_IO supply but through the controller.
These pins are not directly connected to GND but through the control signal on the controller.
These pins are floating in parallel mode operation.
Tie all the unused GPIO pins to DGND or VDD_IO level in the module.
If GPIO3 is connected to GPIO pin on the controller, program GPIO3 as an input before low power hard standby mode and drive GPIO3
externally from the controller to DGND level.
RESET_BAR with Internal Pull-Up
The RESET_BAR pin has an internal pull-up device to
VDD_IO (see Figure 36).
VDDIO
RESET_BAR Pad
Block Diagram
RPULLUP
Z
Rx
Hysteresis
Pad
Figure 36. RESET_BAR Pad Architecture
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MT9D115
Since RPULLUP is active devices connected in triode state,
the value of RPULLUP is dependent on the difference
between VDD_IO and VPAD Level (see Table 31).
Table 31. TYPICAL MISMATCH CURRENT IN VDD_IO DUE TO MISMATCH IN RESET_BAR LEVEL AND VDD_IO LEVEL
(Conditions: VDD = VDD_IO_TX = 1.8 V; VAA = VAA_PIX = VDD_PLL = 2.8 V; Tj = 30°C, EXTCLK is off and tied to GND level. All other pin
states and levels are set according to ON Semiconductor E2E on pin states.)
VDD_IO
VPAD
Min
Typ
Max
Unit
1.80
1.70
14
18
22
mA
1.80
2
5
10
1.95
–13
–17
–21
2.50
61
67
72
2.80
2
7
12
3.10
–54
–60
–66
2.80
NOTE:
The above data is for engineering purposes only. These represent typical values that can be expected.
Recommended System and Test Setup with Multiple
Serial Interface Slave Devices
feasible if there is an additional slave device sharing the
same two-wire serial interface on the controller chip.
In such systems, it is recommended to have a voltage
follower to isolate the pull-up resistors attached between the
two-wire serial interface and VDD_IO supply of MT9D115
as shown in Figure 37. Otherwise, the data toggling from the
two-wire serial interface transactions to other could cause
leakage from the VDD_IO supply of MT9D115.
The recommended system and test setup shown in
Figure 37 is only valid for a system where MT9D115 is the
only two-wire serial interface slave device connected to the
controller chip. As the SCLK and SDATA are to be pulled high
to the VDD_IO level during the hardware standby to
minimize the IO current consumption due to the data
toggling in the two-wire serial interface, this design is not
Voltage
Regulator
Voltage
Follower
VREG
MT9D115
Controller
VDD_IO
GND
VIO_Controller
SCLK
X
SDATA
X
RESET_BAR,
STANDBY
Drive HIGH
SADDR, EXTCLK
Drive LOW
PIXCLK, FRAME_VALID,
LINE_VALID, DOUT[7:0],
GPIO[1:0]
Input
GND
GPIO[3:2]
GND
Other Slave Devices
Figure 37. Recommended System and Test Setup for Minimum VDD_IO Power Consumption in the MT9D115
Sharing with Multiple Two-wire Serial Interface Devices
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MT9D115
In addition, in some system designs where the IO level of
the additional devices sharing the same two-wire serial
interface with MT9D115 is different from that of MT9D115,
it is recommended that the IO voltage level between the
controller and the MT9D115 be maintained to the same level
by sourcing from the same voltage regular as shown in
Figure 38.
Voltage
Regulator
Voltage
Follower
VREG1
MT9D115
GND
Controller
VDD_IO
VIO_Controller
SCLK
X
SDATA
X
RESET_BAR,
STANDBY
Drive HIGH
SADDR, EXTCLK
Drive LOW
PIXCLK, FRAME_VALID,
LINE_VALID, DOUT[7:0],
GPIO[1:0]
Input
GND
GPIO[3:2]
GND
VREG2
Other Slave Devices
Voltage
Regulator
Figure 38. Recommended System and Test Setup for Minimum VDD_IO Power Consumption in the MT9D115
Sharing with Multiple Two-wire Serial Interface Devices at Different IO Level
The current leakage from the voltage level mismatch in
RESET_BAR pad can be characterized as follows:
For a system which uses separate voltage regulators for
MT9D115 sensor and the controller chip as shown in
Figure 39, it is important to match the voltage levels
between two regulators as close as possible. If the voltage
levels are not matched, there can be additional current
consumption in the VDD_IO domain connected to the
sensor. This additional current is generated in the internal
pull up resistor present in RESET_BAR pad and external
resistors used for two-wire serial interface.
I DD_IOmismatch +
V REG2 * V REG1
R PULLUPRESET_BAR@V DD_IO
(eq. 19)
The internal pull up resistance is dependent on the
VDD_IO level. Typical levels of mismatch current at
different VDD_IO levels can be found in Table 31.
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MT9D115
Voltage
Regulator
Voltage
Regulator
VREG2
VREG1
GND
GND
DUT
Controller
2.2 kW
VIO_Controller
VDD_IO
SCLK
High-Z
SDATA
High-Z
RESET_BAR, STANDBY
Drive HIGH
SADDR, EXTCLK
Drive LOW
PIXCLK, FRAME_VALID,
LINE_VALID, DOUT[7:0], GPIO[1:0]
GND
Input
GPIO[3:2]
GND
Figure 39. System Setup with Independent Voltage Sources for MT9D115 and Controller Chip
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MT9D115
Test Sequence for Measuring VDD_IO Current
at Hard Standby Mode
5. Supply the PWRDN pin with VDD_IO volt
externally and wait for one frame + 50 clock. At
this stage, the part is in hard standby.
6. By removing J1, the EXTCLK is disconnected to
the part and then connect EXTCLK pin (J1 pin2)
to either DGND or VDD_IO.
7. Now the part is in hard standby with EXTCLK off.
The user can read off the VDD_IO current from the
ammeter at step 3 above.
Follow the procedure defined within the sensor data sheet.
The following test sequence takes the MT9D115 as
a reference. Contact your local ON Semiconductor
Applications Engineer for any specific product.
To measure VDD_IO current at hard standby mode:
1. Supply PWRDN (also known as STANDBY) pin
(J11 pin2) with 0 volt externally.
2. Supply the RESET_BAR pin (U22 pin4) with
VDD_IO volt externally.
3. Connect an ammeter between IDD_IO (J9) and
DGND.
4. Use jumpers J5, J17, and J20 to make sure GPIO
pins are connected to either GND or VDD_IO.
At this point, the part is in operating mode and it is
possible to load an .INI file to get an image with
DevWare.
Modifications
J9 jumper removed to monitor IDDIO
by connecting Ammeter on Pins 1
and 2
To control the Reset pin externally,
U22 was removed and a 10 kW
resistor connected to Pin 4, which is
connected to a 2.8 V external source
J11 jumper removed to control the
STANDBY or PWDN pin externally.
A 10K resistor is connected for pull−
up on this pin. in 2 in operating= 0 V,
Hard Standby= 2.8 V using external
voltage source.
J1 jumper for CLOCK
Figure 40. Modifications to the Demo2 Sensor Head Board for VDD_IO Current Measurement
Conclusion
in MT9D115. A system configuration to achieve this is
proposed in this document. In addition, suggestions on how
to approach system designs with multiple two-wire serial
interface devices and multiple IO level devices are provided.
It is important from the system perspective to ensure IO
levels between MT9D115 and the controller chip at the same
potential level to achieve minimum IO power consumption
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MT9D115
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