MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Features
1/2-Inch Megapixel CMOS Digital Image Sensor
MT9M001C12STM (Monochrome) Datasheet, Rev. M
For the latest datasheet, please visit www.onsemi.com
Features
Table 1:
• Array Format (5:4): 1,280H x 1,024V (1,310,720 active
pixels). Total (incl. dark pixels): 1,312H x 1,048V
(1,374,976 pixels)
• Frame Rate: 30 fps progressive scan; programmable
• Shutter: Electronic Rolling Shutter (ERS)
• Window Size: SXGA; programmable to any smaller
format (VGA, QVGA, CIF, QCIF, etc.)
• Programmable Controls: Gain, frame rate, frame size
Optical format
Active imager size
Active pixels
Pixel size
Shutter type
Maximum data rate/
master clock
Frame
SXGA
rate
(1280 x 1024)
ADC resolution
Responsivity
Dynamic range
SNRMAX
Supply voltage
Applications
• Digital still cameras
• Digital video cameras
• PC cameras
Power consumption
General Description
Operating temperature
Packaging
The ON Semiconductor MT9M001 is an SXGA-format
with a 1/2-inch CMOS active-pixel digital image sensor. The active imaging pixel array of 1,280H x 1,024V. It
incorporates sophisticated camera functions on-chip
such as windowing, column and row skip mode, and
snapshot mode. It is programmable through a simple
two-wire serial interface.
Value
1/2-inch (5:4)
6.66 mm (H) x 5.32 mm (V)
1,280 H x 1,024 V
5.2 m x 5.2 m
Electronic rolling shutter (ERS)
48 MPS/48 MHz
30 fps progressive scan;
programmable
10-bit, on-chip
2.1 V/lux-sec
68.2 dB
45 dB
3.0 V3.6 V, 3.3 V nominal
363 mW at 3.3 V (operating);
294 W (standby)
0°C to +70°C
48-pin CLCC
The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs
an SXGA-size image at 30 frames per second (fps). An
on-chip analog-to-digital converter (ADC) provides 10
bits per pixel. FRAME_VALID and LINE_VALID signals
are output on dedicated pins, along with a pixel clock
that is synchronous with valid data.
This megapixel CMOS image sensor features ON Semiconductor’s breakthrough low-noise CMOS imaging
technology that achieves CCD image quality (based on
signal-to-noise ratio and low-light sensitivity) while
maintaining the inherent size, cost, and integration
advantages of CMOS.
MT9M001_DS Rev. M Pub. 5/15 EN
Key Performance Parameters
Parameter
1
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
MT9M001C12STM-DP
1 MP 1/2" CIS
Dry Pack with Protective Film
MT9M001C12STM-DR
1 MP 1/2" CIS
Dry Pack without Protective Film
MT9M001C12STM-DR1
1 MP 1/2" CIS
Dry Pack Single Tray without Protective Film
MT9M001C12STM-TP
1 MP 1/2" CIS
Tape & Reel with Protective Film
MT9M001C12STM-TR
1 MP 1/2" CIS
Tape & Reel without Protective Film
MT9M001D00STMC84AC1-200
1 MP 1/2" CIS
Die Sales, 200m Thickness
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Table of Contents
Table of Contents
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Two-Wire Serial Interface Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
48-Pin CLCC Package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pixel Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .15
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Readout of Six Columns in Normal and Column Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . .17
Readout of Six Rows in Normal and Row Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Readout of Eight Pixels in Normal and Column Skip Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Black Level Calibration Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
General Timing for Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Acknowledge Signal Timing After an 8-Bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Acknowledge Signal Timing After an 8-Bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Quantum Efficiency—Monochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Optical Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
48-pin CLCC Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Frame Time—Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Recommended Gain Settings at 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Optical Area Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MT9M001_DS Rev. M Pub. 5/15 EN
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
General Description
MT9M001_DS Rev. M Pub. 5/15 EN
NC
DGND
VDD
NC
NC
VAAPIX
AGND
AGND
SCLK
SDATA
NC
DGND
48-Pin CLCC Package Pinout Diagram
6
5
4
3
2
1
48
47
46
45
44
43
39
STROBE
NC
11
38
DGND
NC
12
37
VDD
OE#
13
36
DOUT
NC
14
35
DOUT
AGND
15
34
DOUT
VAA
16
33
DOUT
AGND
17
32
DOUT
AGND
18
31
PIXCLK
19
20
21
22
23
24
6
25
26
27
28
29
30
NC
10
CLKIN
RESET#
DOUT
LINE_VALID
DOUT
NC
DOUT
FRAME_VALID
40
DOUT
41
9
DOUT
TRIGGER
DGND
NC
VDD
42
8
AGND
7
VAA
STANDBY
NC
Figure 1:
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
Figure 2:
Block Diagram
Control Register
Active-Pixel
Sensor (APS)
Array
SXGA
1,280H x 1,024V
Timing and Control
Two-wire serial
Input/Output
Clock
Sync
Signals
Analog Processing
MT9M001_DS Rev. M Pub. 5/15 EN
ADC
7
10-bit Data
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
General Description
Table 3:
Pin Descriptions
Pin Numbers
Symbol
Type
Description
29
CLKIN
Input
Clock in. Master clock into sensor (48 MHz maximum).
13
OE#
Input
Output enable. OE# when HIGH places outputs DOUT, FRAME_VALID,
LINE_VALID, PIXCLK, and STROBE into a tri-state configuration.
10
RESET#
Input
Reset. Activates (LOW) asynchronous reset of sensor. All registers assume
factory defaults.
46
SCLK
Input
Serial clock. Clock for serial interface.
7
STANDBY
Input
Standby. Activates (HIGH) standby mode, disables analog bias circuitry for
power saving mode.
8
TRIGGER
Input
Trigger. Activates (HIGH) snapshot sequence.
45
SDATA
Input/Output
24–28, 32–36
DOUT
Output
Data out. Pixel data output bits 0:9, DOUT (MSB), DOUT (LSB).
41
FRAME_VALID
Output
Frame valid. Output is pulsed HIGH during frame of valid pixel data.
40
LINE_VALID
Output
Line valid. Output is pulsed HIGH during line of selectable valid pixel data
(see Reg0x20 for options).
31
PIXCLK
Output
Pixel clock. Pixel data outputs are valid during falling edge of this clock.
Frequency = (master clock).
39
STROBE
Output
Strobe. Output is pulsed HIGH to indicate sensor reset operation of pixel
array has completed.
15,17,18,21, 47,
48
5, 23, 38, 43
AGND
Supply
DGND
Supply
Digital ground. Provide isolated ground for digital block.
16, 20
VAA
Supply
Analog power. Provide power supply for analog block, 3.3V ±0.3V.
Serial data. Serial data bus, requires 1.5K resistor to 3.3V for pull-up.
Analog ground. Provide isolated ground for analog block and pixel array.
1
VAAPIX
Supply
Analog pixel power. Provide power supply for pixel array, 3.3V ±0.3V (3.3V).
4, 22, 37
VDD
Supply
Digital power. Provide power supply for digital block, 3.3V ±0.3V.
2, 3 ,6, 9, 11,
12,14, 19, 30, 42,
44
NC
—
MT9M001_DS Rev. M Pub. 5/15 EN
No connect. These pins must be left unconnected.
8
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Pixel Data Format
Pixel Array Structure
The MT9M001 pixel array is configured as 1,312 columns by 1,048 rows (shown in
Figure 3). The first 16 columns and the first eight rows of pixels are optically black, and
can be used to monitor the black level. The last seven columns and the last seven rows of
pixels are also optically black. The black row data is used internally for the automatic
black level adjustment. However, the black rows can also be read out by setting the
sensor to raw data output mode (Reg0x20, bit 11 = 1). There are 1,289 columns by 1,033
rows of optically active pixels, which provides a four-pixel boundary around the SXGA
(1,280 x 1,024) image.
Figure 3:
Pixel Array Description
(0, 0)
8 black rows
SXGA (1,280 x 1,024)
+ 4 pixel boundary
+ additional active column
+ additional active row
= 1,289 x 1,033 active pixels
7 black columns
7 black rows
(1311, 1047)
Figure 4:
16 black columns
Pixel Pattern Detail (Top Right Corner)
column readout direction
..
.
black pixels
Pixel
(8, 16)
ee eo ee eo ee eo ee
row
readout
direction
oe oo oe oo oe oo oe
...
ee eo ee eo ee eo ee
oe oo oe oo oe oo oe
ee eo ee eo ee eo ee
oe oo oe oo oe oo oe
Note:
MT9M001_DS Rev. M Pub. 5/15 EN
e = even column or row
0 = odd column or row
9
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Output Data Format
The MT9M001 image data is read out in a progressive scan. Valid image data is
surrounded by horizontal blanking and vertical blanking, as shown in Figure 5. The
amount of horizontal blanking and vertical blanking is programmable through Reg0x05
and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure.
FRAME_VALID timing is described in “Output Data Timing” on page 10.
Figure 5:
Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Output Data Timing
The data output of the MT9M001 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 6:
Timing Example of Pixel Data
....
LINE_VALID
....
PIXCLK
Blanking
DOUT9-DOUT0
P0
(9:0)
P1
(9:0)
P2
(9:0)
P3
(9:0)
Blanking
....
Valid Image Data
P4
(9:0)
....
Pn-1
(9:0)
Pn
(9:0)
The rising edges of the PIXCLK signal are nominally timed to occur on the rising DOUT
edges. This allows PIXCLK to be used as a clock to latch the data. DOUT data is valid on
the falling edge of PIXCLK. The PIXCLK is HIGH while master clock is HIGH and then
LOW while master clock is LOW. It is continuously enabled, even during the blanking
period. The parameters P1, A, P2, and Q in Figure 7 are defined in Table 4.
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Figure 7:
Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
MT9M001_DS Rev. M Pub. 5/15 EN
P1
A
Q
A
11
Q
A
P2
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Pixel Data Format
Frame Timing Formulas
Table 4:
Frame Timing
Parameter
Name
Equation (MASTER CLOCK)
Default Timing
Notes
A
Active Data Time
(Reg0x04 + 1)
1,280 pixel clocks
= 26.7s
P1
Frame Start Blanking
(242)
242 pixel clocks
= 5.04s
P2
Frame End Blanking
(2 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
2 pixel clocks
= 0.042s
2
Q = P1 + P2
Horizontal Blanking
(244 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
244 pixel clocks
= 5.08s
2
A+Q
Row Time
((Reg0x04 + 1) + (244 + Reg0x05 - 19))
1,524 pixel clocks
= 31.75s
V
Vertical Blanking
(Reg0x06 + 1) x (A + Q)
(MIN Reg0x06 value = 15)
39,624 pixel clocks
= 825.5s
NROWS x (A + Q)
Frame Valid Time
(Reg0x03 + 1) x (A + Q)
1,560,576 pixel clocks
= 32.51ms
F
Total Frame Time
(Reg0x03 + 1 + Reg0x06 + 1) x (A + Q)
1,600,200 pixel clocks
= 33.34ms
Notes:
1
1. Row skip mode should have no effect on the integration time. Column skip mode changes the effective value of Column Size (Reg0x04) as follows:
Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1
Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1
Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1
where the int() function truncates to the next lowest integer. Now use R4eff in the equation for row
time instead of R4
2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19.
Sensor timing is shown above in terms of pixel clock and master clock cycles (please
refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical
blank and total frame time equations assume that the number of integration rows (bits
13 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 +
1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used
instead to determine the frame time, as shown in Table 5.
Table 5:
Frame Time—Long Integration Time
Parameter
V’
F’
Name
Equation (master clock)
Default Timing
Vertical Blanking (long integration time)
(Reg0x09 – Reg0x03) x (A + Q)
39,624 pixel clocks
= 82.5s
Total Frame Time (long integration time)
(Reg0x09 + 1) x (A + Q)
1,600,200 pixel clocks
= 33.34ms
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9M001 through the two-wire serial interface bus. The sensor is a two-wire serial interface slave and is controlled by the serial
clock (SCLK), which is driven by the serial interface master. Data is transferred into and
out of the MT9M001 through the serial data (SDATA) line. The SDATA line is pulled up to
3.3V off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line
down—the serial interface protocol determines which device is allowed to pull the
SDATA line down at any given time.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device eight-bit address
• a(an) (no) acknowledge bit
• an 8-bit message
• a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's eight-bit address. The last bit of the address
determines if the request will be a read or a write, where a “0” indicates a write and a “1”
indicates a read. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit
data for its internal registers, thus requiring two 8-bit transfers to write to one register.
After 16 bits are transferred, the register address is automatically incremented, so that
the next 16 bits are written to the next register address. The master stops writing by
sending a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data eight bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
MT9M001_DS Rev. M Pub. 5/15 EN
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Serial Bus Description
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of seven bits of address
and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indicates the write mode, and a “1” (0xBB) indicates read mode.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Two-Wire Serial Interface Sample Write and Read Sequences
Two-Wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 8. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
will then give an acknowledge bit and expects the register address to come first, followed
by the 16-bit data. After each eight-bit transfer, the image sensor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are
transferred, the register address is automatically incremented so that the next 16 bits are
written to the next register. The master stops writing by sending a start or stop bit.
Figure 8:
Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK
SDATA
Reg0x09
0xBA ADDR
START
ACK
0000 0010
ACK
1000 0100
ACK
STOP
ACK
16-Bit Read Sequence
A typical read sequence is shown in Figure 9. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The
register address should be incremented after every 16 bits is transferred. The data
transfer is stopped when the master sends a no-acknowledge bit.
Figure 9:
Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA
0xBA ADDR
START
MT9M001_DS Rev. M Pub. 5/15 EN
Reg0x09
ACK
0xBB ADDR
ACK
0000 0010
ACK
15
1000 0100
ACK
STOP
NACK
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Feature Description
Signal Path
The MT9M001 signal path consists of two stages, a programmable gain stage and a
programmable analog offset stage.
Programmable Gain Stage
A total programmable gain of 15 is available and can be calculated using the following
formula:
Gain 1 to 8: Gain = (bit[6] + 1) x (bit[5:0] x 0.125)
For gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3
LSB's bit[2:0] to set the higher gain values. The formula for obtaining gain greater than
eight is as follows:
Total gain = 8 + bit[2:0]
For example, for total gain = 12, the value to program is bit[6–0] = 1100100.
The maximum total gain = 15, i.e. bit[6:0] = 1100111.
The gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. The
minimum gain of one corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the
gain below this value may cause the sensor to saturate at ADC output values less than
the maximum, under certain conditions. It is recommended that this guideline be
followed at all times.
Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are
alternative ways of achieving certain gains. Some settings offer superior noise performance to others, despite the same overall gain. Recommended gain settings are listed in
Table 6.
Figure 10:
Signal Path
Gain Selection
(Reg0x2B - 0x2E)
Pixel Output
(signal
minus reset)
+
X
10-bit ADC
ADC Data
(9:0)
Offset Correction Voltage
(Reg0x60, Reg0x61,
Reg0x63, Reg0x64)
(signed lower 9 bits) x 2mV
Table 6:
Recommended Gain Settings at 48 MHz
Nominal Gain
Increments
Recommended Settings
1 to 4.000
4.25 to 8.00
9 to 15
0.125
0.25
1.0
0x08 to 0x20
0x51 to 0x60
0x61 to 0x67
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Programmable Analog Offset Stage
The programmable analog offset stage corrects for analog offset that might be present in
the analog signal. The user would need to program register 0x62 appropriately to enable
the analog offset correction.
The lower eight bits (bit[7:0]) determines the absolute value of the analog offset to be
corrected and bit[8] determines the sign of the correction. When bit[8] is “1”, the sign of
the correction is negative and vice versa. The analog value of the correction relative to
the analog gain stage can be determined from the following formula:
Analog offset (bit[8] = 0) = bit[7:0] x 2mV
Analog offset (bit[8] = 1) = - (bit[7:0] x 2mV)
Column and Row Mirror Image
By setting bit 14 of Reg0x20, the readout order of the columns will be reversed, as shown
in Figure 11.
Figure 11:
Readout of Six Columns in Normal and Column Mirror Output Mode
LINE_VALID
Normal readout
DOUT9–DOUT0
Col0
(9:0)
Col1
(9:0)
Col2
(9:0)
Col3
(9:0)
Col4
(9:0)
Col5
(9:0)
Col5
(9:0)
Col4
(9:0)
Col3
(9:0)
Col2
(9:0)
Col1
(9:0)
Col0
(9:0)
Reverse readout
DOUT9–DOUT0
By setting bits 15 of Reg0x20 the readout order of the rows will be reversed, as shown in
Figure 12.
Figure 12:
Readout of Six Rows in Normal and Row Mirror Output Mode
FRAME_VALID
Normal readout
DOUT9–DOUT0
Row0
(9:0)
Row1
(9:0)
Row2
(9:0)
Row3
(9:0)
Row4
(9:0)
Row5
(9:0)
Row5
(9:0)
Row4
(9:0)
Row3
(9:0)
Row2
(9:0)
Row1
(9:0)
Row0
(9:0)
Reverse readout
DOUT9–DOUT0
Column and Row Skip
By setting bit 3 of Reg0x20, only half of the columns set will be read out. An example is
shown in Figure 13. Only columns with bit 1 equal to “0” will be read out (xxxxxxx0x).
The row skip works in the same way and will only read out rows with bit 1 equal to “0.”
Row skip mode is enabled by setting bit 4 of Reg0x20. For both row and column skips, the
number of rows or columns read out will be half of what is set in Reg0x03 or Reg0x04,
respectively.
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Figure 13:
Readout of Eight Pixels in Normal and Column Skip Output Mode
LINE_VALID
Normal readout
DOUT9–DOUT0
G0
(9:0)
R0
(9:0)
G1
(9:0)
R1
(9:0)
G0
(9:0)
R0
(9:0)
G2
(9:0)
R2
(9:0)
G2
(9:0)
R2
(9:0)
G3
(9:0)
R3
(9:0)
LINE_VALID
Column skip readout
DOUT9–DOUT0
Black Level Calibration
The MT9M001 has automatic black level calibration on-chip which can be overridden by
the user, as described below and shown in Figure 14.
The automatic black level calibration measures the average value of 256 pixels from two
dark rows of the chip for each of the four colors. The pixels are averaged as if they were
light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames.
For each color, the new filtered average is compared to a minimum acceptable level (to
screen for too low a black level) and a maximum acceptable level. If the average is lower
than the minimum acceptable level, the offset correction voltage for that color is
increased by one offset LSB (offset LSBs do not match ADC LSBs; typically, one offset
LSB is approximately 2mV). If it is above the maximum level, the level is decreased by 1
LSB (2mV). The upper threshold is automatically adjusted upwards whenever an
upward shift in the black level from below the minimum results in a new black level
above the maximum. This prevents black level oscillation from below the minimum to
above the maximum. The lower threshold is increased with the maximum gain setting
according to the formula described under Reg0x5F. This prevents clipping of the black
level.
Whenever the gain or any of the readout timing registers is changed (shutter width,
vertical blanking, number of rows or columns, or the shutter delay) or if the black level
recalculation bit, reset bit or restart bit is set, the running digitally filtered average is
reset to the first average of the dark pixels. The digital filtering over many frames is then
restarted. Whenever the gain or the readout timing registers are changed, the upper
threshold is restored to its default value.
After changes to the sensor configuration, large shifts in the black level calibration can
result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row
readout is performed on the first frame after certain changes to the sensor registers. Any
changes to the registers listed above will cause this recalculation. The data from this
sweep allows the sensor to choose an accurate new starting point for the running
average. This procedure can be disabled as described under Reg0x5F.
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Figure 14:
Black Level Calibration Flow Chart
Gain Selection
(color-wise)
Pixel Output
(signal minus
reset)
X
+
10-bit ADC
ADC Data
(9:0)
Offset Correction Voltage
(color-wise)
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Feature Description
Still Image Capture with External Synchronization
In continuous mode video image capture, the TRIGGER signal should be held LOW or
“0.” To capture a still image, the sensor must first be put into snapshot mode by
programming a “1” in register 0x1E, bit 8. In snapshot mode, the sensor waits for a
TRIGGER signal (FRAME_VALID, LINE_VALID signals are LOW, pixel clock signal
continues). When the TRIGGER signal is received (active HIGH), one frame is read out (a
TRIGGER signal can also be achieved by programming a restart—for example, program
a “1” to bit 0 of Reg0x0B). The reset, readout timing for that frame will be the same as for
a continuous frame with similar register settings; the only difference is that only one
frame is read out. General timing for the snapshot mode is shown in Figure 15.
Figure 15:
General Timing for Snapshot Mode
TRIGGER
Reset Row 1
Reset Row
Reset Row x
MAX strobe length (all rows integrating)
STROBE
MIN strobe length (1 row time)
Readout
LINE_VALID Signal
By setting bit 9 and 10 of Reg0x20 the line valid signal can get three different output
formats. The formats are shown when reading out four rows and two vertical blanking
rows (Figure 16). In the last format, the LINE_VALID signal is the XOR between the
continuously LINE_VALID signal and the FRAME_VALID signal.
Figure 16:
Different LINE_VALID Formats
Default
FRAME_VALID
LINE_VALID
Continuously
FRAME_VALID
LINE_VALID
XOR
FRAME_VALID
LINE_VALID
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Electrical Specifications
Data Output and Propagation Delays
By default, the MT9M001 launches pixel data, FRAME_VALID and LINE_VALID with the
rising edge of PIXCLK. The expectation is that the user captures DOUT[7:0],
FRAME_VALID and LINE_VALID using the falling edge of PIXCLK.
Figure 17:
Data Output Timing Diagram
tR
tCLKIN
tF
CLKIN
tCP
PIXCLK
tOS
tFVS
tLVS
XXX
Data[0-7]
T
tPD
XXX
P0
P1
XXX
P2
XXX
XXX
PN
XXX
tPFL
tPLL
tOH
Frame Valid/
Line Valid
Note: Frame_Valid leads Line_Valid by 242 PIXCLKs.
Note: Frame_Valid trails
Line_Valid (1+ Reg0x05-19) PIXCLKS.
tPFH
tPLH
Table 7:
DC Electrical Characteristics
(DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C)
Symbol
Definition
Condition
Min
Typ
Max
Units
VDD
Core digital voltage
3
3.3
3.6
V
VAA
Analog voltage
3
3.3
3.6
V
VAAPIX
Pixel supply voltage
3
3.3
VIH
Input high voltage
VIL
Input low voltage
IIN
Input leakage current
No Pull-up Resistor; VIN = VDD or
DGND
3.6
V
VPWR - 0.3
VPWR + 0.3
V
-0.3
0.8
V
-15
15
A
—
V
0.2
V
VOH
Output high voltage
VOL
Output low voltage
IOZ
Tri-state output leakage current
—
15
A
IDD
Digital operating current
—
20
24
mA
IAA
Analog operating current
—
85
110
mA
IAAPIX
Pixel supply current
—
5
10
mA
MT9M001_DS Rev. M Pub. 5/15 EN
VPWR - 0.2
21
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Table 7:
DC Electrical Characteristics (continued)
(DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C)
Symbol
Definition
ISTDBYD
Digital standby current
STDBY = VDD, CLKIN = 0 MHz
ISTDBYD
W/CLK
Digital standby current
STDBY = VDD, CLKIN = 48 MHz
ISTDBYDA
Analog standby current
STDBY = VDD
Table 8:
Condition
Min
Typ
Max
Units
—
9
20
A
—
55
125
A
—
80
100
A
Max
Unit
.
AC Electrical Characteristics
(AC Setup Conditions: fCLKIN= 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, Output Load = 30pF,
TA = 25°C))
Symbol
Definition
Condition
Min
Typ
1
—
48
MHz
1000
—
20.83
ns
—
20.83
fCLKIIN
Input clock frequency
tCLKIN
Input clock period
T
PIXCLK period
1000
tR
Input clock rise time
tF
Input clock fall time
—
4
Clock duty cycle
45
50
55
4
ns
V/ns
V/ns
%
tCP
CLKIN to PIXCLK propagation delay
—
10
—
ns
tPD
PIXCLK to data valid
—
—
1
ns
tPFH
PIXCLK to FV high
—
—
7
ns
tPLH
PIXCLK to LV high
—
—
7
ns
tPFL
PIXCLK to FV low
—
—
13
ns
tPLL
PIXCLK to LV low
—
—
13
ns
tOS
Setup time for data before falling edge of PIXCLK
T/2 -1
T/2
T/2 +1
ns
tOH
Hold time for data after falling edge of PIXCLK
T/2 -1
T/2
T/2 +1
ns
tFVS
Setup time for FV before falling edge of PIXCLK
2
3
—
ns
tLVS
Setup time for LV before falling edge of PIXCLK
2
3
—
ns
CLOAD
Load capacitance
30
pF
Table 9:
Absolute Maximum Ratings
Rating
Symbol
TOP
TSTG1
Note:
Parameter
Operating temperature
Storage temperature
MIN
MAX
Unit
0
70
°C
–40
125
°C
1Stresses greater than those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Two-wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles
between transitions. These are specified in the following diagrams in master clock
cycles.
Figure 18:
Serial Host Interface Start Condition Timing
5
4
SCLK
SDATA
Figure 19:
Serial Host Interface Stop Condition Timing
5
4
SCLK
SDATA
Note:
Figure 20:
All timing are in units of master clock cycle.
Serial Host Interface Data Timing for Write
4
4
SCLK
SDATA
Note:
Figure 21:
SDATA is driven by an off-chip transmitter.
Serial Host Interface Data Timing for Read
5
SCLK
SDATA
Note:
MT9M001_DS Rev. M Pub. 5/15 EN
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.
23
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Figure 22:
Acknowledge Signal Timing After an 8-Bit Write to the Sensor
3
6
SCLK
Sensor pulls down
SDATA pin
SDATA
Figure 23:
Acknowledge Signal Timing After an 8-Bit Read from the Sensor
7
6
SCLK
SDATA
Note:
MT9M001_DS Rev. M Pub. 5/15 EN
Sensor tri-states SDATA pin
(turns off pull down)
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When
read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float
HIGH. On the following cycle, a start or stop bit may be used.
24
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Quantum Efficiency
Figure 24:
Quantum Efficiency—Monochrome
Quantum Efficiency - Monochrome
Quantum Efficiency (%)
60
50
40
30
20
10
0
350
450
550
650
750
Wavelength (nm)
850
950
1050
Image Center Offset and Orientation
Figure 25:
Image Center Offset
7.75mm
Pad 1
Pixel
Array
Pixel (0,0)
Pixel (12, 20)
Image Center
0.015mm
0.712mm
7.75mm
Black and
Boundary
Pixels
Die Center
MT9M001_DS Rev. M Pub. 5/15 EN
25
©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
Table 10:
Optical Area Dimensions
Optical Area
Pixel
SXGA
Chip Size, mm
Y-dimension
3,340.70m
3,372.45m
Center of Pixel (1299, 1035)
-3,315.2m
-1,952.35m
7.75mm
7.75mm
(including Seal Ring)
Notes:
Figure 26:
X-Dimension
Center of pixel (20, 12)
1. X and Y coordinates referenced to center of die.
2. Die center = package center.
3. Image center offset from package center (x = 0.015mm, y = 0.712mm).
Optical Orientation
Top of board
UP
Pixel Array
Pin 1
Bottom of board
MT9M001_DS Rev. M Pub. 5/15 EN
26
©Semiconductor Components Industries, LLC,2015.
MT9M001_DS Rev. M Pub. 5/15 EN
Figure 27:
48-pin CLCC Package Outline Drawing
Notes:
Side View
Bottom View
©Semiconductor Components Industries, LLC,2015
1. All exposed metallized area shall be gold plated 60 micro inches min thk. over nickel plated unless otherwise specified in purchase
order.
2. Seal area and die attach area shall be without metallization.
3. Die center to package center accuracy +/- 100 m.
4. Die thickness = 0.675mm(26.5mils).
5. Epoxy thickness for die attachment is 0.025~0.050 mm.
6. Glass transmittance >=90%.
7. Glass tilt =0.10mm max.
8. All dimensions in millimeters.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Electrical Specifications
27
Top View
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Revision History
Revision History
Rev. M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/15
• Updated “Ordering Information” on page 2
Rev. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15
• Converted to ON Semiconductor template
Rev. K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/2/11
• Removed Digital Clarity
• Applied updated template
Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10
• Updated to non-confidential
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10
• Removed registers and transfered to separate document
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/09
• Updated Figure 27: “48-pin CLCC Package Outline Drawing” on page 30
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/09
• Updated to Aptina template
Rev E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/06
• Updated description in Table 2, “Available Part Numbers,” on page 1
• Update Figure 4: “Pixel Pattern Detail (Top Right Corner),” on page 9
• Updated "Data Output and Propagation Delays" on page 21
• Updated tPFL and tPLL in Table 8, “AC Electrical Characteristics,” on page 22
Rev D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/06
• Updated Table 1, “Key Performance Parameters,” on page 1
• Update Table 2, “Available Part Numbers,” on page 1
• Updated Figure 4: “Pixel Pattern Detail (Top Right Corner),” on page 9
Rev C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/05
• Remove color information
• Updated Table 1, “Key Performance Parameters,” on page 1
• Updated Table 6, “Register List and Default Values,” on page 11
• Updated Table 7, “Register Description,” on page 12
• Updated Figure 12, Readout of Six Rows in Normal and Row Mirror Output Mode, on
page 17
• Deleted Figure 13, Readout of Eight Pixels in Normal and Column Skip Output Mode,
on page 18
• Updated Table 8, “AC Electrical Characteristics,” on page 22
• Updated Figure 25, Image Center Offset, on page 25
• Updated Figure 27, 48-pin CLCC Package Outline Drawing, on page 27
Rev B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05
• Page 1, remove PRELIMINARY disclaimer
• Page 1, add Key Performance Parameters table, add APPLICATIONS
• Page 2, add Table of Contents
• Page 6, update Pin Description table
MT9M001_DS Rev. M Pub. 5/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
Revision History
• Page 11, update Serial Bus Description
• Page 12, update Timing Diagram Showing a Read from Reg0x09; Returned Value
0x0284 figure
• Page 13, update Register List and Default Values table
• Page 14, update Register Description Table (add Test Data-Reg0x32[11:2], update
Output Control-Reg0x07[6]
• Page 28, update AC and DC Electrical Characteristics table
• Page 29, add Figure 17, Data Output Timing Diagram, and Absolute Maximum
Ratings, Table 11
• Page 30, update Propagation Delay for Frame_Valid and Line_Valid Signals (Data
Output and Propagation Delays
• Page 32, delete Quantum Efficiency figure (Color)
• Page 33, update Figure 27, 48-pin CLCC Package Outline Drawing
Rev A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/03
• Initial Release of document
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rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/
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without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey
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MT9M001_DS Rev. M Pub. 5/15 EN
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