MTD6N15T4GV

MTD6N15 Power Field Effect Transistor DPAK for Surface Mount N−Channel Enhancement−Mode Silicon Gate This Power FET is designed for high speed, low loss power switching applications such as switching regulators, converters, solenoid and relay drivers. Features • • • • • • • Silicon Gate for Fast Switching Speeds Low RDS(on) — 0.3 W Max Rugged — SOA is Power Dissipation Limited Source−to−Drain Diode Characterized for Use With Inductive Loads Low Drive Requirement — VGS(th) = 4.0 V Max Surface Mount Package on 16 mm Tape Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) MAX ID MAX 150 V 0.3 W 6.0 A N−CHANNEL D G S MAXIMUM RATINGS Rating Value Unit VDSS 150 Vdc Drain−Gate Voltage (RGS = 1.0 MW) VDGR 150 Vdc Gate−Source Voltage − Continuous − Non−Repetitive (tp ≤ 50 ms) VGS VGSM ± 20 ± 40 Vdc Vpk ID IDM 6.0 20 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 20 0.16 W W/°C Total Power Dissipation @ TA = 25°C Derate above 25°C (Note 1) PD 1.25 0.01 W W/°C Total Power Dissipation @ TA = 25°C (Note 1) Derate above 25°C (Note 2) PD 1.75 W 0.014 W/°C −65 to +150 °C Drain Current − Continuous Drain Current − Pulsed Operating and Storage Junction Temperature Range TJ, Tstg 4 1 2 CASE 369C DPAK (Surface Mount) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain 1 Gate THERMAL CHARACTERISTICS Characteristic Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Symbol Value RqJC RqJA RqJA 6.25 100 71.4 Unit °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using the minimum recommended pad size. 2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size. 3 YWW T 6N15G Symbol Drain−Source Voltage Y WW 6N15 G 2 Drain 3 Source = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION Device MTD6N15T4 MTD6N15T4G Package Shipping† DPAK 2500/Tape & Reel DPAK (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 5 1 Publication Order Number: MTD6N15/D MTD6N15 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 150 − Vdc − − 10 100 OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0 Vdc) TJ = 125°C IDSS Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF − 100 nAdc Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR − 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) TJ = 100°C VGS(th) 2.0 1.5 4.5 4.0 Vdc Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) − 0.3 W Drain−Source On−Voltage (VGS = 10 Vdc) (ID = 6.0 Adc) (ID = 3.0 Adc, TJ = 100°C) VDS(on) − − 1.8 1.5 gFS 2.5 − mhos pF mAdc ON CHARACTERISTICS (Note 3) Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) (See Figure 11) Output Capacitance Reverse Transfer Capacitance Ciss − 1200 Coss − 500 Crss − 120 td(on) − 50 tr − 180 td(off) − 200 SWITCHING CHARACTERISTICS* (TJ = 100°C) Turn−On Delay Time Rise Time (VDD = 25 Vdc, ID = 3.0 Adc, RG = 50 W) (See Figures 13 and 14) Turn−Off Delay Time Fall Time Total Gate Charge (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 Vdc) (See Figure 12) Gate−Source Charge Gate−Drain Charge tf − 100 Qg 15 (Typ) 30 Qgs 8.0 (Typ) − Qgd 7.0 (Typ) − VSD 1.3 (Typ) 2.0 ns nC SOURCE−DRAIN DIODE CHARACTERISTICS* Forward On−Voltage Forward Turn−On Time (IS = 6.0 Adc, di/dt = 25 A/ms, VGS = 0 Vdc) Reverse Recovery Time Limited by stray inductance trr 325 (Typ) PD, POWER DISSIPATION (WATTS) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 2.5 25 2 20 1.5 15 1 10 0.5 5 0 0 TA TC TC 25 50 75 100 T, TEMPERATURE (°C) Figure 1. Power Derating http://onsemi.com 2 125 Vdc ton 150 − ns MTD6N15 TYPICAL ELECTRICAL CHARACTERISTICS I D , DRAIN CURRENT (AMPS) 10 V VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS) 24 9V 20 TJ = 25°C 16 8V 12 8 7V 4 6V 5V 0 0 10 20 30 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 60 3.6 2.8 2.4 2 - 50 TJ = 25°C I D , DRAIN CURRENT (AMPS) VDS = 10 V 12 10 8 6 4 100°C - 55°C 2 0 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 1.6 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.20 TJ = 100°C 25°C 0.15 - 55°C 0.10 0.05 0 0 4 8 12 16 ID, DRAIN CURRENT (AMPS) VGS = 0 V ID = 0.25 mA 1.2 0.8 0.4 0 - 50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) 200 Figure 5. Breakdown Voltage Variation With Temperature 0.30 0.25 150 2 Figure 4. Transfer Characteristics VGS = 10 V 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 3. Gate−Threshold Voltage Variation With Temperature V(BR)DSS , DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 2. On−Region Characteristics 14 VDS = VGS ID = 1 mA 3.2 2 1.6 1.2 0.8 0.4 0 - 50 20 VGS = 10 V ID = 3 A Figure 6. On−Resistance versus Drain Current 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) Figure 7. On−Resistance Variation With Temperature http://onsemi.com 3 200 MTD6N15 SAFE OPERATING AREA 20 100 ms 10 10 ms I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 20 1 ms 5 2 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.5 0.2 0.1 dc 15 TJ ≤ 150°C 10 5 TC = 25°C VGS = 20 V SINGLE PULSE 0.05 0.03 0.3 0.5 0.7 1 2 3 5 7 10 20 30 50 70 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 200 300 0 20 Figure 8. Maximum Rated Forward Biased Safe Operating Area 40 60 80 100 120 140 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 160 Figure 9. Maximum Rated Switching Safe Operating Area SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 9 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn−on and turn−off of the devices for switching times less than one microsecond. The power averaged over a complete switching cycle must be less than: FORWARD BIASED SAFE OPERATING AREA r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, “Transient Thermal Resistance−General Data and Its Use” provides detailed instructions. 0.7 0.5 D = 0.5 0.3 0.2 TJ(max) − TC RqJC 0.2 0.1 P(pk) 0.1 0.05 0.07 0.02 0.05 0.03 0.02 0.01 0.01 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 t, TIME OR PULSE WIDTH (ms) Figure 10. Thermal Response http://onsemi.com 4 20 RqJC(t) = r(t) RqJC RqJC(t) = 6.25°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 50 100 200 500 1000 MTD6N15 2000 TJ = 25°C VGS = 0 1600 C, CAPACITANCE (pF) VGS, GATE SOURCE VOLTAGE (VOLTS) 16 1200 800 400 0 15 Ciss VDS = 0 10 5 VGS 0 5 10 Coss Crss 25 30 20 15 TJ = 25°C ID = 6 A 12 75 V VDS = 50 V 8 4 0 35 120 V 0 4 VDS 8 12 Qg, TOTAL GATE CHARGE (nC) 16 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Capacitance Variation Figure 12. Gate Charge versus Gate−To−Source Voltage RESISTIVE SWITCHING VDD ton td(on) RL Vout Vin PULSE GENERATOR Rgen 50 W tr td(off) tf 90% 90% OUTPUT, Vout INVERTED DUT z = 50 W toff 10% 90% 50 W INPUT, Vin 50% 50% 10% PULSE WIDTH Figure 13. Switching Test Circuit Figure 14. Switching Waveforms http://onsemi.com 5 20 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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