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notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
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liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
MTD6P10E
Preferred Device
Power MOSFET
6 Amps, 100 Volts
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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V(BR)DSS
RDS(on) TYP
ID MAX
100 V
660 mW
6.0 A
P−Channel
Features
D
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
G
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Packages are Available
S
MARKING DIAGRAM & PIN ASSIGNMENTS
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
100
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
100
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 20
Vdc
Vpk
ID
ID
6.0
3.9
18
Adc
PD
50
0.4
1.75
W
W/°C
W
TJ, Tstg
−55 to
150
°C
EAS
180
mJ
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tp ≤ 10 ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 6.0 Apk, L = 10 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
IDM
1 2
Apk
2.50
100
71.4
TL
260
August, 2006 − Rev. 5
DPAK
CASE 369C
STYLE 2
Y
WW
T6P10E
G
1
4
Drain
Source 3
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
DPAK
75 Units/Rail
MTD6P10EG
DPAK
(Pb−Free)
75 Units/Rail
MTD6P10ET4
DPAK
2500 Tape & Reel
DPAK
(Pb−Free)
2500 Tape & Reel
Device
MTD6P10ET4G
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
© Semiconductor Components Industries, LLC, 2006
3
°C/W
°C
YWW
T6
P10EG
Drain 2
MTD6P10E
RqJC
RqJA
RqJA
Gate 1
4
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MTD6P10E/D
MTD6P10E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
−
−
124
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
2.9
4.0
4.0
−
Vdc
mV/°C
−
0.56
0.66
W
−
−
3.6
−
4.8
4.2
gFS
1.5
3.0
−
mhos
Ciss
−
550
840
pF
Coss
−
154
240
Crss
−
27
56
td(on)
−
12
25
tr
−
29
60
td(off)
−
18
40
tf
−
9
20
QT
−
15.3
22
Q1
−
4.1
−
Q2
−
7.1
−
Q3
−
6.8
−
−
−
1.8
1.5
5.0
−
trr
−
112
−
ta
−
92
−
tb
−
20
−
QRR
−
0.603
−
mC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
−
4.5
−
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
−
7.5
−
nH
OFF CHARACTERISTICS
V(BR)DSS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0)
IGSS
mAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 3.0 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
(VDD = 50 Vdc, ID = 6.0 Adc,
VGS = 10 Vdc, RG = 9.1 W)
Turn−Off Delay Time
Fall Time
Gate Charge (See Figure 8)
(VDS = 80 Vdc, ID = 6.0 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure 14)
(IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
MTD6P10E
TYPICAL ELECTRICAL CHARACTERISTICS
12
9V
10
8
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
12
VGS = 10 V
TJ = 25°C
8V
6
7V
4
6V
2
TJ = −55°C
VDS ≥ 10 V
25°C
10
100°C
8
6
4
2
5V
2
4
6
8
10
12
14
16
18
0
20
4
5
6
7
8
9
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
1.1
1.0
TJ = 100°C
0.9
0.8
0.7
25°C
0.6
0.5
−55 °C
0.4
0.3
3
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.3
1.2
2
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
0
2
4
6
8
10
12
TJ = 25°C
0.9
0.8
0.7
VGS = 10 V
0.6
15 V
0.5
0.4
0
2
4
6
8
10
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
12
100
1.8
1.6
10
1.0
VGS = 10 V
ID = 3 A
VGS = 0 V
1.4
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
1.2
1.0
0.8
TJ = 125°C
0.6
0.4
− 50
− 25
0
25
50
75
100
125
10
− 120
150
− 100
− 80
− 60
− 40
− 20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
0
MTD6P10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1600
C, CAPACITANCE (pF)
VGS = 0 V
VDS = 0 V
1400
TJ = 25°C
Ciss
1200
1000
800
Crss
600
Ciss
400
200
0
Coss
Crss
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
12
90
QT
10
Q1
75
VGS
Q2
8
60
6
45
4
30
ID = 6 A
TJ = 25°C
2
0
15
VDS
Q3
0
2
4
6
8
10
QT, TOTAL CHARGE (nC)
12
14
0
16
1000
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTD6P10E
VDD = 50 V
ID = 6 A
VGS = 10 V
TJ = 25°C
100
tr
td(off)
td(on)
tf
10
1
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
6
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
0.50
0.75
1.0
1.25
1.50
1.75
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
2.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTD6P10E
SAFE OPERATING AREA
200
VGS = 10 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10
100 ms
1 ms
10 ms
1.0
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
dc
1.0
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
160
120
80
40
0
100
ID = 6 A
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
150
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1 0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E−05
t1
t2
DUTY CYCLE, D = t1/t2
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
MTD6P10E
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
−T−
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local
Sales Representative
MTD6P10E/D
