MVDF1N05ER2G

MMDF1N05E, MVDF1N05E Power MOSFET 2 A, 50 V, N−Channel SO−8, Dual These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a low reverse recovery time. These devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. http://onsemi.com 2 AMPERE, 50 VOLTS RDS(on) = 300 mW N−Channel D Features • • • • • • • • • • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs Miniature SO−8 Surface Mount Package − Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed Avalanche Energy Specified Mounting Information for SO−8 Package Provided IDSS Specified at Elevated Temperature This is a Pb−Free Device MVDF Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDS 50 V Gate−to−Source Voltage − Continuous VGS ± 20 V ID A IDM 2.0 10 EAS 300 mJ TJ, Tstg −55 to 150 °C Drain Current − Continuous Drain Current − Pulsed Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 V, VGS = 10 V, IL = 2 Apk) Operating and Storage Temperature Range Total Power Dissipation @ TA = 25°C Thermal Resistance, Junction−to−Ambient (Note 1) Maximum Temperature for Soldering, Time in Solder Bath December, 2012 − Rev. 11 S MARKING DIAGRAM 8 SO−8 CASE 751 STYLE 11 8 1 F1N05 AYWWG G 1 F1N05 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT Source−1 1 8 Drain−1 Gate−1 2 7 Drain−1 Source−2 3 6 Drain−2 Gate−2 4 5 Drain−2 Top View PD 2.0 W RqJA 62.5 °C/W TL 260 10 °C Sec Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10 sec. max. © Semiconductor Components Industries, LLC, 2012 G 1 ORDERING INFORMATION Device Package Shipping† MMDF1N05ER2G SO−8 2,500/Tape & Reel (Pb−Free) MVDF1N05ER2G SO−8 2,500/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MMDF1N05E/D MMDF1N05E, MVDF1N05E ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit V(BR)DSS 50 − − Vdc Zero Gate Voltage Drain Current (VDS = 50 V, VGS = 0) IDSS − − 2 mAdc Gate−Body Leakage Current (VGS = 20 Vdc, VDS = 0) IGSS − − 100 nAdc Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) VGS(th) 1.0 − 3.0 Vdc Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 4.5 Vdc, ID = 0.6 Adc) RDS(on) RDS(on) − − − − 0.30 0.50 gFS − 1.5 − mhos Ciss − 330 − pF Coss − 160 − Crss − 50 − td(on) − − 20 tr − − 30 td(off) − − 40 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0, ID = 250 mA) ON CHARACTERISTICS (Note 2) Forward Transconductance (VDS = 15 V, ID = 1.5 A) W DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 V, VGS = 0, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 10 V, ID = 1.5 A, RL = 10 W, VG = 10 V, RG = 50 W) Fall Time Total Gate Charge Gate−Source Charge Gate−Drain Charge (VDS = 10 V, ID = 1.5 A, VGS = 10 V) ns tf − − 25 Qg − 12.5 − Qgs − 1.9 − Qgd − 3.0 − VSD − − 1.6 V trr − 45 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C) Forward Voltage (Note 2) Reverse Recovery Time (IS = 1.5 A, VGS = 0 V) (dIS/dt = 100 A/ms) 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 MMDF1N05E, MVDF1N05E TYPICAL ELECTRICAL CHARACTERISTICS 10 6V 8V 10 TJ = 25°C 8 4.5 V 6 4V 4 VGS = 3.5 V 2 8 0 2 4 6 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 6 4 25°C 2 0 10 0 1 RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE ON-RESISTANCE (OHMS) VGS = 10 V 0.4 0.3 100°C 25°C 0.1 -55°C 0 2 4 ID, DRAIN CURRENT (AMPS) 6 8 0.5 ID = 1.5 A 0.4 0.3 0.2 0.1 2 3 4 5 6 7 8 125 150 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 9 1.8 1.6 1.4 VGS = 10 V ID = 1.5 A 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) Figure 4. On−Resistance Variation with Temperature V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 3. On−Resistance versus Drain Current 0 -55°C 3 Figure 2. Transfer Characteristics 0.5 0 2 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics 0.2 25°C 100°C 100°C 0 -55°C VDS ≥ 10 V 5V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 10 V 10 1.2 VDS = VGS ID = 1 mA 1.1 1 0.9 0.8 0.7 -50 Figure 5. On Resistance versus Gate−To−Source Voltage -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 Figure 6. Gate Threshold Voltage Variation with Temperature http://onsemi.com 3 150 MMDF1N05E, MVDF1N05E VGS 1200 VDS 12 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 25°C Crss 1000 C, CAPACITANCE (pF) 0 Ciss 800 VDS = 0 VGS = 0 600 Ciss 400 Coss 200 Crss 0 VDS = 25 V ID = 1.2 A 10 8 6 4 2 0 25 15 5 5 10 15 20 10 0 20 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0 2 Figure 7. Capacitance Variation 4 6 8 10 12 Qg, TOTAL GATE CHARGE (nC) 14 16 Figure 8. Gate Charge versus Gate−To−Source Voltage SAFE OPERATING AREA INFORMATION 100 I D , DRAIN CURRENT (AMPS) Forward Biased Safe Operating Area The FBSOA curves define the maximum drain−to−source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. ON Semiconductor Application Note, AN569, “Transient Thermal Resistance − General Data and Its Use” provides detailed instructions. 10 VGS = 20 V SINGLE PULSE TC = 25°C Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max. 100 ms 10 ms 1 10 ms dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.01 0.1 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 9. Maximum Rated Forward Biased Safe Operating Area Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 Normalized to qja at 10s. Chip 0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F 0.01 0.01 SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 Figure 10. Thermal Response http://onsemi.com 4 1.0E+01 1.0E+02 Ambient 1.0E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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