N01S830BAT22IT

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. N01S830HA, N01S830BA 1 Mb Ultra-Low Power Serial SRAM Standard SPI Interface and Multiplex DUAL and QUAD Interface www.onsemi.com Overview The ON Semiconductor serial SRAM family includes several integrated memory devices including this 1 Mb serially accessed Static Random Access Memory, internally organized as 128 K words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) protocol. In SPI mode, a single data-in (SI) and data-out (SO) line is used along with the clock (SCK) to access data within the device. In DUAL mode, two multiplexed data-in/data-out (SIO0-SIO1) lines are used and in QUAD mode, four multiplexed data-in/data-out (SIO0-SIO3) lines are used with the clock to access the memory. The devices can operate over a wide temperature range of −40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead TSSOP package. The N01S830xA device has two different variations, a HOLD version that allows communication to the device to be paused and a battery back-up (BBU) version to be used with a battery to retain data when power is lost. Features • • • • • • • • • • • Power Supply Range: 2.5 to 5.5 V Very Low Typical Standby Current < 4 mA at +85°C Very Low Operating Current < 10 mA Simple Serial Interface ♦ Single-bit SPI Access ♦ DUAL-bit and QUAD-bit SPI-like Access Flexible Operating Modes ♦ Word Mode ♦ Page Mode ♦ Burst Mode (Full Array) High Frequency Read and Write Operation ♦ Clock Frequency up to 20 MHz Functional Options ♦ HOLD Pin for Pausing Operation ♦ VBAT Pin for Battery−Back up Built-in Write Protection (CS High) High Reliability ♦ Unlimited Write Cycles Temperature Ranges Supported ♦ Industrial (I): TA = −40°C to +85°C ♦ Automotive (E): TA = −40°C to +125°C These Devices are Pb−Free and are RoHS Compliant ♦ Green TSSOP © Semiconductor Components Industries, LLC, 2016 February, 2016 − Rev. 2 TSSOP8 3x4.4 CASE 948BH PACKAGE CONFIGURATION CS 1 8 VCC SO / SIO1 2 7 HOLD / SIO3 NC / SIO2 3 6 SCK VSS 4 5 SI / SIO0 HOLD Version CS 1 8 VCC SO / SIO1 2 7 VBAT NC 3 6 SCK VSS 4 5 SI / SIO0 BBU Version ORDERING INFORMATION Device Package Shipping† N01S830HAT22I TSSOP−8 (Pb−Free) 100 Units / Tube TSSOP−8 (Pb−Free) 3000 / Tape & Reel TSSOP−8 (Pb−Free) 100 Units / Tube TSSOP−8 (Pb−Free) 3000 / Tape & Reel N01S830BAT22I N01S830HAT22IT N01S830BAT22IT N01S830HAT22E N01S830BAT22E N01S830HAT22ET N01S830BAT22ET †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: N01S830HA/D N01S830HA, N01S830BA Table 1. DEVICE OPTIONS Power Supply Speed Package Temperature Range Function N01S830HAT22 HV 2.5 V − 5.5 V 20 MHz for I−Temp, 16 MHz E−Temp TSSOP−8 I, E HOLD N01S830BAT22 HV 2.5 V − 5.5 V 20 MHz for I−Temp, 16 MHz E−Temp TSSOP−8 I, E BBU − Battery Back-up Device / Part Number Table 2. PIN NAMES Pin Name Pin Function CS Chip Select SCK Serial Clock SI / SIO0 Data Input − SPI mode Data Input/Output 0 − DUAL and QUAD mode SO / SIO1 Data Output − SPI mode Data Input/Output 1 − DUAL and QUAD mode NC / SIO2 No Connect − SPI and DUAL mode Data Input/Output 2 − QUAD mode HOLD / SIO3 HOLD Version HOLD Input − SPI and DUAL mode Data Input/Output 3 − QUAD mode VBAT BBU Version Battery Supply − SPI and DUAL mode VCC Power VSS Ground Decode Logic SCK CS SI / SIO0 Interface Circuitry Control Logic SRAM Array SO / SIO1 Data Flow Circuitry SIO2 HOLD / SIO3 (HOLD Version) VBAT Battery Controls (BBU Version) Figure 1. Functional Block Diagram Table 3. CONTROL SIGNAL DESCRIPTIONS Signal Mode Used Name Description CS All Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence being started. SCK All Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of SCK. SI SPI Serial Data In SO SPI Serial Data Out Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. www.onsemi.com 2 N01S830HA, N01S830BA Table 3. CONTROL SIGNAL DESCRIPTIONS Signal Mode Used Name Description HOLD SPI and DUAL Hold A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the HOLD function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z. VBAT SPI and DUAL Battery Voltage SIO0 - 1 DUAL Serial Data Input / Output Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL access mode. SIO0 - 3 QUAD Serial Data Input / Output Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD access mode. Provides the battery power connection to retain data in battery backed mode. Basic Operation By programming the device through a command instruction, the dual and quad access modes may be initiated. In these modes, multiplexed I/O lines take the place of the SPI SI and SO pins and along with the CS and SCK control the device in a SPI-like, two bit (DUAL) and four bit (QUAD) wide serial manner. Once the device is put into either the DUAL or QUAD mode, the device will remain operating in that mode until powered down or the Reset Mode operation is programmed. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. The 1 Mb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro-controllers in the default state. It may also interface with other non-SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The Hold operation is only supported in SPI and DUAL modes. Table 4. INSTRUCTION SET Instruction Command Description READ 03h Read data from memory starting at selected address WRITE 02h Write (program) data to memory starting at selected address EQIO 38h Enable QUAD I/O access EDIO 3Bh Enable DUAL I/O access RSTQIO FFh Reset from QUAD and DUAL to SPI I/O access RDMR 05h Read mode register WRMR 01h Write mode register www.onsemi.com 3 N01S830HA, N01S830BA DEVICE OPERATIONS Read Operation By continuing to provide clock cycles to the device, data can continue to be read out of the memory array in sequentially. The internal address pointer is automatically incremented to the next higher address after each byte of data is read out until the highest memory address is reached. When the highest memory address is reached, 1FFFFh, the address pointer wraps to the address 00000h. This allows the read cycles to be continued indefinitely. All Read operations are terminated by pulling CS high. The serial SRAM Read operation is started by by enabling CS low. First, the 8-bit Read instruction is transmitted to the device through the SI (or SIO0-3) pin(s) followed by the 24-bit address with the 7 MSBs of the address being “don’t care” bits and ignored. In SPI mode, after the READ instruction and address bits are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time. Additional “dummy” clock cycles (four in DUAL and two in QUAD) are required to follow the instruction and address inputs prior to the data being driven out on the SIO0-3 pins while operating in these two modes. CS SCK 0 1 2 3 4 5 6 7 8 9 23 22 Instruction SI 0 0 0 0 0 10 11 29 30 31 1 0 32 33 34 7 6 5 35 36 37 38 39 2 1 0 24−bit address 0 1 1 21 20 2 Data Out High−Z SO 4 3 Figure 2. SPI Read Sequence (Single Byte) CS SCK 0 1 2 3 4 5 6 7 8 9 23 22 Instruction SI 0 0 0 0 0 10 29 11 30 31 1 0 32 1 1 21 20 2 SO 42 43 44 45 35 36 37 38 39 1 0 Don’t Care ADDR 1 41 34 24−bit address 0 Data Out from ADDR 1 7 High−Z 40 33 46 47 48 49 50 51 52 53 54 6 5 4 3 2 55 Don’t Care Data Out from ADDR 3 Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Data Out from ADDR n 1 0 ... 7 6 Figure 3. SPI Read Sequence (Sequential Bytes) www.onsemi.com 4 5 4 3 2 1 0 N01S830HA, N01S830BA CS SCK 0 1 2 3 4 5 Instruction 12 14 15 16 17 18 19 21 22 A3 23 24 25 26 Data out A2 A1 A0 X X X X H0 H0 MSB Notes: 20 24−bit address C3 C2 C1 C0 A11 A10 SIO[1:0] 13 L0 L0 H1 H1 L1 L1 MSB C[3:0] = 03h H0 = 2 high order bits of data byte 0 L0 = 2 low order bits of data byte 0 H1 = 2 high order bits of data byte 1 L1 = 2 low order bits of data byte 1 Figure 4. DUAL Read Sequence CS SCK 0 1 2 3 Instruction SIO[3:0] C1 C0 4 5 6 7 8 9 11 12 24−bit address A5 A4 A3 A2 A1 13 14 15 16 Data out A0 X X H0 MSB Notes: 10 L0 H1 L1 H2 L2 H3 L3 MSB C[1:0] = 03h H0 = 4 high order bits of data byte 0 L0 = 4 low order bits of data byte 0 H1 = 4 high order bits of data byte 1 L1 = 4 low order bits of data byte 1 Figure 5. QUAD Read Sequence Write Operation page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached, 1FFFFh, the address counter wraps to the address 00000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted to the device followed by the 24-bit address with the 7 MSBs being don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the www.onsemi.com 5 N01S830HA, N01S830BA CS SCK 0 1 2 3 4 5 6 7 8 9 10 Instruction 0 SI 0 0 0 11 29 30 31 32 33 24−bit address 0 0 1 0 23 22 21 20 34 35 36 37 38 39 1 0 Data In to ADDR 1 2 1 0 7 53 54 55 6 5 4 3 2 ADDR 1 High−Z SO 40 41 42 43 44 45 46 47 48 Data In to ADDR 2 7 6 5 4 3 49 50 51 52 Data In to ADDR 3 2 1 0 7 6 5 4 3 Data In to ADDR n 2 1 0 ... 7 6 5 4 3 2 High−Z Figure 6. SPI Write Sequence CS SCK 0 1 2 3 4 Instruction SIO1:0] 5 12 13 14 15 17 18 19 24−bit address C3 C2 C1 C0 A11 A10 A3 A2 20 21 Data in A1 A0 H0 H0 L0 L0 H1 H1 MSB MSB Notes: 16 C[3:0] = 02h H0 = 2 high order bits of data byte 0 L0 = 2 low order bits of data byte 0 H1 = 2 high order bits of data byte 1 L1 = 2 low order bits of data byte 1 Figure 7. DUAL Write Sequence www.onsemi.com 6 Ln Ln 1 0 N01S830HA, N01S830BA CS SCK 0 1 2 3 Instruction SIO[3:0] C1 C0 4 5 6 7 9 10 11 24−bit address A5 A4 A3 A2 12 13 Data in A1 A0 H0 MSB Notes: 8 L0 H1 L1 H2 L2 Hn Ln MSB C[1:0] = 02h H0 = 4 high order bits of data byte 0 L0 = 4 low order bits of data byte 0 H1 = 4 high order bits of data byte 1 L1 = 4 low order bits of data byte 1 Figure 8. QUAD Write Sequence READ Mode Register (RDMR) This instruction provides the ability to read the mode register. The register may be read at any time including during a Write operation. The Read Mode Register operation is executed by driving CS low, then sending the RDMR instruction to the device. Immediately after the instruction, the device outputs data on the SO (SIO0-3) pin(s). To complete the operation, drive CS high to terminate the register read. CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 0 1 1 Mode Register Data Out High−Z SO 7 6 5 4 3 2 1 0 Figure 9. SPI Read Mode Register Sequence (RDMR) CS SCK 0 1 2 3 Instruction SIO[1:0] C3 C2 C1 C0 4 5 6 7 Mode Bits H Notes: C[3:0] = 05h H L L MSB Figure 10. DUAL Read Mode Register Sequence (RDMR) www.onsemi.com 7 N01S830HA, N01S830BA CS SCK 0 1 2 3 Instruction Mode Bits SIO[3:0] C1 C0 H Notes: C[1:0] = 05h L MSB Figure 11. QUAD Read Mode Register Sequence (RDMR) Write Mode Register (WRMR) This instruction provides the ability to write the mode register. The Write Mode Register operation is executed by driving CS low, then sending the WRMR instruction to the device. Immediately after the instruction, the data is driven to the device on the SO (SIO0-3) pin(s). To complete the operation, drive CS high to terminate the register write. CS SCK 0 1 2 3 4 5 6 7 8 9 Instruction 10 11 12 13 14 15 1 0 Mode Register Data In SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 High−Z SO Figure 12. SPI Write Mode Register Sequence CS SCK 0 1 2 3 Instruction SIO[1:0] 4 5 6 7 Notes: C[3:0] = 01h Mode Bits C3 C2 C1 C0 H H L L MSB Figure 13. DUAL Write Mode Register Sequence CS SCK 0 1 2 3 Instruction Mode Bits SIO[3:0] C1 C0 H Notes: C[1:0] = 01h L MSB Figure 14. QUAD Write Mode Register Sequence www.onsemi.com 8 N01S830HA, N01S830BA Battery Back-Up Operation Table 5. MODE REGISTER Bit The Battery Back-Up function is available on the BBU version of the serial SRAM. This version of the SRAM cannot operate in the QUAD mode since the SIO3 input is used for the VBAT connection. A standard coin cell battery should be connected to the VBAT pin. On chip circuitry monitors the VCC pin and when it is determined that the main VCC power supply is turning off, the device automatically switches the memory array to VBAT power input. When in battery back-up mode and 3.0 to 3.4 V power supplied to the VBAT input, memory data is retained in the SRAM array and all existing interface and operating mode information is retained. Function 0 Hold Function 1 = Hold function disabled 0 = Hold function enabled (Default) 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 6 Operating Mode Bit 7 Bit 6 0 0 = Word Mode 1 0 = Page Mode 0 1 = Burst Mode (Default) 1 1 = Reserved 7 VCC CS SO NC VBAT Serial SRAM SCK Coin Cell Battery 3.0 to 3.4 V SI Power-Up State VSS The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS = 1. A low level on CS is required to enter a active state. Figure 15. Battery Back-Up Version Schematics Table 6. ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Units VIN,OUT –0.3 to VCC + 0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 5.5 V Power Dissipation PD 500 mW TSTG −40°C to 125°C °C Ambient Temperature Under Bias TA −40°C to +125°C °C Soldering Temperature and Time TSOLDER 260°C, 10 sec °C Voltage on any pin relative to VSS Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 7. OPERATING CHARACTERISTICS (Industrial (I): TA= −40°C to +85°C, Automotive (E): TA = −40°C to +125°C) Item Symbol Test Conditions Min Typ (Note 1) Max Units 5.5 V Supply Voltage VCC 2.5 Data Retention Voltage VDR 1.0 Input High Voltage VIH 0.7 VCC VCC + 0.3 V Input Low Voltage VIL −0.3 0.1 VCC V Output High Voltage VOH Output Low Voltage VOL IOL = 1 mA 0.2 V ILI CS = VCC, VIN = 0 to VCC 1.0 mA Input Leakage Current IOH = −0.4 mA V VCC − 0.2 V Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 1.0 mA Operating Current ICC f = 20 MHz, IOUT = 0, SPI / DUAL 10 mA Standby Current ISB CS = VCC, VIN = VSS or VCC, I−Temp f = 20 MHz, IOUT = 0, QUAD CS = VCC, VIN = VSS or VCC, E−Temp 1. Typical values are measured at VCC = VCC Typ., TA = 25°C and are not 100% tested. www.onsemi.com 9 20 4 10 20 mA N01S830HA, N01S830BA Table 8. CAPACITANCE (Note 2) Symbol Test Conditions Max Units Input Capacitance Item CIN VIN = 0 V, f = 1 MHz, TA = 25°C Min 7 pF I/O Capacitance CI/O VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF 2. These parameters are verified in device characterization and are not 100% tested. Table 9. TIMING TEST CONDITIONS Item Value Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30 pF Operating Temperature Industrial (I): −40°C to +85°C Automotive (E): −40°C to +125°C Table 10. TIMING I−Temp Characteristic Symbol Min E−Temp Max Min Max Units Clock Frequency fCLK 20 16 MHz Clock Rise Time tR 20 20 ns 20 ns Clock Fall Time tF Clock High Time tHI 25 32 ns Clock Low Time tLO 25 32 ns Clock Delay Time tCLD 25 32 ns CS Setup Time tCSS 25 32 ns CS Hold Time tCSH 50 50 ns CS Disable Time tCSD 25 32 ns SCK to CS tSCS 5 5 ns Data Setup Time tSU 10 10 ns Data Hold Time tHD 10 10 ns Output Valid From Clock Low Output Hold Time Output Disable Time 20 tV tHO 25 0 tRDIS 32 0 20 ns ns 20 ns HOLD Setup Time tHS 10 10 ns HOLD Hold Time tHH 10 10 ns HOLD Low to Output High−Z tHZ 10 HOLD High to Output Valid tHV 10 50 www.onsemi.com 10 ns 50 ns N01S830HA, N01S830BA tCSD tCLD CS tR tF tCSH tSCS tCSS SCK tSU tHD MSB in SI LSB in High−Z SO Figure 16. SPI Input Timing CS tLO tHI tCSH SCK tV tDIS SO MSB out LSB out Don’t Care SI Figure 17. SPI Output Timing CS tHS tHS tHH SCK tHH SO n+2 n+1 n High−Z tHV n tHZ SI n+2 n+1 n−1 tSU n Don’t Care HOLD Figure 18. SPI Hold Timing www.onsemi.com 11 n n−1 N01S830HA, N01S830BA tCSD tCLD CS tR tF tCSH tSCS tCSS SCK tSU tHD MSB in SI0 LSB in Figure 19. QUAD Input Timing CS tLO tHI tCSH SCK tV tDIS SIO MSB out LSB out Figure 20. QUAD Output Timing www.onsemi.com 12 N01S830HA, N01S830BA PACKAGE DIMENSIONS TSSOP8 3x4.4 / TSSOP8 (225 mil) CASE 948BH ISSUE O ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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