N02L83W2A

N02L83W2A 2Mb Ultra-Low Power Asynchronous CMOS SRAM 256K × 8 bit Overview The N02L83W2A is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 262,144 words by 8 bits. The device is designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. The N02L83W2A is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 256Kb x 8 SRAMs Features • Single Wide Power Supply Range 2.3 to 3.6 Volts • Very low standby current 2.0µA at 3.0V (Typical) • Very low operating current 2.0mA at 3.0V and 1µs (Typical) • Very low Page Mode operating current 0.8mA at 3.0V and 1µs (Typical) • Simple memory control Dual Chip Enables (CE1 and CE2) Output Enable (OE) for memory expansion • Low voltage data retention Vcc = 1.8V • Very fast output enable access time 30ns OE access time • Automatic power down to standby mode • TTL compatible three-state output driver Product Family Part Number N02L83W2AT N02L83W2AN N02L83W2AT2 N02L83W2AN2 Package Type 32 - TSOP I 32 - STSOP I 32 - TSOP I Green 32 - STSOP I Green 55ns @ 2.7V -40oC to +85oC 2.3V - 3.6V 70ns @ 2.3V 2 µA 2 mA @ 1MHz Operating Power Temperature Supply (Vcc) Speed Standby Operating Current (ISB), Current (Icc), Typical Typical Pin Configuration A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 Pin Descriptions Pin Name A0-A17 WE CE1, CE2 OE I/O0-I/O7 VCC VSS Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Data Inputs/Outputs Power Ground N02L83W2A STSOP-I, TSOP-I ©2008 SCILLC. All rights reserved. July 2008 - Rev. 8 Publication Order Number: N02L83W2A/D N02L83W2A Functional Block Diagram Address Inputs A0 - A3 Word Address Decode Logic Word Mux Input/ Output Mux and Buffers Address Inputs A4 - A17 Page Address Decode Logic 16K Page x 16 word x 8 bit RAM Array I/O0 - I/O7 CE1 CE2 WE OE Control Logic Functional Description CE1 H X L L L CE2 X L H H H WE X X L H H OE X X X2 L H I/O0 - I/O7 High Z High Z Data In Data Out High Z MODE Standby1 Standby Write2 Read Active 1 POWER Standby Standby Active Active Active 1. When the device is in standby mode, control inputs (WE and OE), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 2. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. Capacitance1 Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF VIN = 0V, f = 1 MHz, TA = 25oC 1. These parameters are verified in device characterization and are not 100% tested Rev. 8 | Page 2 of 10 | www.onsemi.com N02L83W2A Absolute Maximum Ratings1 Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER Rating –0.3 to VCC+0.3 –0.3 to 4.5 500 –40 to 125 -40 to +85 260oC, 10sec Unit V V mW oC oC oC 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 µs Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Page Mode Operating Supply Current @ 70 ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) Read/Write Quiescent Operating Supply Current3 Symbol VCC VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f=0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V VCC = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 2.0 2.0 12.0 Chip Disabled3 Test Conditions Min. 2.3 1.8 1.8 –0.3 VCC–0.2 0.2 0.5 0.5 4.0 16.0 VCC+0.3 0.6 Typ1 3.0 Max 3.6 Unit V V V V V V µA µA mA mA ICC3 4.0 mA ICC4 3.0 mA Maximum Standby Current3 ISB1 20.0 µA Maximum Data Retention Current3 IDR 10.0 µA 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. Rev. 8 | Page 3 of 10 | www.onsemi.com N02L83W2A Power Savings with Page Mode Operation (WE = VIH) Page Address (A4 - A17) Open page ... Word Address (A0 - A3) Word 1 Word 2 Word 16 CE1 CE2 OE Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 8-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Rev. 8 | Page 4 of 10 | www.onsemi.com N02L83W2A Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85 oC Timing Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAW tWP tAS tWR tWHZ tDW tDH tOW 40 0 5 10 5 0 0 10 70 50 50 40 0 0 20 35 0 5 20 20 2.3 - 3.6 V Min. 70 70 70 35 10 5 0 0 10 55 45 45 35 0 0 15 15 15 Max. 2.7 - 3.6 V Min. 55 55 55 30 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. 8 | Page 5 of 10 | www.onsemi.com N02L83W2A Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA tHZ CE1 tCO CE2 tLZ tOE OE tOLZ Data Out High-Z Data Valid tOHZ Rev. 8 | Page 6 of 10 | www.onsemi.com N02L83W2A Timing Waveform of Write Cycle (WE control) tWC Address tAW CE1 tCW CE2 tAS WE tDW High-Z Data In tWHZ Data Out High-Z tDH tWP tWR Data Valid tOW Timing Waveform of Write Cycle (CE1 Control) tWC Address tAW CE1 (for CE2 Control, use inverted signal) tAS tCW tWR tWP WE tDW Data In tLZ Data Out tWHZ tDH Data Valid High-Z Rev. 8 | Page 7 of 10 | www.onsemi.com N02L83W2A 32-Lead TSOP-I Package (T32) 18.40±0.10 0.50mm REF 8.0±0.10 0.27 0.17 20.0±0.20 SEE DETAIL B DETAIL B 1.10±0.15 0o-8o 0.20 0.00 0.80mm REF Note: 1. All dimensions in millimeters 2. Package dimensions exclude molding flash Rev. 8 | Page 8 of 10 | www.onsemi.com N02L83W2A 32-Lead STSOP-I Package (N32) 11.80±0.10 0.50mm REF 8.0±0.10 0.27 0.17 13.40±0.20 SEE DETAIL B DETAIL B 1.10±0.15 0o-8o 0.20 0.00 0.80mm REF Note: 1. All dimensions in millimeters 2. Package dimensions exclude molding flash Rev. 8 | Page 9 of 10 | www.onsemi.com N02L83W2A Ordering Information Part Number N02L83W2AT5I N02L83W2AT25I N02L83W2AN5I N02L83W2AN25I N02L83W2AT5IT N02L83W2AT25IT N02L83W2AN5IT N02L83W2AN25IT Package Leaded 32-TSOP I Green 32-TSOP I (RoHS Compliant) Leaded 32-sTSOP I Green 32-sTSOP I (RoHS Compliant) Leaded 32-TSOP I Green 32-TSOP I (RoHS Compliant) Leaded 32-sTSOP I Green 32-sTSOP I (RoHS Compliant) Shipping Method Tray Tray Tray Tray Tape & Reel Tape & Reel Tape & Reel Tape & Reel Revision History Revision # A B Date Jan 2001 Mar 2001 Initial Advance Release Added Table 3: Capacitance Revised quiescent operating current, changed pin 31 to CE1, modified table 1 and figure 2, other minor edits Part number change from EM256L08, modified Overview and Features, added Page Mode Operation diagram and Package diagram, revised Operating Characteristics table, Functional Description table, Timing diagrams, and Ordering Information diagram Replaced Isb and Icc on Product Family table with typical values Added Green Package Option RoHS Compliant added onto Green packages Converted to ON Semiconductor and new part numbers Change Description C D E F G 8 Dec. 2001 Nov. 2002 Oct. 2004 Dec. 2005 July 2008 September 2006 Converted to AMI Semiconductor ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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