N04L63W2AT7IT

N04L63W2A 4Mb Ultra-Low Power Asynchronous CMOS SRAM 256K × 16 bit Overview The N04L63W2A is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits. The device is designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The N04L63W2A is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in JEDEC standard packages compatible with other standard 256Kb x 16 SRAMs Features • Single Wide Power Supply Range 2.3 to 3.6 Volts • Very low standby current 4.0µA at 3.0V (Typical) • Very low operating current 2.0mA at 3.0V and 1µs (Typical) • Very low Page Mode operating current 0.8mA at 3.0V and 1µs (Typical) • Simple memory control Dual Chip Enables (CE1 and CE2) Output Enable (OE) for memory expansion • Low voltage data retention Vcc = 1.8V • Very fast output enable access time 25ns OE access time • Automatic power down to standby mode • TTL compatible three-state output driver • Compact space saving BGA package available Product Family Part Number N04L63W2AB N04L63W2AT N04L63W2AB2 N04L63W2AT2 Package Type 48 - BGA 44 - TSOP II 48 - BGA Green 44 - TSOP II Green 70ns @ 2.7V -40oC to +85oC 2.3V - 3.6V 55ns @ 2.7V 4 µA 2 mA @ 1MHz Operating Temperature Power Supply (Vcc) Speed Options Standby Operating Current (ISB), Current (Icc), Typical Typical Pin Configuration A4 A3 A2 A1 A0 CE1 I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN ONE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CE2 A8 A9 A10 A11 A17 1 A B C D E F G H LB I/O8 I/O9 VSS VCC 2 OE UB I/O10 I/O11 I/O12 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 NC Pin Descriptions Pin Name A0-A17 WE CE1, CE2 OE LB UB I/O0-I/O15 VCC VSS NC Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Ground Not Connected N04L63W2A TSOP-II I/O14 I/O13 I/O15 NC NC A8 48 Pin BGA (top) 6 x 8 mm ©2008 SCILLC. All rights reserved. July 2008 - Rev. 10 Publication Order Number: N04L63W2A/D N04L63W2A Functional Block Diagram Address Inputs A0 - A3 Word Address Decode Logic Address Inputs A4 - A17 Page Address Decode Logic 16K Page x 16 word x 16 bit RAM Array Input/ Output Mux and Buffers Word Mux I/O0 - I/O7 I/O8 - I/O15 CE1 CE2 WE OE UB LB Control Logic Functional Description CE1 H X L L L L CE2 X L H H H H WE X X X L H H OE X X X X3 L H UB X X H L 1 LB X X H L 1 I/O0 - I/O151 High Z High Z High Z Data In Data Out High Z MODE Standby2 Standby2 Standby Write3 Read Active POWER Standby Standby Standby Active Active Active L1 L1 L1 L 1 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. Capacitance1 Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25 C o Min Max 8 8 Unit pF pF 1. These parameters are verified in device characterization and are not 100% tested Rev. 10 | Page 2 of 10 | www.onsemi.com N04L63W2A Absolute Maximum Ratings1 Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER Rating –0.3 to VCC+0.3 –0.3 to 4.5 500 –40 to 125 -40 to +85 260oC, 10sec Unit V V mW oC oC oC 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 µs Cycle Time2 Read/Write Operating Supply Current @ 70 ns Cycle Time2 Page Mode Operating Supply Current @ 70ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) Read/Write Quiescent Operating Supply Current3 Symbol VCC VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f=0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.6 V Vcc = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85oC 4.0 2.0 10.0 Chip Disabled 3 Test Conditions Min. 2.3 1.8 1.8 –0.3 VCC–0.2 Typ1 3.0 Max 3.6 3.6 VCC+0.3 0.6 0.2 0.5 0.5 3.0 16.0 Unit V V V V V V µA µA mA mA ICC3 4.0 mA ICC4 2.0 mA Maximum Standby Current3 ISB1 20.0 µA Maximum Data Retention Current3 IDR 10 µA 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. Rev. 10 | Page 3 of 10 | www.onsemi.com N04L63W2A Power Savings with Page Mode Operation (WE = VIH) Page Address (A4 - A17) Open page ... Word Address (A0 - A3) Word 1 Word 2 Word 16 CE1 CE2 OE LB, UB Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Rev. 10 | Page 4 of 10 | www.onsemi.com N04L63W2A Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85 oC Timing -70 Item Symbol 2.3 - 2.65 V Min. Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output tRC tAA tCO tOE tLB, tUB tLZ tOLZ tBZ tHZ tOHZ tBHZ tOH tWC tCW tAW tBW tWP tAS tWR tWHZ tDW tDH tOW 40 0 5 10 5 10 0 0 0 10 85 50 50 50 40 0 0 20 40 0 5 20 20 20 85 85 85 30 85 10 5 10 0 0 0 10 70 50 50 50 40 0 0 20 40 0 5 20 20 20 Max. 2.7 - 3.6 V Min. 70 70 70 25 70 10 5 10 0 0 0 10 55 45 45 45 40 0 0 20 20 20 20 Max. -55 2.7 - 3.6 V Min. 55 55 55 25 55 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units Rev. 10 | Page 5 of 10 | www.onsemi.com N04L63W2A Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA tHZ CE1 tCO CE2 tLZ tOE OE tOLZ tLB, tUB LB, UB tBLZ Data Out High-Z tBHZ Data Valid tOHZ Rev. 10 | Page 6 of 10 | www.onsemi.com N04L63W2A Timing Waveform of Write Cycle (WE control) tWC Address tAW CE1 tCW CE2 tBW LB, UB tAS WE High-Z Data In tWHZ Data Out High-Z tDW tDH tWP tWR Data Valid tOW Timing Waveform of Write Cycle (CE1 Control) tWC Address tAW CE1 (for CE2 Control, use inverted signal) LB, UB tWP WE tDW Data In tLZ Data Out tWHZ tDH tCW tAS tBW tWR Data Valid High-Z Rev. 10 | Page 7 of 10 | www.onsemi.com N04L63W2A 44-Lead TSOP II Package (T44) 18.41±0.13 10.16±0.13 11.76±0.20 0.80mm REF 0.45 0.30 SEE DETAIL B DETAIL B 1.10±0.15 0o-8o 0.20 0.00 0.80mm REF Note: 1. All dimensions in inches (Millimeters) 2. Package dimensions exclude molding flash Rev. 10 | Page 8 of 10 | www.onsemi.com N04L63W2A Ball Grid Array Package A1 BALL PAD CORNER (3) D 0.28±0.05 1.24±0.10 1. 0.35±0.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z SD e SE BOTTOM VIEW Dimensions (mm) e = 0.75 D 6±0.10 E SD 8±0.10 0.375 SE 0.375 J 1.125 K 1.375 BALL MATRIX TYPE FULL Rev. 10 | Page 9 of 10 | www.onsemi.com N04L63W2A Ordering Information Part Number N04L63W2AT7I N04L63W2AT27I N04L63W2AB7I N04L63W2AB27I N04L63W2AT7IT N04L63W2AT27IT N04L63W2AB7IT N04L63W2AB27IT Package Leaded 44-TSOP II Green 44-TSOP II (RoHS Compliant) Leaded 48-BGA Green 48-BGA (RoHS Compliant) Leaded 44-TSOP II Green 44-TSOP II (RoHS Compliant) Leaded 48-BGA Green 48-BGA (RoHS Compliant) Shipping Method Tray Tray Tray Tray Tape & Reel Tape & Reel Tape & Reel Tape & Reel Please contact factory for 55ns speed grade Revision History Revision A B C D E F G H I 10 Date Jan. 2001 Dec. 2001 Nov. 2002 February 2003 August 2004 Oct 2004 Nov. 2005 September 2006 October 2007 July 2008 Initial Preliminary Release Change Description Part number change from EM256J16, modified Overview and Features, added Page Mode Operation diagram, revised Operating Characteristics table, Package diagram, Functional Description table and Ordering Information diagram Replaced Isb and Icc on Product Family table with typical values Added 55ns sort Removed 55ns sort Added Pb-Free and Green Package Option Removed Pb-Free Pkg., added Green Pkg and RoHS Compliant was added Converted to AMI Semiconductor Added 55ns performance sort Converted to ON Semiconductor and new part numbers ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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