N24C02UVTG

2/4/8/16-Kb I2C CMOS Serial EEPROM N24C02, N24C04, N24C08, N24C16 Description The N24C02/04/08/16 are EEPROM Serial 2/4/8/16−Kb I2C devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight N24C02, four N24C04, two N24C08 and one N24C16 device on the same bus. www.onsemi.com US8 U SUFFIX CASE 493 MARKING DIAGRAM 8 8 Features • • • • • • • • • • • • • Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified Supports Standard, Fast and Fast−Plus I2C Protocol 1.7 V / 1.6 V to 5.5 V Supply Voltage Range 16−Byte Page Write Buffer Fast Write Time (4 ms max) Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology More than 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Automotive Grade 1 Temperature Range US 8−Lead Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PIN CONFIGURATION N24C__ 16 / 08 / 04 / 02 NC / NC / NC / A0 NC / NC / A1 / A1 NC / A2 / A2 / A2 VSS XX ALYW 1 1 N24C02UDTG N24C02UVTG N24C08UDTG N24C08UVTG N24C16UDTG N24C16UVTG N24C04UDTG N24C04UVTG XX = Specific Device Code M = Date Code G = Pb−Free Package A = Assembly Location L = Wafer Lot Traceability YW = Date Code (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet. 8 VCC 2 7 WP 3 6 SCL 4 5 SDA 1 XX MG G US8 (U) (Top View) © Semiconductor Components Industries, LLC, 2016 April, 2020 − Rev. 4 1 Publication Order Number: N24C02/D N24C02, N24C04, N24C08, N24C16 VCC Table 1. PIN FUNCTION Pin Name Function A0, A1, A2 SCL A2, A1, A0 N24Cxx SDA WP Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input WP Write Protect Input VCC Power Supply VSS Ground NC No Connect VSS Figure 1. Functional Symbol Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature −65 to +150 °C Voltage on any pin with respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2 and WP should not exceed VCC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of VCC. Table 3. RELIABILITY CHARACTERISTICS Symbol NEND (Note 2) TDR (Note 2) Parameter Endurance Data Retention Min Units 1,000,000 Write Cycles (Note 3) 100 Years 2. TA = 25°C 3. A Write Cycle refers to writing a Byte or a Page. Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Max Units ICCR Read Current Read, fSCL = 1 MHz 0.3 mA ICCW Write Current Write 0.5 mA Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 mA TA = −40°C to +125°C 2 ISB IL Parameter Test Conditions I/O Pin Leakage Pin at GND or VCC VIL1 Input Low Voltage 2.2 V ≤ VCC ≤ 5.5 V VIL2 Input Low Voltage 1.6 V ≤ VCC < 2.2 V VIH1 Input High Voltage VIH2 Min 2 mA −0.5 0.3 VCC V −0.5 0.2 VCC V 2.2 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V Input High Voltage 1.6 V ≤ VCC < 2.2 V 0.8 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.2 V, IOL = 6.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.2 V, IOL = 2.0 mA 0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. *VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C. www.onsemi.com 2 N24C02, N24C04, N24C08, N24C16 Table 5. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF WP Input Current, Address Input Current (A0, A1, A2) VIN < VIH, VCC = 5.5 V 50 mA VIN < VIH, VCC = 3.3 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 IWP, IA (Note 5) Parameter Conditions 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. *VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C. Table 6. A.C. CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 6) Standard FSCL tHD:STA Min Parameter Symbol Clock Frequency Fast Max Min 100 START Condition Hold Time Fast−Plus Max Min 400 Max Units 1,000 kHz 4 0.6 0.26 ms tLOW Low Period of SCL Clock 4.7 1.3 0.50 ms tHIGH High Period of SCL Clock 4 0.6 0.26 ms tSU:STA START Condition Setup Time 4.7 0.6 0.26 ms tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 7) SDA and SCL Rise Time 1,000 300 120 ns tF (Note 7) SDA and SCL Fall Time 300 300 120 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH (Note 7) Ti (Note 7) Data Out Hold Time 4 0.6 0.26 ms 4.7 1.3 0.5 ms 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs 0.9 100 50 0.45 50 50 ms ns 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR tPU (Notes 7, 8) Write Cycle Time Power-up to Ready Mode 4 4 4 ms 0.35 0.35 0.35 ms 6. Test conditions according to “A.C. Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. *VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C. Table 7. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC for VCC ≥ 2.2 V 0.15 x VCC to 0.85 x VCC for VCC < 2.2 V Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.3 x VCC, 0.7 x VCC Output Load Current Source: IOL = 6 mA (VCC ≥ 2.2 V); IOL = 2 mA (VCC < 2.2 V); CL = 100 pF www.onsemi.com 3 N24C02, N24C04, N24C08, N24C16 Power−On Reset (POR) Each N24Cxx* incorporates Power−On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. A N24Cxx device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. *For common features, the N24C02/04/08/16 will be referred to as N24Cxx. During data transfer, the SDA line must remain stable while the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition (Figure 2). The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake−up’ call to all receivers. Absent a START, a Slave will not respond to commands. The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. NOTE: The I/O pins of N24Cxx do not obstruct the SCL and SDA lines if the VCC supply is switched off. During power−up, the SCL and SDA pins (connected with pull−up resistors to VCC) will follow the VCC monotonically from VSS (0 V) to nominal VCC value, regardless of pull−up resistor value. The delta between the VCC and the instantaneous voltage levels during power ramping will be determined by the relation between bus time constant (determined by pull−up resistance and bus capacitance) and actual VCC ramp rate. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven, these pins are pulled LOW internally. WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. When not driven, this pin is pulled LOW internally. Device Addressing The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at 1010 (Ah). The next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. The last bit of the slave address, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension bits are assigned as illustrated in Figure 3. A2, A1 and A0 must match the state of the external address pins, and a10, a9 and a8 are internal address bits. Functional Description The N24Cxx supports the Inter−Integrated Circuit (I2C) Bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. Data flow is controlled by a Master device, which generates the serial clock and all START and STOP conditions. The N24Cxx acts as a Slave device. Master and Slave alternate as either transmitter or receiver. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle (Figure 4). The Slave will also acknowledge the address byte and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, and then releases the SDA line during the 9th clock cycle. As long as the Master acknowledges the data, the Slave will continue transmitting. The Master terminates the session by not acknowledging the last data byte (NoACK) and by issuing a STOP condition. Bus timing is illustrated in Figure 5. I2C Bus Protocol The I2C bus consists of two ‘wires’, SCL and SDA. The two wires are connected to the VCC supply via pull−up resistors. Master and Slave devices connect to the 2−wire bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see AC Characteristics). www.onsemi.com 4 N24C02, N24C04, N24C08, N24C16 SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 R/W N24C02 1 0 1 0 A2 A1 a8 R/W N24C04 1 0 1 0 A2 a9 a8 R/W N24C08 1 0 1 0 a10 a9 a8 R/W N24C16 Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACK SETUP (w tSU:DAT) ACK DELAY (v tAA) START Figure 4. Acknowledge Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 5. Bus Timing www.onsemi.com 5 tBUF N24C02, N24C04, N24C08, N24C16 WRITE OPERATIONS Byte Write are received and the STOP condition has been sent by the Master, the internal Write cycle begins. At this point all received data is written to the N24Cxx in a single write cycle. In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero to the Slave. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the N24Cxx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The N24Cxx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6). While this internal cycle is in progress (tWR), the SDA output will be tri−stated and the N24Cxx will not respond to any request from the Master device (Figure 7). Acknowledge Polling The acknowledge (ACK) polling routine can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the N24Cxx initiates the internal write cycle. The ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the N24Cxx is still busy with the write operation, NoACK will be returned. If the N24Cxx has completed the internal write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Page Write The N24Cxx writes up to 16 bytes of data in a single write cycle, using the Page Write operation (Figure 8). The Page Write operation is initiated in the same manner as the Byte Write operation, however instead of terminating after the data byte is transmitted, the Master is allowed to send up to fifteen additional bytes. After each byte has been transmitted the N24Cxx will respond with an acknowledge and internally increments the four low order address bits. The high order bits that define the page address remain unchanged. If the Master transmits more than sixteen bytes prior to sending the STOP condition, the address counter ‘wraps around’ to the beginning of page and previously transmitted data will be overwritten. Once all sixteen bytes BUS ACTIVITY: MASTER S T A R T Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the operation of the N24Cxx. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the first data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the N24Cxx will not acknowledge the data byte and the Write request will be rejected. Delivery State The N24Cxx is shipped erased, i.e., all bytes are FFh. SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 − a 0 d7 − d 0 S T O P P S SLAVE A C K A C K Figure 6. Byte Write Sequence www.onsemi.com 6 A C K N24C02, N24C04, N24C08, N24C16 SCL 8th Bit SDA ACK Byte n tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: MASTER S T A R T DATA BYTE n ADDRESS BYTE SLAVE ADDRESS DATA BYTE n+1 S T O P DATA BYTE n+P S P A C K SLAVE n=1 P v 15 A C K A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 9 a7 a0 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing www.onsemi.com 7 A C K N24C02, N24C04, N24C08, N24C16 READ OPERATIONS Immediate Read acknowledges the byte address, the Master device resends the START condition and the slave address, this time with the R/W bit set to one. The N24Cxx then responds with its acknowledge and sends the requested data byte. The Master device does not acknowledge the data (NoACK) but will generate a STOP condition (Figure 11). Upon receiving a Slave address with the R/W bit set to ‘1’, the N24Cxx will interpret this as a request for data residing at the current byte address in memory. The N24Cxx will acknowledge the Slave address, will immediately shift out the data residing at the current address, and will then wait for the Master to respond. If the Master does not acknowledge the data (NoACK) and then follows up with a STOP condition (Figure 10), the N24Cxx returns to Standby mode. Sequential Read If during a Read session, the Master acknowledges the 1st data byte, then the N24Cxx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page). Selective Read Selective Read operations allow the Master device to select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the N24Cxx BUS ACTIVITY: MASTER N O S T A R T S AT CO KP SLAVE ADDRESS P S A C K SLAVE SCL D ATA BYTE 8 9 8th Bit SDA DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: MASTER S T A R T S T A R T ADDRESS BYTE SLAVE ADDRESS S N O S AT CO KP SLAVE ADDRESS P S A C K SLAVE A C K A C K D ATA BYTE Figure 11. Selective Read Sequence N O BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K S AT CO KP A C K P SLAVE A C K D ATA BYTE n D ATA BYTE n+1 D ATA BYTE n+2 Figure 12. Sequential Read Sequence www.onsemi.com 8 D ATA BYTE n+x N24C02, N24C04, N24C08, N24C16 ORDERING INFORMATION N24C02 Ordering Information Specific Device Marking Package Type Temperature Range Shipping† N24C02UDTG AV U = US−8 D = Industrial (−40°C to +85°C) T = Tape & Reel, 3,000 Units / Reel N24C02UVTG AM U = US−8 V = Automotive Grade 1 (−40°C to +125°C) T = Tape & Reel, 3,000 Units / Reel Specific Device Marking Package Type Temperature Range Shipping† N24C04UDTG AN U = US−8 D = Industrial (−40°C to +85°C) T = Tape & Reel, 3,000 Units / Reel N24C04UVTG AW U = US−8 V = Automotive Grade 1 (−40°C to +125°C) T = Tape & Reel, 3,000 Units / Reel Specific Device Marking Package Type Temperature Range Shipping† N24C08UDTG AP U = US−8 D = Industrial (−40°C to +85°C) T = Tape & Reel, 3,000 Units / Reel N24C08UVTG AX U = US−8 V = Automotive Grade 1 (−40°C to +125°C) T = Tape & Reel, 3,000 Units / Reel Specific Device Marking Package Type Temperature Range Shipping† N24C16UDTG AQ U = US−8 D = Industrial (−40°C to +85°C) T = Tape & Reel, 3,000 Units / Reel N24C16UVTG AZ U = US−8 V = Automotive Grade 1 (−40°C to +125°C) T = Tape & Reel, 3,000 Units / Reel Device Order Number N24C04 Ordering Information Device Order Number N24C08 Ordering Information Device Order Number N24C16 Ordering Information Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS US8 CASE 493 ISSUE F DATE 01 SEP 2021 SCALE 4 :1 GENERIC MARKING DIAGRAM* 8 XX MG G 1 XX M G = Specific Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04475D US8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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