N24C64UVTG

EEPROM Serial 64-Kb I2C N24C64 Description The N24C64 is a EEPROM Serial 64−Kb I2C device, organized internally as 256 pages of 32 bytes each. This device supports the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 32 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight N24C64 devices on the same bus. www.onsemi.com US8 U SUFFIX CASE 493 Features • • • • • • • • • • • • • Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified Supports Standard, Fast and Fast−Plus I2C Protocol 1.7 V / 1.6 V to 5.5 V Supply Voltage Range 32−Byte Page Write Buffer Fast Write Time (4 ms max) Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Automotive Grade 1 Temperature Range US 8−lead and 4−ball WLCSP Packages These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS Compliant WLCSP4 A4 SUFFIX CASE 567NH PIN CONFIGURATIONS 1 A0 A1 A2 VSS 1 VCC VCC WP SCL SCL SDA A1 A2 VSS B1 B2 SDA WLCSP4 (Top View) US8 (U) (Top View) MARKING DIAGRAMS 8 8 AT ALYW A6 MG G 1 N24C64UVTG 1 N24C64UDTG T YW XX or T = Specific Device Code* M = Date Code A = Assembly Location L = Wafer Lot Traceability YW = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2016 April, 2020 − Rev. 4 1 Publication Order Number: N24C64/D N24C64 VCC VCC SCL A2, A1, A0 SDA N24C64 SCL SDA N24C64 WP VSS VSS US8 WLCSP4 PIN FUNCTION Pin Name Function A0, A1, A2 Device Address SDA Serial Data SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground Figure 1. Functional Symbols Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature –65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS Symbol NEND (Note 2) TDR (Note 2) Parameter Endurance Data Retention 2. TA = 25°C 3. A Write Cycle refers to writing a Byte or a Page. www.onsemi.com 2 Max Units 1,000,000 Write Cycles (Note 3) 100 Years N24C64 Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Read Current Read, fSCL = 1 MHz 1 mA ICCW Write Current Write, fSCL = 1 MHz 1 mA ISB Standby Current All I/O Pins at GND or VCC 2 mA IL I/O Pin Leakage Pin at GND or VCC 2 mA VIL Input Low Voltage SCL, SDA −0.5 VCC x 0.3 V VIH Input High Voltage SCL, SDA VCC x 0.7 VCC + 0.5 V VILA Input Low Voltage A2, A1, A0 and WP −0.5 VCC x 0.3 V VIHA Input High Voltage A2, A1, A0 and WP VCC x 0.8 VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Min Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V 8 pF CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF RPD (Note 5) WP, A0, A1 or A2 On−Chip Pull−Down Resistor VIN < VIHA IPD (Note 5) WP, A0, A1 or A2 On−Chip Pull−Down Current VIN > VIHA 50 kW 2 mA 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. For improved noise immunity (and to allow for floating input pins), the WP, A0, A1 & A2 inputs are pulled−down to GND by relatively strong on−chip resistors. When attempting to drive these inputs High, the external drivers must be able to supply sufficient current, until the input level at the pin exceeds VIHA. Once the input level at the pin exceeds VIHA, the resistive pull−down (RPD) converts to a constant current pull−down (IPD). www.onsemi.com 3 N24C64 Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V / 1.6 V* to 5.5 V, TA = −40°C to +85°C and VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C unless otherwise noted.) (Note 6) Standard Symbol FSCL tHD:STA Parameter Min Fast Max Clock Frequency Min 100 START Condition Hold Time Fast−Plus Max Min 400 Max Units 1,000 kHz 4 0.6 0.25 ms tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms tHIGH High Period of SCL Clock 4 0.6 0.40 ms 4.7 0.6 0.25 ms tSU:STA START Condition Setup Time tHD:DAT Data In Hold Time 0 0 0 ms tSU:DAT Data In Setup Time 250 100 50 ns tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns tF (Note 7) SDA and SCL Fall Time 300 300 100 ns tSU:STO STOP Condition Setup Time tBUF Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH (Note 7) Ti (Note 7) Data Out Hold Time 4 0.6 0.25 ms 4.7 1.3 0.5 ms 3.5 100 0.9 100 Noise Pulse Filtered at SCL and SDA Inputs 50 0.40 50 50 ms ns 50 ns tSU:WP WP Setup Time 0 0 0 ms tHD:WP WP Hold Time 2.5 2.5 1 ms tWR tPU (Notes 7, 8) Write Cycle Time Power-up to Ready Mode 4 4 4 ms 0.35 0.35 0.35 ms *VCC(min) = 1.6 V for Read operations, TA = −20°C to +85°C 6. Test conditions according to “A.C. Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. A.C. TEST CONDITIONS Input Levels 0.2 x VCC to 0.8 x VCC for VCC ≥ 2.2 V; 0.15 x VCC to 0.85 x VCC for VCC < 2.2 V Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 x VCC, 0.7 x VCC Output Reference Levels 0.3 x VCC, 0.7 x VCC Output Load Current Source: IOL = 6 mA (VCC ≥ 2.5 V); IOL = 2 mA (VCC < 2.5 V); CL = 100 pF www.onsemi.com 4 N24C64 I2C Bus Protocol Power-On Reset (POR) Each N24C64 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power. The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH. START/STOP Condition Pin Description SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these inputs are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH. Device Addressing The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the N24C64, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3). The device in WLCSP with 4 bumps responds only to address combination A2A1A0 = 000. Functional Description The N24C64 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The N24C64 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. Acknowledge During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5. SCL SDA START CONDITION STOP CONDITION Figure 2. Start/Stop Timing 1 0 1 0 A2 A1 A0 DEVICE ADDRESS Figure 3. Slave Address Bits www.onsemi.com 5 R/W N24C64 BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 5. Bus Timing WRITE OPERATIONS Byte Write Acknowledge Polling To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7). As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK. Hardware Write Protection With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected. Page Write The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR). Delivery State The N24C64 is shipped erased, i.e., all bytes are FFh. www.onsemi.com 6 N24C64 BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS ADDRESS BYTE DATA BYTE a7 − a0 d7 − d0 a15 − a8 S S T O P P * * * * A C K A C K SLAVE *a15 − a13 are don’t care bits. A C K A C K Figure 6. Byte Write Sequence SCL SDA 8th Bit Byte n ACK tWR STOP CONDITION START CONDITION ADDRESS Figure 7. Write Cycle Timing BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS DATA BYTE n ADDRESS BYTE DATA BYTE n+1 S T O P DATA BYTE n+P P S n = 1; P ≤ 31 A C K A C K A C K SLAVE A C K A C K Figure 8. Page Write Sequence ADDRESS BYTE DATA BYTE 1 8 a7 a0 9 1 8 d7 d0 SCL SDA tSU:WP WP tHD:WP Figure 9. WP Timing www.onsemi.com 7 A C K A C K N24C64 READ OPERATIONS Immediate Read Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11). To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode. Sequential Read Selective Read If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the Byte N O BUS ACTIVITY: S T A MASTER R T S A T CO K P SLAVE ADDRESS P S A C K SLAVE SCL 8 SDA DATA BYTE 9 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Read Sequence and Timing BUS ACTIVITY: S T A MASTER R T ADDRESS BYTE SLAVE ADDRESS S T A R T ADDRESS BYTE S N O A C K SLAVE ADDRESS P S A C K SLAVE A C K A C K A C K DATA BYTE Figure 11. Selective Read Sequence N O A C K BUS ACTIVITY: MASTER A C K SLAVE ADDRESS A C K A C K S T O P P SLAVE A C K DATA BYTE n DATA BYTE n+1 DATA BYTE n+2 Figure 12. Sequential Read Sequence www.onsemi.com 8 S T O P DATA BYTE n+x N24C64 ORDERING INFORMATION Specific Device Marking Package Type Temperature Range Shipping† N24C64UDTG AT U = US−8 D = Industrial (−40°C to +85°C) T = Tape & Reel, 3,000 Units / Reel N24C64UVTG A6 U = US−8 V = Automotive Grade 1 (−40°C to +125°C) T = Tape & Reel, 3,000 Units / Reel T A = WLCSP D = Industrial (−40°C to +85°C) T = Tape & Reel, 5,000 Units / Reel Device Order Number N24C64A4DXTG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 9. All packages are RoHS-compliant (Lead-free, Halogen-free). 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS US8 CASE 493 ISSUE F DATE 01 SEP 2021 SCALE 4 :1 GENERIC MARKING DIAGRAM* 8 XX MG G 1 XX M G = Specific Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04475D US8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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