N34TS108C6EXT5G

N34TS108 Low‐Voltage Digital Temperature Sensor Description N34TS108 is a digital-output temperature sensor with a dynamically-programmable limit window, and under- and over temperature alert functions. These features provide optimized temperature control without the need of frequent temperature readings by the controller or application processor. The N34TS108 features SMBus t and two-wire interface compatibility, and allows up to three devices on one bus with the SMBus alert function. The N34TS108 is ideal for thermal management optimization in a variety of consumer, computer, and environmental applications. The device is specified over a temperature range of –40°C to +125°C. www.onsemi.com WLCSP6 C6 SUFFIX CASE 567WQ FUNCTION DIAGRAM Features • Dynamically-Programmable Limit Window with Under- and Over Temperature Alerts V+ • Accuracy: ±0.75°C (max) from –20°C to +85°C ±1°C (max) from –40°C to +125°C Low Quiescent Current: ♦ 6 mA Active from –40°C to +125°C Supply Range: 1.4 V to 3.6 V Resolution: 12 Bits (0.0625°C) Package: 1.2-mm × 0.8-mm, 6-Ball WCSP ♦ • • • • A1 B1 ♦ A0 C1 Diode Temp Sensor Control Logic A2 DS ADC Serial Interface B2 OSC Config and Temp Register C2 ALERT GND SCL SDA Typical Applications • • • • Smartphone and Tablet Thermal Management Battery Management Thermostat Control Under- and Over Temperature Protection for Environmental Monitoring and HVAC Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage MARKING DIAGRAM T YW (WLCPA) T Y W = Specific Device Code = Year = Work Week Rating Unit 3.6 V ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Input Voltage −0.5 to 3.6 V Operating Temperature −55 to 150 °C Junction Temperature (TJ) 150 °C Storage Temperature (Tstg) −60 to 150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2014 February, 2020 − Rev. 1 1 Publication Order Number: N34TS108/D N34TS108 PIN CONFIGURATION WLCSP6 Pin 1 UDFN6 VCC A1 A2 GND A0 B1 B2 SCL ALERT C1 C2 Pin 1 SDA SCL GND VCC ALERT A0 SDA (Top View) (Top View) Table 2. ESD RATINGS ESD Rating V(ESD) Electrostatic Discharge Value Unit Human body model (HBM), per ANSI/ESDA/JEDEC JS−001, all pins11l ±2000 V Charged device model (COM), per JEDEC specification JESD22−C101, all pins ±1000 V Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V, TA = 25°C, unless otherwise specified) Parameter Conditions Min Typ Max Unit +125 °C ±0.75 °C TEMPERATURE INPUT –40 Range Accuracy (Temperature Error) –20°C to +85°C ±0.15 –40°C to +125°C Accuracy vs. Supply ±0.3 ±1 °C ±0.03 ±0.3 °C/V DIGITAL INPUT/OUTPUT VIH Input Logic High Level 0.7 (VCC) VCC V VIL Input Logic Low Level −0.5 0.3 (VCC) V IIN Input Current 0 V < VIN < (VCC) +0.3 V 1 mA VOL Output Logic Low Level VCC > 2 V, IOUT = 3 mA 0.4 V VCC < 2 V, IOUT = 3 mA 0.2 (VCC) V 120 kW ALERT Internal Pull-up Resistor ALERT to VCC 80 Resolution 100 12 Conversion Time One-Shot mode Conversion Modes CR1 = 0, CR0 = 0 17 22 Bit 28 ms 0.25 Conv/s CR1 = 0, CR0 = 1 (default) 1 Conv/s CR1 = 1, CR0 = 0 4 Conv/s CR1 = 1, CR0 = 1 16 Conv/s Timeout Time 21 30 35 ms 3.6 V POWER SUPPLY Operating Supply Range, VCC Pin 1.4 www.onsemi.com 2 N34TS108 Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.8 V, TA = 25°C, unless otherwise specified) Parameter Conditions Min Typ Max Unit Serial bus inactive, CR1 = 0, CR0 = 1 (default) 3.1 3.6 mA Serial bus inactive, CR1 = 0, CR0 = 1 (default), –40°C to +125°C 6 mA Serial bus active, SCL frequency = 400 kHz, CR1 = 0, CR0 = 1 (default) 8 mA Serial bus active, SCL frequency = 3.4 MHz, CR1 = 0, CR0 = 1 (default) 41 mA Serial bus inactive 2.5 POWER SUPPLY IQ ISD Quiescent Current Shutdown Current 3.1 mA Serial bus active, SCL frequency = 400 kHz 8 mA Serial bus active, SCL frequency = 3.4 MHz 41 mA TEMPERATURE Specified Range –40 +125 °C Storage Range –55 +150 °C www.onsemi.com 3 N34TS108 Table 4. A.C. OPERATING CHARACTERISTICS (VCC = 1.4 V to 3.6 V, TA = −40°C to +125°C) Fast Mode High Speed Mode Min Max Min Max Unit SCL Operating Frequency, VCC ≥ 1.8 V 0.001 0.4 0.001 3.4 MHz SCL Operating Frequency, VCC < 1.8 V 0.001 0.4 0.001 2.5 MHz Bus Free Time between Stop and Start Conditions, VCC 1300 160 ns Bus Free Time between Stop and Start Conditions, VCC 1300 260 ns t(HDSTA) Hold Time after Repeated Start Condition. After this period, the first clock is generated. 600 160 ns t(SUSTA) Repeated Start Condition Setup Time 600 160 ns t(SUSTO) Stop Condition Setup Time 600 160 ns t(HDDAT) Data Hold Time, VCC ≥ 1.8 V 0 900 0 70 ns Data Hold Time, VCC < 1.8 V 0 900 0 130 ns Data Setup Time, VCC ≥ 1.8 V 100 10 ns Data Setup Time, VCC < 1.8 V 100 50 ns Test Conditions Parameter f(SCL) t(BUF) t(SUDAT) t(LOW) t(HIGH) SCL Clock Low Period, VCC ≥ 1.8 V 1300 160 ns SCL Clock Low Period, VCC < 1.8 V 1300 260 ns SCL Clock High Period 600 60 ns tR, tF − SDA Data Rise/Fall Time 300 80 ns tR, tF − SCL Clock Rise/Fall Time 300 40 ns Clock/Data Rise Time for SCLK ≤ 100 kHz 1000 tR ns 1. For the N34TS108, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time-out count takes place when SCL is low in the time interval between START and STOP. 2. In a “Wired-OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be able to sink the (external) bus pull-up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus or a larger bus pull-up resistor. 3. The first valid temperature recording can be expected after tPU at nominal supply voltage. Table 5. PIN CAPACITANCE (VCC = 3.6 V, TA = 25°C, f = 400 kHz) Parameter Symbol CIN Test Conditions/Comments Min Max Unit SDA, Pin Capacitance VIN = 0 8 pF Input Capacitance (SCL) VIN = 0 6 pF Table 6. PIN DESCRIPTIONS Pin Name Ball Number Description A0 B1 Address selection pin ALERT C1 Alert output pin GND A2 Ground SCL B2 Input clock pin SDA C2 Input/output data pin VCC A1 Supply Voltage (1.4 V to 3.6 V) www.onsemi.com 4 N34TS108 SCL SDA START CONDITION STOP CONDITION Figure 1. START/STOP Timing BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER 1 BUS RELEASE DELAY (RECEIVER) 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 2. Acknowledge Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tSU:DAT tHD:STA tSU:STO SDA IN tDH tAA tBUF SDA OUT Figure 3. Bus Timing OVERVIEW The N34TS108 is a digital temperature sensor optimal for thermal management and thermal protection applications. The N34TS108 is two-wire and SMBus Interface compatible, and is specified over a temperature range of −40°C to +125°C. The N34TS108 temperature sensor is the chip itself; the solder bumps provide the primary thermal path as a result of the lower thermal resistance of metal. The temperature sensor result is equivalent to the local temperature of the printed circuit board (PCB) on which the sensor is mounted. The N34TS108 only requires pull-up resistors on SCL and SDA; although, a 0.01 mF bypass capacitor is recommended. There is an internal 100 kW pull-up resistor connected to supply on the ALERT pin. If required, use an external resistor of smaller value on the ALERT pin for a stronger pull-up to VCC. The SCL and SDA lines can be pulled up to a supply that is equal to or higher than VCC through the pull-up resistors. To configure one of three different addresses on the bus, connect AO to either VCC, GND, or SDA. If AO is connected to SDA, make its pull-up supply equal to VCC. www.onsemi.com 5 N34TS108 POINTER REGISTER Figure 4 shows the internal register structure of the N34TS108. Use the 8-bit pointer register to address a given data register. The pointer register uses the two LSBs (see Table 16) to identify which of the data registers respond to a read or write command. Table 7 identifies the bits of the pointer register byte. Table 8 describes the pointer address of the registers available in the N34TS108. The power-up reset value of the P1 and P0 bits is ‘00’. Pointer Register Temperature Register SCL Configuration Register I/O Control Interface TLOW Register SDA THIGH Register Figure 4. Internal Register Structure Table 7. POINTER REGISTER BYTE P7 P6 P5 P4 P3 P2 0 0 0 0 0 0 Table 8. POINTER ADDRESSES P1 P0 Register 0 0 Temperature Register (Read Only, Default) 0 1 Configuration Register (Read/write) 1 0 TLOW Register (Read/Write) 1 1 THIGH Register (Read/Write) www.onsemi.com 6 P1 P0 Register Bits N34TS108 TEMPERATURE REGISTER The temperature register is configured as a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, as shown in Table 9 and Table 10. Note that byte 1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature. There is no requirement to read the least significant byte if that information is not needed (for example, for resolution lower than 1°C). Table 5 summarizes the temperature data format. One LSB equals 0.0625°C. Negative numbers are represented in binary twos complement format. Following power-up or reset, the temperature register reads 0°C until the first conversion is complete. The unused bits in the temperature register always read ‘0’. Table 9. BYTE 1 OF TEMPERATURE REGISTER D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table 10. BYTE 2 OF TEMPERATURE REGISTER D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 Table 11. TEMPERATURE DATA FORMAT (Note 4) Digital Output Temperature (5C) Binary Hex 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 –0.25 1111 1111 1100 FFC –25 1110 0111 0000 E70 –55 1100 1001 0000 C90 4. The temperature sensor ADC resolution is 0.0625°C/count. • To convert negative temperatures to a digital data Table 11 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format for a given temperature. • To convert positive temperatures to a digital data format: Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified format, and MSB = 0 to denote a positive sign. Example: (+50°C)/(0.0625°C/count) = 800 = 320h = 0011 0010 0000 format: Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a 12-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary number and adding one. Denote a negative number with MSB = 1. Example: (|–25°C|)/(0.0625°C/count) = 400 = 190h = 0001 1001 0000 Twos complement format: 1110 0110 1111 + 1 = 1110 0111 0000 www.onsemi.com 7 N34TS108 CONFIGURATION REGISTER The configuration register is a 16-bit read and write register used to store bits that control the operational modes of the temperature sensor. Read and write operations are performed MSB first. The format and power-up (reset) default value of the configuration register is shown in Table 12, followed by an explanation of the register bits. Other options for the default values are available by request. Table 12. CONFIGURATION AND POWER-UP/RESET FORMAT Byte D7 D6 D5 D4 D3 D2 D1 D0 1 ID CR1 CR0 FH FL TM M1 M0 0 0 1 0 0 1 1 0 POL 0 HYS1 HYS0 0 0 0 0 0 0 0 1 0 0 0 0 2 Hysteresis Control (HYS1 and HYS0) the limit comparison of the N34TS108 to 0°C, 1°C, 2°C, or 4°C. The default hysteresis is 1°C. Table 13 shows the settings for HYS1 and HYS0. When operating in comparator mode, the hysteresis control bits (HYS1 and HYS0) configure the hysteresis for Table 13. HYSTERESIS SETTINGS HYS1 HYS2 0 0 0°C 0 1 1°C (Default) 1 0 2°C 1 1 4°C Polarity (POL) Hysteresis useful for reducing the power consumption of the N34TS108 when continuous temperature monitoring is not required. As a result of the short conversion time, the N34TS108 can achieve a higher conversion rate. A single conversion typically takes 22 ms and a read can take place in less than 20 ms. However, when using one-shot mode, 30 or more conversions per second are possible. The polarity of the ALERT pin can be programmed using the POL bit. If POL = ‘0’ (default), the ALERT is active low. For POL = ‘1’, the ALERT pin is active high, and the state of the ALERT pin is inverted. Mode Bits (M1 and M0) The mode bits, M1 and M0, can be set to three different modes: shutdown, one-shot, or continuous conversion. Continuous Conversion Mode (M1 = ‘1’) When the N34TS108 is in continuous conversion mode (M1 = ‘1’), a single conversion is performed at a rate determined by the conversion rate bits (CR1 and CR0 in the configuration register). The N34TS108 performs a single conversion, and then goes in standby and waits for the appropriate delay set by the CR1 and CR0 bits. See Table 14 for CR1 and CR0 settings. Shutdown Mode (M1 = ‘0’, M0 = ‘0’) Shutdown mode saves power by shutting down all device circuitry other than the serial interface, thus reducing current consumption to typically less than 2.5 mA. Shutdown mode is enabled when M1 and M0 = ‘00’. The device shuts down when current conversion is completed. One-Shot Mode (M1 = ‘0’, M0 = ‘1’) The N34TS108 features a one-shot temperature measurement mode. When the device is in shutdown mode, writing a ‘01’ to the M1 and M0 bits starts a single temperature conversion. During the conversion, the M1 and M0 bits reads ‘01’. The device returns to the shutdown state at the completion of the single conversion. After the conversion, the M1 and M0 bits read ‘00’. This feature is Thermostat Mode (TM) The thermostat mode bit indicates to the device whether to operate in comparator mode (TM = ‘0’) or interrupt mode (TM = ‘1’, default). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section. www.onsemi.com 8 N34TS108 SMBus ALERT Response only clears the pin and not the flags. Reading the configuration register clears both the flags and the pin unless the device is in comparator mode. Temperature Watchdog Flags (FL and FH) The N34TS108 uses temperature watchdog flags in the configuration register that indicate the result of comparing the device temperature at the end of every conversion to the values stored in the temperature limit registers (THIGH and TLOW). If the temperature of the N34TS108 exceeds the value in the THIGH register, then the flag-high bit (FH) in the configuration register is set to ‘1’. If the temperature falls below the value in the TLOW register, then the flag-low bit (FL) is set to ‘1’. If both flag bits remain ‘0’, then the temperature is within the temperature range set by the temperature limit registers. In interrupt mode, when any of the flags is set by an under- or over-temperature event, the Conversion Rate The conversion rate bits, CR1 and CR0, configure the N34TS108 for conversion rates of 0.25 Hz, 1 Hz, 4 Hz, or 16 Hz. The default rate is 1 Hz. The N34TS108 has a typical conversion time of 22 ms. To achieve different conversion rates, the N34TS108 makes a conversion, and then powers down and waits for the appropriate delay set by CR1 and CR0. Table 14 shows the settings for CR1 and CR0. Table 14. CONVERSION RATE SETTINGS CR1 CR0 Conversion Rate IQ (Typ) 0 0 0.25 Hz 3 mA 0 1 1 Hz (Default) 4 mA 1 0 4 Hz 5 mA 1 1 16 Hz 13 mA quiescent current during conversion is 27 mA (typical at +25°C). The quiescent current during delay is 2.5 mA (typical at +25°C). After power-up or a general-call reset, the N34TS108 immediately starts a conversion, as shown in Figure 5. The first result is available after 22 ms (typical). The active Delay* Delay* 22 ms Startup 22 ms Start of Conversion 22 ms Start of Conversion *Delay is set by the CR1 and CR0 bits in the configuration register. Figure 5. Conversion Start HIGH- AND LOW-LIMIT REGISTERS In comparator mode (TM = ‘0’), the ALERT pin becomes active when the temperature exceeds the value in the THIGH register or drops below the value in the TLOW register. The ALERT pin remains active until the temperature returns to a value that is within the range set by: (T LOW ) HYS) and (T HIGH * HYS) In interrupt mode (TM = ‘1’), the ALERT pin becomes active when the temperature exceeds the value in the THIGH register or drops below the value in the TLOW register, and remains active until a read operation of the configuration register occurs (also clears the values latched in the watchdog flags, FL and FH), or the device successfully responds to the SMBus alert response address. The ALERT pin is also cleared by resetting the device with the general call reset command. (eq. 1) Where: HYS is the hysteresis set by the hysteresis control bits (HYS1 and HYS0). www.onsemi.com 9 N34TS108 Both operational modes are represented in Figure 6 and Figure 7. Table 15 and Table 16 describe the format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up (reset) default values are THIGH = +127.9375°C and TLOW = –128°C. These values ensure that upon power-up, the limit window is set to maximum, and the ALERT pin does not become active until the desired limit values are programmed in the registers. Other default values for the temperature limits are available by request. The format of the data for THIGH and TLOW is the same as for the temperature register. Table 15. BYTES 1 AND 2 OF THIGH REGISTER Byte D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 H3 H2 H1 H0 0 0 0 0 Table 16. BYTES 1 AND 2 OF TLOW REGISTER Byte D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 Byte D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 NOTE: Update THIGH and TLOW limit. Read the configuration register to clear the flags and the ALERT pin. Figure 6. Interrupt Mode www.onsemi.com 10 N34TS108 Figure 7. Comparator Mode SERIAL BUS ADDRESS To communicate with the N34TS108, the master must first communicate with slave devices using a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing either a read or write operation. The N34TS108 features an address pin that allows up to three devices to be addressed on a single bus. The N34TS108 latches the status of the address pin at the start of a communication. Table 17 describes the pin logic levels and the corresponding address values. Other values for the fixed address bits are available by request. SERIAL INTERFACE The N34TS108 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The N34TS108 supports the transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All data bytes are transmitted MSB first. Table 17. ADDRESS PIN AND SLAVE ADDRESSES Device Two-wire Address A0 Pin Connection 1001000 GND 1001001 VCC 1001010 SDA 1001011 SCL BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte; the last bit indicates whether a read or write operation follows. During the ninth clock pulse, the slave being addressed responds to the master by generating an acknowledge bit and pulling SDA low. Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted as a start or stop signal. After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to high, while SCL is high. WRITING/READING OPERATION Accessing a particular register on the N34TS108 is accomplished by writing the appropriate value to the pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the N34TS108 requires a value for the pointer register. When reading from the N34TS108, the last value stored in the pointer register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value www.onsemi.com 11 N34TS108 must be written to the pointer register. This action is accomplished by issuing a slave address byte with the R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate a start condition and send the slave address byte with the R/W bit high to initiate the read command. If repeated reads from the same register are desired, it is not necessary to continually send the pointer register bytes because the N34TS108 stores the pointer register value until it is changed by the next write operation. Note that register bytes are sent with the most significant byte first, followed by the least significant byte. acknowledges the SMBus alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates whether the alert condition is caused by the temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than THIGH, or low if the temperature is less than TLOW. If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion of the SMBus alert command determines which device clears its alert status first. If the N34TS108 wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the N34TS108 loses the arbitration, its ALERT pin remains active. SLAVE MODE OPERATIONS The N34TS108 can operate as a slave receiver or slave transmitter. GENERAL CALL The N34TS108 responds to a two-wire general call address (0000000) if the eighth bit is ‘0’. The device acknowledges the general call address and responds to commands in the second byte. If the second byte is 00000100, the N34TS108 latches the status of the address pin, but does not reset. If the second byte is 00000110, the N34TS108 internal registers are reset to power-up values. The N34TS108 does not support the general address acquire command. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit low. The N34TS108 then acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The N34TS108 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The N34TS108 acknowledges reception of each data byte. The master can terminate data transfer by generating a start or stop condition. HIGH-SPEED (Hs) MODE In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed operation. The N34TS108 does not acknowledge this byte, but does switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition, the N34TS108 switches the input and output filters back to fast-mode operation. Slave Transmitter Mode: The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by generating a start or stop condition. TIMEOUT FUNCTION The N34TS108 resets the serial interface if SCL or SDA are held low for 30 ms (typ) between a start and stop condition. If the N34TS108 is pulled low, it releases the bus and then waits for a start condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL operating frequency. SMBus ALERT FUNCTION The N34TS108 supports the SMBus alert function. When the N34TS108 operates in interrupt mode (TM = ‘1’), the ALERT pin may be connected as an SMBus alert signal. When a master senses that an alert condition is present on the ALERT line, the master sends an SMBus alert command (00011001) to the bus. If the ALERT pin is active, the device Table 18. ORDERING INFORMATION Device Order Number Marking Package Type Temperature Range Shipping† N34TS108C6ECT5G C WLCSP 6-ball −40°C to +125°C 5,000 / Tape & Reel N34TS108MUET3G A UDFN 6 *40°C to +125°C 3,000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 5. All packages are RoHS-compliant (Lead-free, Halogen-free). 6. The standard lead/ball finish is SnAgCu. www.onsemi.com 12 N34TS108 SMBus is a trademark of Intel Corporation www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 2x2, 0.65P CASE 517DR ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13696G UDFN6 2x2, 0.65P DATE 31 OCT 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP6, 1.1888x0.788x0.625 CASE 567YQ ISSUE O DATE 12 NOV 2019 GENERIC MARKING DIAGRAM* X YW X Y W = Specific Device Code = Year = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON14165H Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. WLCSP6, 1.1888x0.788x0.625 PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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