N64S830HAT22IT

N64S830HA 64Kb Low Power Serial SRAMs 8K × 8 bit Organization Overview The ON Semiconductor serial SRAM family includes several integrated memory devices including this 64K serially accessed Static Random Access Memory, internally organized as 8K words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high-speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) serial bus. A single data in and data out line is used along with a clock to access data within the devices. The N64S830HA devices include a HOLD pin that allows communication to the device to be paused. While paused, input transitions will be ignored. The devices can operate over a wide temperature range of -40oC to +85oC and can be available in several standard package offerings. Features • Power Supply Range 2.5 to 3.6V • Very low standby current As low as 1uA • Very low operating current As low as 3mA • Simple memory control Single chip select (CS) Serial input (SI) and serial output (SO) • Flexible operating modes Word read and write Page mode (32 word page) Burst mode (full array) • Organization 8K x 8 bit • Self timed write cycles • Built-in write protection (CS high) • HOLD pin for pausing communication • High reliability Unlimited write cycles • RoHS Compliant Packages Green SOIC and TSSOP Device Options Part Number N64S830HAS2 N64S830HAT2 Density Power Supply (V) 3.0 Speed (MHz) 20 Package SOIC TSSOP Typical Standby Current 1uA Read/Write Operating Current 3 mA @ 1Mhz 64Kb ©2009 SCILLC. All rights reserved. June 2009 - Rev. K Publication Order Number: N64S830HA/D N64S830HA Package Configurations Pin Names Pin Name CS SCK SI SO HOLD NC VCC VSS Pin Function Chip Select Input Serial Clock Input Serial Data Input Serial Data Output Hold Input No Connect Power Ground CS SO NC VSS 1 8 VCC HOLD SCK SI SOIC 2 3 4 7 6 5 CS SO NC VSS 1 8 VSS HOLD SCK SI TSSOP 2 3 4 7 6 5 Functional Block Diagram SCK HOLD Clock Circuitry CS Decode Logic 64Kb SRAM Array SDI Data In Receiver SDO Data Out Buffer Rev. K | Page 2 of 15 | www.onsemi.com N64S830HA Absolute Maximum Ratings1 Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,OUT VCC PD TSTG TA TSOLDER Rating –0.3 to VCC+0.3 –0.3 to 4.5 500 –40 to 125 -40 to +85 260oC, 10sec Unit V V mW o o o C C C 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Current Standby Current Symbol VCC VIH VIL VOH VOL ILI ILO ICC1 ICC2 ICC3 ISB IOH = -0.4mA IOL = 1mA CS = VCC, VIN = 0 to VCC CS = VCC, VOUT = 0 to VCC F = 1MHz, IOUT = 0 F = 10MHz, IOUT = 0 F = fCLK MAX, IOUT = 0 CS = VCC, VIN = VSS or VCC 1 Test Conditions 3V Device Min. 2.5 0.7 x VCC –0.3 VCC–0.5 0.2 0.5 0.5 3 6 10 4 Typ1 Max 3.6 VCC+0.3 0.8 Unit V V V V V µA µA mA mA mA µA 1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested. Capacitance1 Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 7 7 Unit pF pF 1. These parameters are verified in device characterization and are not 100% tested Rev. K | Page 3 of 15 | www.onsemi.com N64S830HA Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 100pF -40 to +85 oC Timing Item Clock Frequency Clock Rise Time Clock Fall Time Clock High Time Clock Low Time Clock Delay Time CS Setup Time CS Hold Time CS Disable Time SCK to CS Data Setup Time Data Hold Time Output Valid From Clock Low Output Hold Time Output Disable Time HOLD Setup Time HOLD Hold Time HOLD Low to Output High-Z HOLD High to Output Valid Symbol fCLK tR tF tHI tLO tCLD tCSS tCSH tCSD tSCS tSU tHD tV tHO tDIS tHS tHH tHZ tHV 10 10 10 50 0 20 25 25 25 25 50 25 5 10 10 25 Min. Max. 20 2 2 Units MHz us us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. K | Page 4 of 15 | www.onsemi.com N64S830HA Serial Input Timing tCSD CS tR SCK tSU SI MSB in tCSS tHD LSB in tF tCSH tSCS tCLD SO High-Z Serial Output Timing CS tLO SCK tV SO tDIS MSB out Don’t Care LSB out tHI tCSH SI Hold Timing CS tHS SCK tHH SO n+2 n+1 tHZ SI n+2 n+1 n Don’t Care n n High-Z tHS tHH tHV n tSU n-1 n-1 HOLD Rev. K | Page 5 of 15 | www.onsemi.com N64S830HA Control Signal Descriptions Signal CS Name Chip Select I/O I Description A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence being started. Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge of SCK. Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out after the falling edge of SCK. A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the Hold function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High-Z. SCK SI SO Serial Clock Serial Data In Serial Data Out I I O HOLD Hold I Functional Operation Basic Operation The 64Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro-controllers. It may also interface with other non-SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. Instruction Set Instruction READ WRITE RDSR WRSR Instruction Format 0000 0011 0000 0010 0000 0101 0000 0001 Description Read data from memory starting at selected address Write data to memory starting at selected address Read status register Write status register Rev. K | Page 6 of 15 | www.onsemi.com N64S830HA READ Operations The serial SRAM READ is selected by enabling CS low. First, the 8-bit READ instruction is transmitted to the device followed by the 16-bit address with the 3 MSBs being don’t care. After the READ instruction and addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely. All READ operations are terminated by pulling CS high. Word READ Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Instruction SI 0 0 0 0 0 0 1 1 15 14 16-bit address 13 12 2 1 0 Data Out SO High-Z 7 6 5 4 3 2 1 0 Rev. K | Page 7 of 15 | www.onsemi.com N64S830HA Page and Burst READ Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Instruction SI 0 0 0 0 0 0 1 1 15 14 16-bit address 13 12 2 1 0 Don’t Care ADDR 1 Data Out from ADDR 1 SO High-Z 7 6 5 4 3 2 1 0 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Don’t Care Data Out from ADDR 2 7 6 5 4 3 2 1 0 7 Data Out from ADDR 3 6 5 4 3 2 1 0 ... 7 Data Out from ADDR n 6 5 4 3 2 1 0 Page READ Sequence SI 16-bit address Page address (X) Word address (Y) SO Page X Word Y Page X Page X Page X Word 31 Page X Word 0 Page X Word 1 Data Words: sequential, at the end of the page the address wraps back to the beginning of the page Word Y+1 Word Y+2 Burst READ Sequence SI 16-bit address Page address (X) Word address (Y) SO Page X Word Y Page X Word Y+1 Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. ... Page X Word 31 Page X Word 0 Page X Word 1 ... Page X Page X+1 Page X+1 Word Y+1 Word Y-1 Word Y Rev. K | Page 8 of 15 | www.onsemi.com N64S830HA WRITE Operations The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted to the device followed by the 16-bit address with the 3 MSBs being don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (1FFFh), the address counter wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. Word WRITE Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Instruction SI 0 0 0 0 0 0 1 0 15 14 16-bit address 13 12 ... 2 1 0 7 6 Data In 5 4 3 2 1 0 SO High-Z Rev. K | Page 9 of 15 | www.onsemi.com N64S830HA Page and Burst WRITE Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 Instruction SI 0 0 0 0 0 0 1 0 15 14 16-bit address 13 12 2 1 0 7 6 5 4 3 2 1 0 ADDR 1 SO High-Z Data In to ADDR 1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Data In to ADDR n Data In to ADDR 2 7 6 5 4 3 2 1 0 7 Data In to ADDR 3 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0 High-Z Page WRITE Sequence Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SI 16-bit address Page address (X) Word address (Y) SO Page X Word Y Page X Page X Page X Word 31 Page X Word 0 Page X Word 1 Word Y+1 Word Y+2 High-Z Burst WRITE Sequence SI 16-bit address Page address (X) Word address (Y) Page X Word Y Page X Word Y+1 ... Page X Word 31 Page X Word 0 Page X Word 1 ... Page X Page X+1 Page X+1 Word Y+1 Word Y-1 Word Y Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. SO High-Z Rev. K | Page 10 of 15 | www.onsemi.com N64S830HA WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. Several of the register bits must be set to a low ‘0’. The timing sequence to write to the status register is shown below, followed by the organization of the status register. WRITE Status Register Sequence CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 0 0 1 7 6 Status Register Data In 5 4 3 2 1 0 SO High-Z Status Register - Data to Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode 0 0 = Word Mode (Default) 1 0 = Page Mode 0 1 = Burst Mode 1 1 = Reserved Reserved Must = 0 Hold Function 0 = Hold (Default) 1 = No Hold Rev. K | Page 11 of 15 | www.onsemi.com N64S830HA READ Status Register Instruction (RDSR) This instruction provides the ability to read the programmable bits of the Status Register. These register bits may be read at any time by performing the following timing sequence. Bits 0, 6 and 7 contain the data for the functional operation and Bit 1 will read data type ‘1’ for the 64Kb device. READ Status Register Instruction (RDSR) CS SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 1 0 1 Status Register Data Out SO High-Z 7 6 5 4 3 2 1 0 Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode 0 0 = Word Mode 1 0 = Page Mode 0 1 = Burst Mode 1 1 = Reserved 0 0 0 0 1 = 64Kb Hold Function 0 = Hold 1 = No Hold Power-Up State The serial SRAM enters a know state at power-up time. The device is in low-power standby state with CS = 1. A low level on CS is required to enter a active state. Rev. K | Page 12 of 15 | www.onsemi.com N64S830HA 8-Lead Plastic Small Outline, 150mil SOIC E E1 p D α B A2 h 45o A1 A φ L β c Parameter Pin Pitch Overall height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom Sym p A A2 A1 E E1 D h L Min 1.35 1.32 0.10 5.79 3.71 4.80 0.25 0.48 0 0.20 0.33 0 0 Nom 1.27 1.55 1.42 0.18 6.02 3.91 4.90 0.38 0.62 4 0.23 0.42 12 12 Max 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 φ c B α β Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Rev. K | Page 13 of 15 | www.onsemi.com N64S830HA 8-Lead Plastic Thin Shrink Small Outline, 4.4 mm TSSOP E E1 p D B α A2 A1 A φ L β c Parameter Pin Pitch Overall height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom Sym p A A2 A1 E E1 D L Min Nom 0.65 Max 1.10 0.85 0.05 6.25 4.30 2.90 0.50 0 0.09 0.19 0 0 0.90 0.10 6.38 4.40 3.00 0.60 4 0.15 0.25 5 5 0.95 0.15 6.50 4.50 3.10 0.70 8 0.20 0.30 10 10 φ c B α β Note: 1. All dimensions in Millimeters 2. Package dimensions exclude mold flash and protusions. Rev. K | Page 14 of 15 | www.onsemi.com N64S830HA Ordering Information Part Number N64S830HAS22I N64S830HAT22I N64S830HAS22IT N64S830HAT22IT Package 8-Pin SOIC (RoHS Compliant) 8-Pin TSSOP (RoHS Compliant) 8-Pin SOIC (RoHS Compliant) 8-Pin TSSOP (RoHS Compliant) Shipping Method Tray Tray Tape & Reel Tape & Reel Revision History Revision # A B C D E F G H I J K Date October 2005 January 2006 January 2006 January 2006 September 2006 May 2007 October 2007 January 2008 July 2008 September 2008 June 2009 Initial advance release Separated density, removed write protection and added page and burst modes Changed packages to green type Changed TSSOP pinout to match SOIC Split x8 and x16 devices Converted to AMI Semiconductor Updated DC parameters Maximum frequency changed to 16MHz for 1.8V device Removed ADVANCE from datasheet Changed AMIS address Change to Status Register Bit #1 - must be set to ‘1’ Converted to ON Semiconductor and new part numbers Change to WRITE Status Register Bit #1 - must be set to ‘0’ Change to READ Status Register Updated Operating Characteristics - minimum operating voltge = 2.5V Change Description ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor PO Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East & Africa Technical Support: Phone 421-33-790-2910 Japan Customer Focus Center: Phone 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Rev. K | Page 15 of 15 | www.onsemi.com