3.3 V Dual Differential
LVPECL/LVDS to LVTTL
Translator
NB100ELT23L
Description
The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL
translator. Because LVPECL (Positive ECL) or LVDS levels are used,
only +3.3 V and ground are required. The small outline 8-lead package
and the dual gate design of the ELT23L makes it ideal for applications
which require the translation of a clock and a data signal.
The ELT23L is available in only the ECL 100K standard. Since
there are no LVPECL outputs or an external VBB reference, the
ELT23L does not require both ECL standard versions. The LVPECL
inputs are differential. Therefore, the NB100ELT23L can accept any
standard differential LVPECL/LVDS input referenced from a VCC of
+3.3 V.
Features
•
•
•
•
•
www.onsemi.com
MARKING
DIAGRAMS*
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
8
TSSOP−8
DT SUFFIX
CASE 948R
8
2.1 ns Typical Propagation Delay
Maximum Operating Frequency > 160 MHz
KT23L
ALYW
G
1
1
K23L
ALYWG
G
24 mA LVTTL Outputs
Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
NB100ELT23LDR2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
NB100ELT23LDTG
TSSOP−8
(Pb−Free)
100 Units /
Tube
NB100ELT23LDTR2G TSSOP−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
April, 2021 − Rev. 13
1
Publication Order Number:
NB100ELT23L/D
NB100ELT23L
Table 1. PIN DESCRIPTION
D0
D0
1
8
2
7
LVPECL
VCC
PIN
Q0
LVTTL
D1
3
6
Q1
D1
4
5
GND
FUNCTION
Q0, Q1
LVTTL Outputs
D0*, D1*
D0**, D1**
Differential LVPECL Inputs
VCC
Positive Supply
GND
Ground
*Pins will default to VCC/2 when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation.
**Pins will default to 2/3 VCC when left open. If connected to a
common termination voltage under no signal conditions, then the
device will be susceptible to self−oscillation. See AND8020,
Section 6 for options.
Figure 1. 8−Lead Pinout (Top View) and
Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
D
D
50 kW
75 kW
Internal Input Pullup Resistor
50 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb−Free Pkg
SOIC−8
TSSOP−8
Level 1
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 1.25 in
Transistor Count
91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
www.onsemi.com
2
NB100ELT23L
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
3.8
V
3.8
V
50
100
mA
mA
−40 to +85
°C
VCC
Power Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SO−8
SO−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SO−8
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
Tsol
Wave Solder
