NB100ELT23LDTR2

NB100ELT23L 3.3V Dual Differential LVPECL/LVDS to LVTTL Translator The NB100ELT23L is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used, only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the ELT23L makes it ideal for applications which require the translation of a clock and a data signal. The ELT23L is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the ELT23L does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the NB100ELT23L can accept any standard differential LVPECL/LVDS input referenced from a VCC of +3.3 V. Features http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 KT23L ALYW G • • • • • 8 8 1 TSSOP−8 DT SUFFIX CASE 948R 1 K23L ALYWG G 2.1 ns Typical Propagation Delay Maximum Operating Frequency > 160 MHz 24 mA LVTTL Outputs Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V Pb−Free Packages are Available DFN8 MN SUFFIX CASE 506AA 1 A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2007 1 March, 2007 − Rev. 8 Publication Order Number: NB100ELT23L/D 6F M G G 4 NB100ELT23L Table 1. PIN DESCRIPTION D0 1 8 VCC PIN Q0, Q1 D0 2 LVPECL D1 3 LVTTL 6 Q1 7 Q0 D0*, D1* D0**, D1** VCC GND EP LVTTL Outputs Differential LVPECL Inputs Positive Supply Ground Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. FUNCTION D1 4 5 GND *Pins will default to VCC/2 when left open. If connected to a common termination voltage under no signal conditions, then the device will be susceptible to self−oscillation. **Pins will default to 2/3 VCC when left open. If connected to a common termination voltage under no signal conditions, then the device will be susceptible to self−oscillation. See AND8020, Section 6 for options. Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model D D Value 50 kW 75 kW 50 kW > 1.5 kV > 100 V > 2 kV Level 1 UL 94 V−0 @ 1.25 in 91 Devices Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 http://onsemi.com 2 NB100ELT23L Table 3. MAXIMUM RATINGS Symbol VCC VI Iout TA Tstg qJA qJC qJA qJC qJA Tsol Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Thermal Resistance (Junction−to−Ambient) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm