2.5 V/3.3 V Quad Differential
Driver/Receiver
NB100LVEP17
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
These Devices are Pb−Free, Halogen Free and RoHS Compliant
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24
1
24 PIN QFN
MN SUFFIX
CASE 485L
TSSOP−20
DT SUFFIX
CASE 948E
MARKING DIAGRAMS*
24
1
N100
VP17
ALYWG
G
A
L
Y
W
G
N100
VP17
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
NB100LVEP17DTR2G TSSOP−20
(Pb−Free)
Shipping†
2500 /
Tape & Reel
NB100LVEP17MNG
QFN−24 92 Units / Tube
(Pb−Free)
NB100LVEP17MNR2G
QFN−24
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
May, 2021 − Rev. 9
1
Publication Order Number:
NB100LVEP17/D
NB100LVEP17
D0
R1
Q0
R2
D0
R1
D1
R1
Q0
Q1
R2
D1
R1
D2
R1
Q1
Q2
R2
D2
R1
Q2
D3
R1
Q3
VCC
VEE
R2
D3
R1
Q3
VBB
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Pin
TSSOP
QFN
Name
I/O
Default
State
1,20
13,18,21,
22,23
VCC
−
−
Positive Supply Voltage. All VCC Pins Must be Externally Connected
to Power Supply to Guarantee Proper Operation.
11
10
VEE
−
−
Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation.
10
9
VBB
−
−
ECL Reference Voltage Output.
2,4,6,8
1,3,5,7
D[0:3]
ECL Input
Low
Noninverted Differential Inputs [0:3]. Internal 75 k to VEE.
3,5,7,9
2,4,6,8
D[0:3]
ECL Input
High
Inverted Differential Inputs [0:3]. Internal 75 k to VEE and 37 k to
VCC.
19,17,15,13
12,15,17,2
0
Q[0:3]
ECL Output
−
Noninverted Differential Outputs [0:3]. Typically Terminated with
50 to VTT = VCC − 2 V.
18,16,14,12
11,14,16,1
9
Q[0:3]
ECL Output
−
Inverted Differential Outputs [0:3]. Typically Terminated with 50 to
VTT = VCC − 2 V.
N/A
24
NC
−
−
No Connect. The NC Pin is Electrically Connected to the Die and
“MUST BE” Left Open.
N/A
−
EP
−
Description
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad
on the package bottom (see case drawing) must be attached to a heat−sinking conduit.
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2
NB100LVEP17
NC VCC VCC VCC Q0
24
VCC Q0
Q0
Q1 Q1
Q2
Q2
Q3
Q3 VEE
20
18
17
15
14
13
12
19
16
11
NB100LVEP17
1
2
3
4
5
6
7
8
9
VCC
D0
D0
D1
D1
D2
D2
D3
D3 VBB
10
23
22
21
20
Q0
Exposed Pad
(EP)
19
D0
1
18
VCC
D0
2
17
Q1
D1
3
16
Q1
D1
4
15
Q2
D2
5
14
Q2
D2
6
13
VCC
NB100LVEP17
7
8
D3
D3
9
10
VBB VEE
11
12
Q3
Q3
Figure 3. QFN−24 Lead Pinout (Top View)
Figure 2. TSSOP−20 Lead Pinout (Top View)
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (R1)
75 k
Internal Input Pullup Resistor (R2)
37 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb−Free Pkg
TSSOP−20
QFN−24
Level 1
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
274 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
NB100LVEP17
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
6
V
VEE
Negative Mode Power Supply
VCC = 0 V
−6
V
VI
Positive Mode Input Voltage
Negative Mode Input Voltage
VEE = 0 V
VCC = 0 V
6
−6
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
$0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−3 (1S − Single Layer Test Board)
0 lfpm
500 lfpm
20 TSSOP
20 TSSOP
140
50
°C/W
°C/W
JA
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−6 (2S2P Multilayer Test Board) with Filled Thermal
Vias
0 lfpm
500 lfpm
24 QFN
24 QFN
37
32
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
Standard Board
20 TSSOP
24 QFN
23 to 41
11
°C/W
°C/W
Tsol
Wave Solder (Pb−Free)
265
°C
VI v VCC
VI w VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V; VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
55
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 3)
505
775
900
505
775
900
505
775
900
mV
VIH
Input HIGH Voltage (Single−Ended) (Note 4)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single−Ended) (Note 4)
505
875
505
875
505
875
mV
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
1.2
2.5
1.2
2.5
1.2
2.5
V
150
A
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
150
D
D
0.5
−150
150
0.5
−150
0.5
−150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.125 V to +1.3 V.
3. All loading with 50 to VEE = VCC − 2.0 V.
4. Do not use VBB at VCC < 3.0 V.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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4
NB100LVEP17
Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V; VEE = 0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
30
40
50
30
40
50
30
40
55
mA
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 7)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 7)
1305
1575
1700
1305
1575
1700
1305
1575
1700
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1305
1675
1305
1675
1305
1675
mV
VBB
ECL Output Reference Voltage (Note 8)
1775
1975
1775
1975
1775
1975
mV
3.3
1.2
3.3
1.2
3.3
V
150
A
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
1875
1.2
1875
150
D
D
0.5
−150
1875
150
0.5
−150
0.5
−150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.5 V to −0.3 V.
7. All loading with 50 to VCC − 2.0 V.
8. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
30
40
50
30
40
50
30
40
55
mA
VOH
Output HIGH Voltage (Note 11)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 11)
−1995
−1725
−1600
−1995
−1725
−1600
−1995
−1725
−1600
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1995
−1600
−1995
−1600
−1995
−1600
mV
VBB
ECL Output Reference Voltage
(Note 12)
−1525
−1325
−1525
−1325
−1525
−1325
mV
0.0
V
150
A
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IIH
Input HIGH Current (@ VIH)
IIL
Input LOW Current (@ VIL)
−1425
VEE + 1.2
0.0
VEE + 1.2
150
D
D
0.5
−150
−1425
0.0
VEE + 1.2
150
0.5
−150
−1425
0.5
−150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
10. Input and output parameters vary 1:1 with VCC.
11. All loading with 50 to VCC − 2.0 V.
12. Single ended input operation is limited VEE ≤ −3.0V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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5
NB100LVEP17
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 V to −3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14)
−40°C
Symbol
VOUTPP
Typ
fin < 1 GHz
fin = 2 GHz
fin = 2.5 GHz
600
400
300
700
500
400
D to Q, Q
200
250
325
5
5
25
Characteristic
Output Voltage Amplitude
(See Figures 4, 5)
tPLH,
tPHL
Propagation Delay to Output Differential
tSkew
Pulse Skew (Note 15)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 17)
tJITTER
RMS Random Clock Jitter (Note 18)
Peak−to Peak Data Dependent Jitter
(Note 19)
VINPP
Input Voltage Swing (Differential Configuration)
(Note 20)
tr
tf
Output Rise/Fall Times @ 50 MHz
(20% − 80%)
25°C
Min
Q, Q
85°C
Min
Typ
600
325
250
700
500
400
200
250
325
25
25
100
5
5
25
0.5
5
5
1
15
15
150
800
1200
125
175
225
fin = 2.5 GHz
fin = 1.5 Gb/s
fin = 2.5 Gb/s
Max
Max
Min
Typ
Max
550
300
200
700
500
400
225
300
350
25
25
100
5
5
25
25
25
100
ps
0.5
5
5
1
15
15
0.5
5
5
1
15
15
ps
150
800
1200
150
800
1200
mV
140
190
240
150
200
250
Unit
mV
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. Input edge rates 150 ps (20% − 80%).
15. Pulse Skew = |tPLH − tPHL|
16. Worst case difference between Q0 and Q1 outputs.
17. Skew is measured between outputs under identical transitions.
18. Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz.
19. Peak−to−Peak jitter with input NRZ data at PRBS 231−1 at 2.5 Gb/s with all inputs active.
20. Input voltage swing is a single−ended measurement operating in differential mode, with minimum propagation change of 50 ps.
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6
NB100LVEP17
10
9.0
750
8.0
Q AMP (mV)
7.0
650
6.0
5.0
550
4.0
450
3.0
2.0
350
250
RMS JITTER (ps)
OUTPUT VOLTAGE AMPLITUDE
(mV)
850
RMS JITTER (ps)
0.5
1.0
1.5
2.0
2.5
1.0
0
INPUT FREQUENCY (GHz)
850
10
9.0
750
8.0
Q AMP (mV)
7.0
650
6.0
5.0
550
4.0
450
3.0
2.0
350
250
RMS JITTER (ps)
OUTPUT VOLTAGE AMPLITUDE (mV)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 2.5 V, Ambient Temperature
RMS JITTER (ps)
0.5
1.0
1.5
2.0
2.5
1.0
0
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 3.3 V, Ambient Temperature
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 6. AC Reference Measurement
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7
NB100LVEP17
Q
Zo = 50
D
Receiver
Device
Driver
Device
Q
D
Zo = 50
50
50
VTT
VTT = VCC − 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
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