2.5 V/3.3 V 2:1:15
Differential ECL/PECL ÷1/÷2
Clock Driver
NB100LVEP222
The NB100LVEP222 is a low skew 2:1:15 differential ÷1/÷2 ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be used in a differential
configuration or single−ended (with VBB output reference bypassed
and connected to the unused input of a pair). Either of two fully
differential clock inputs may be selected. Each of the four output
banks of 2, 3, 4, and 6 differential pairs may be independently
configured to fanout 1X or 1/2X of the input frequency. When the
output banks are configured with the B1 mode, data can also be
distributed. The LVEP222 specifically guarantees low output to output
skew. Optimal design, layout, and processing minimize skew within a
device and from lot to lot. This device is an improved version of the
MC100LVE222 with higher speed capability and reduced skew.
The fsel pins and CLK_Sel pin are asynchronous control inputs.
Any changes may cause indeterminate output states requiring an MR
pulse to resynchronize any 1/2X outputs (See Figure 3). Unused
output pairs should be left unterminated (open) to reduce power and
switching noise.
The NB100LVEP222, as with most ECL devices, can be operated
from a positive VCC/VCC0 supply in LVPECL mode. This allows the
LVEP222 to be used for high performance clock distribution in
+2.5/3.3 V systems. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. For more information on using PECL, designers should refer
to Application Note AN1406/D. For a SPICE model, refer to
Application Note AN1560/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended LVPECL input conditions, the
unused differential input is connected to VBB as a switching reference
voltage. VBB may also rebias AC coupled inputs. When used, decouple
VBB and VCC/VCC0 via a 0.01 mF capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB should be left open.
Single−ended CLK input operation is limited to a VCC/VCC0 ≥ 3.0 V in
LVPECL mode, or VEE ≤ −3.0 V in NECL mode.
Features
•
•
•
•
•
www.onsemi.com
1
52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB100
LVEP222
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping
NB100LVEP222MNG
QFN−52
(Pb−Free)
260 Units /
Tray
20 ps Output−to−Output Skew
85 ps Part−to−Part Skew
Selectable 1x or 1/2x Frequency Outputs
LVPECL Mode Operating Range:
VCC/VCC0 = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC/VCC0 = 0 V with VEE = −2.375 V to −3.8 V
Internal Input Pulldown Resistors
•
• Performance Upgrade to ON Semiconductor’s MC100LVE222
• VBB Output
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2015
April, 2021− Rev. 14
1
Publication Order Number:
NB100LVEP222/D
CLK0*, CLK0**
CLK1*, CLK1**
CLK_Sel*
MR*
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Qc0:3, Qc0:3
Qd0:5, Qd0:5
fseln*
VBB
VCC, VCC0
VEE***
NC
Qa0
Qa1
Qa1
VCC0
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
50
49
48
47
46
45
44
43
42
41
VCC0
Qa0
51
VCC
1
39
VCC0
MR
2
38
Qc0
fsela
3
37
Qc0
fselb
4
36
Qc1
CLK0
5
35
Qc1
CLK0
6
34
Qc2
CLK_SEL
7
33
Qc2
CLK1
8
32
Qc3
CLK1
9
31
Qc3
VBB
10
30
VCC0
fselc
11
29
NC
fseld
12
28
NC
VEE
13
27
VCC0
16
17
18
19
20
21
22
23
24
25
Qd5
Qd4
Qd4
Qd3
Qd3
Qd2
Qd2
Qd1
Qd1
Qd0
26
15
Qd5
Qd0
14
VCC0
NB100LVEP222
Figure 1. QFN−52 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
Exposed Pad (EP)
40
VCC0
52
NB100LVEP222
Table 2. FUNCTION TABLE
Function
FUNCTION
ECL Differential Input Clock
ECL Differential Input Clock
ECL Clock Select
ECL Master Reset
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL Differential Outputs
ECL
1 or
2 Select
Reference Voltage Output
Positive Supply, VCC = VCC0
Negative Supply
No Connect
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the package is
electrically connected to VEE internally.
www.onsemi.com
2
Input
L
H
MR
CLK_Sel
fseln
Active
CLK0
÷1
Reset
CLK1
÷2
NB100LVEP222
MR
CLK0
CLK0
÷1
CLK1
2
Qa0:1
Qa0:1
÷2
CLK1
CLK_SEL
VBB
fsela
3
Qb0:2
Qb0:2
fselb
4
Qc0:3
Qc0:3
VCC/VCC0
VEE
fselc
6
Qd0:5
Qd0:5
fseld
Figure 2. Logic Diagram
CLK
MR
Q (B2)
Q (B1)
Figure 3. Master Reset (MR) Timing Diagram
www.onsemi.com
3
NB100LVEP222
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
37.5 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb−Free Pkg
QFN−52
Level 2
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−O @ 0.125 in
Transistor Count
821 Devices
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC/VCC0
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC/VCC0 = 0 V
−6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC/VCC0 = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
±0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note )
0 lfpm
500 lfpm
QFN−52
QFN−52
25
19.6
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note )
2S2P
QFN−52
21
°C/W
Tsol
Wave Solder
< 2 to 3 sec @ 248°C
265
°C
VI ≤ VCC/VCC0
VI ≥ VEE
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
4
NB100LVEP222
Table 5. LVPECL DC CHARACTERISTICS VCC = VCC0 = 2.5 V; VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
150
104
130
156
112
140
168
mA
VOH
Output HIGH Voltage (Note 3)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 3)
555
680
900
555
680
900
555
680
900
mV
VIH
Input HIGH Voltage (Single−Ended)
(Note 4)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single−Ended)
(Note 4)
555
900
555
900
555
900
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 5) (Figure 5)
1.2
2.5
1.2
2.5
1.2
2.5
V
150
mA
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
−150
150
0.5
−150
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.125 V to −1.3 V.
3. All loading with 50 W to VCC/VCC0 − 2.0 V.
4. Do not use VBB Pin #10 at VCC/VCC0 < 3.0 V (see AND8066/D).
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
Table 6. LVPECL DC CHARACTERISTICS VCC = VCC0 = 3.3 V; VEE = 0.0 V (Note 6)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
100
125
150
104
130
156
112
140
168
mA
VOH
Output HIGH Voltage (Note 7)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 7)
1355
1480
1700
1355
1480
1700
1355
1480
1700
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1355
1700
1355
1700
1355
1700
mV
VBB
Output Reference Voltage (Note 8)
1775
1975
1775
1975
1775
1975
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9) (Figure 5)
1.2
3.3
1.2
3.3
1.2
3.3
V
150
mA
Symbol
Characteristic
IIH
Input HIGH Current
IIL
Input LOW Current
1875
150
CLK
CLK
0.5
−150
1875
150
0.5
−150
0.5
−150
1875
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.925 V to −0.5 V.
7. All loading with 50 W to VCC/VCC0−2.0 V.
8. Single−Ended input operation is limited VCC/VCC0 ≥ 3.0 V in LVPECL mode.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
www.onsemi.com
5
NB100LVEP222
Table 7. LVNECL DC CHARACTERISTICS VCC = VCC0 = 0.0 V; VEE = −3.8 V to −2.375 V (Note 10)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
100
125
150
104
130
156
112
140
168
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 11)
−1145
−1020
−895
−1145
−1020
−895
−1145
−1020
−895
mV
VOL
Output LOW Voltage (Note 11)
−1945
−1820
−1600
−1945
−1820
−1600
−1945
−1820
−1600
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
−1600
−1945
−1600
−1945
−1600
mV
−1325
−1525
−1325
−1525
−1325
mV
0.0
V
150
mA
VIL
Input LOW Voltage (Single−Ended)
−1945
VBB
Output Reference Voltage (Note 12)
−1525
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13) (Figure 5)
IIH
Input HIGH Current
IIL
Input LOW Current
−1425
VEE + 1.2
0.0
VEE + 1.2
150
CLK
CLK
0.5
−150
−1425
0.0
VEE + 1.2
150
0.5
−150
−1425
0.5
−150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
10. Input and output parameters vary 1:1 with VCC/VCC0.
11. All loading with 50 W to VCC/VCC0 − 2.0 V.
12. Single−Ended input operation is limited VEE ≤ −3.0 V in NECL mode.
13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the
differential input signal.
www.onsemi.com
6
NB100LVEP222
Table 8. AC CHARACTERISTICS VCC = VCC0 = 2.375 to 3.8 V; VEE = 0.0 V or VCC = VCC0 = 0.0 V; VEE = −2.375 to −3.8 V
(Note 14)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
85°C
Min
Typ
Max
500
525
425
600
650
650
700
700
875
900
1000
1200
Min
Typ
Max
500
500
400
600
650
600
850
700
975
900
1150
1200
Unit
VOpp
Differential Output Voltage
(Figure 4)
fout = 50 MHz
fout = 0.8 GHz
fout = 1.0 GHz
500
550
500
600
650
650
tPLH
tPHL
Propagation Delay (Differential Configuration)
CLKx−QX
MR−QXX
650
700
800
900
900
1200
tskew
Within−Device Skew (Note 15)
(÷1 Mode)
− Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
10
10
20
10
40
40
60
40
10
10
20
10
40
40
60
40
10
10
20
10
40
40
60
40
− QaN, QbN, QdN
− All Outputs
10
20
40
60
10
20
40
60
10
20
40
60
− Qa[0:1]
− Qb[0:2]
− Qc[0:3]
− Qd[0:5]
15
15
20
15
70
70
70
70
10
10
20
10
40
40
50
40
15
10
15
15
70
40
70
70
− QaN, QbN, QdN
− All Outputs
15
20
70
70
10
20
40
50
15
15
70
70
Device−to−Device Skew (Differential
Configuration) (Note 16)
85
300
85
300
85
300
ps
Random Clock Jitter (Figure 4) (RMS)
1
5
1
4
1
5
ps
tskew
tskew
tJITTER
Within−Device Skew (Note 15)
(÷2 Mode)
mV
ps
ps
ps
VPP
Input Swing (Differential Configuration)
(Note 17) (Figure 5)
150
800
1200
150
800
1200
150
800
1200
mV
DCO
Output Duty Cycle
49.5
50
50.5
49.5
50
50.5
49.5
50
50.5
%
Output Rise/Fall Time 20%−80%
100
200
300
100
200
300
150
250
350
ps
tr/tf
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14. Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC/VCC0 − 2.0 V.
15. Skew is measured between outputs under identical transitions and operating conditions.
16. Device−to−Device skew for identical transitions at identical VCC/VCC0 levels.
17. VPP is the differential configuration input voltage swing required to maintain AC characteristics including tPD and device−to−device skew.
www.onsemi.com
7
NB100LVEP222
10
9.0
800
8.0
Q AMP (÷ 2)
700
7.0
6.0
600
Q AMP (÷ 1)
5.0
500
4.0
400
3.0
RMS JITTER
2.0
300
200
RMS JITTER (ps)
VOPP, OUTPUT VOLTAGE (mV)
900
1.0
0.1
0.5
1.0
INPUT FREQUENCY (GHz)
0
2.0
1.5
Figure 4. Output Voltage (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER) @ 255C
VCC/VCC0(LVPECL)
VPP
VIH(DIFF)
VIHCMR
VIL(DIFF)
VEE
Figure 5. LVPECL Differential Input Levels
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
www.onsemi.com
8
NB100LVEP222
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN52 8x8, 0.5P
CASE 485M−01
ISSUE C
1
52
D
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
PIN ONE
REFERENCE
DATE 16 FEB 2010
B
DIM
A
A1
A2
A3
b
D
D2
E
E2
e
K
L
E
2X
0.15
C
2X
0.15 C
A2
0.10 C
GENERIC MARKING
DIAGRAM
A
0.08 C
SEATING PLANE
A3
A1
1
REF
C
XXXXXXXXX
XXXXXXXXX
AWLYYWWG
D2
14
52 X
L
26
27
13
XXXXXXXXX
A
WL
YY
WW
G
E2
39
1
52 X
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.60
0.80
0.20 REF
0.18
0.30
8.00 BSC
6.50
6.80
8.00 BSC
6.50
6.80
0.50 BSC
0.20
--0.30
0.50
52
40
e
52 X
b
= Device Code
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
RECOMMENDED
SOLDERING FOOTPRINT
NOTE 3
0.10 C A B
8.30
0.05 C
52X
0.62
6.75
6.75
PKG
OUTLINE
DOCUMENT NUMBER:
DESCRIPTION:
98AON12057D
52 PIN QFN, 8X8, 0.5P
0.50
PITCH
8.30
52X
0.30
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
