NB2309A

NB2309A 3.3 V Zero Delay Clock Buffer The NB2309A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks. It accepts one reference input and drives out nine low−skew clocks. It is available in a 16 pin package. The −1H version of the NB2309A operates at up to 133 MHz, and has higher drive than the −1 devices. All parts have on−chip PLL’s that lock to an input clock on the REF pin. The PLL feedback is on−chip and is obtained from the CLKOUT pad. The NB2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three−stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple NB2309A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle−to−cycle jitter. The input and output propagation delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps. The NB2309A is available in two different configurations, as shown in the ordering information table. The NB2309A1 is the base part. The NB2309Ax1H* is the high drive version of the −1 and its rise and fall times are much faster than −1 part. Features http://onsemi.com MARKING DIAGRAMS* 16 1 SOIC−16 D SUFFIX CASE 751B 1 16 16 1 TSSOP−16 DT SUFFIX CASE 948F XXXX A WL, L Y W, WW G or G XXXX XXXX ALYWG G 16 XXXXXXXXG AWLYWW 1 • 15 MHz to 133 MHz Operating Range, Compatible with CPU and • • • • • • • • • • PCI Bus Frequencies Zero Input − Output Propagation Delay Multiple Low−Skew Outputs Output−Output Skew Less than 250 ps Device−Device Skew Less than 700 ps One Input Drives 9 Outputs, Grouped as 4 + 4 + 1 Less than 200 ps Cycle−to−Cycle Jitter is Compatible with PentiumR Based Systems Test Mode to Bypass PLL Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP 3.3 V Operation, Advanced 0.35 m CMOS Technology These are Pb−Free Devices** = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. *x = C for Commercial; I for Industrial. **For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 4 1 Publication Order Number: NB2309A/D NB2309A PLL REF MUX CLKOUT CLKA1 CLKA2 CLKA3 S2 SELECT INPUT DECODING S1 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Figure 1. Block Diagram Table 1. SELECT INPUT DECODING S2 0 0 1 1 S1 0 1 0 1 Clock A1 − A4 Three−state Driven Driven Driven Clock B1 − B4 Three−state Three−state Driven Driven CLKOUT (Note 1) Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL ShutDown N N Y N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. http://onsemi.com 2 NB2309A REF CLKA1 CLKA2 1 2 3 4 16 15 14 13 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 VDD GND NB2309A 5 6 7 8 12 11 10 9 CLKB1 CLKB2 S2 Figure 2. Pin Configuration Table 2. PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF (Note 2) CLKA1 (Note 3) CLKA2 (Note 3) VDD GND CLKB1 (Note 3) CLKB2 (Note 3) S2 (Note 4) S1 (Note 4) CLKB3 (Note 3) CLKB4 (Note 3) GND VDD CLKA3 (Note 3) CLKA4 (Note 3) CLKOUT (Note 3) Description Input reference frequency, 5 V tolerant input. Buffered clock output, Bank A. Buffered clock output, Bank A. 3.3 V supply. Ground. Buffered clock output, Bank B. Buffered clock output, Bank B. Select input, bit 2. Select input, bit 1. Buffered clock output, Bank B. Buffered clock output, Bank B. Ground. 3.3 V supply. Buffered clock output, Bank A. Buffered clock output, Bank A. Buffered output, internal feedback on this pin. 2. Weak pulldown. 3. Weak pulldown on all outputs. 4. Weak pullup on these inputs. http://onsemi.com 3 NB2309A Table 3. MAXIMUM RATINGS Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Maximum Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL−STD−883, Method 3015) Min −0.5 −0.5 −0.5 −65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 Unit V V V °C °C °C V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Table 4. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Commercial Industrial Description Min 3.0 0 −40 Max 3.6 70 85 30 10 7 Unit V °C pF pF pF Table 5. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter VIL VIH IIL IIH VOL VOH IDD IDD Description Input LOW Voltage (Note 5) Input HIGH Voltage (Note 5) Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current (Commercial Temp) Supply Current (Industrial Temp) VIN = 0 V VIN = VDD IOL = 8 mA (−1) IOL = 12 mA (−1H) IOH = −8 mA (−1) IOH = −12 mA (−1H) Unloaded outputs at 66.67 MHz, Select inputs at VDD Unloaded outputs at 100 MHz 66.67 MHz 33 MHz Select inputs at VDD or GND, at Room Temp 2.4 34 50 34 19 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V mA mA V V mA mA 5. REF input has a threshold voltage of VDD/2. http://onsemi.com 4 NB2309A Table 6. SWITCHING CHARACTERISTICS (Commercial and Industrial) (Note 6) Parameter 1/t1 1/t1 t3 t4 t5 t6 t7 t8 tJ tLOCK trin tfin Description Output Frequency Duty Cycle = (t2 / t1) * 100 Output Rise Time Output Fall Time Output−to−Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device−to−Device Skew Output Slew Rate Cycle−to−Cycle Jitter PLL Lock Time REF Input Rise Time REF Input Rise Fall Time (−1, −1H) (−1H) (−1, −1H) (−1H) 30 pF load 10 pF load Measured at 1.4 V, FOUT = 66.67 MHz < 50 MHz Measured between 0.8 V and 2.0 V Measured between 2.0 V and 0.8 V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of the device Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Measured between 0.8 V to 2.0 V Measured between 2.0 V to 0.8 V 1 200 1.0 1.0 1.0 0 0 Test Conditions Min 15 15 40 45 50 50 Typ Max 100 133.33 60 55 2.5 1.5 1.5 250 ±350 700 Unit MHz % ns ns ps ps ps V/ns ps ms ns ns 6. All parameters specified with loaded outputs and apply to both PLL−Mode and PLL−Bypass Mode. http://onsemi.com 5 NB2309A Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input−output delay. For applications requiring zero input−output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero−input−output delay. SWITCHING WAVEFORMS t1 t2 1.4 V 1.4 V 1.4 V OUTPUT 2.0 V 0.8 V t3 2.0 V 0.8 V t4 0V 3.3 V Figure 3. Duty Cycle Timing Figure 4. All Outputs Rise/Fall Time OUTPUT OUTPUT 1.4 V 1.4 V t5 INPUT OUTPUT t6 V DD 2 V DD 2 Figure 5. Output − Output Skew Figure 6. Input − Output Propagation Delay CLKOUT, Device 1 CLKOUT, Device 2 t7 V DD 2 V DD 2 Figure 7. Device − Device Skew TEST CIRCUITS VDD VDD 0.1 mF VDD 0.1 mF 1 kW OUTPUTS 1 kW VDD GND 0.1 mF GND GND 10 pF OUTPUTS CLKOUT CLOAD VDD 0.1 mF GND Figure 8. Test Circuit #1 Figure 9. Test Circuit #2 For parameter t8 (output slew rate) on −1H devices http://onsemi.com 6 NB2309A ORDERING INFORMATION Device NB2309AC1DG NB2309AC1DR2G NB2309AI1DG NB2309AI1DR2G NB2309AC1HDG NB2309AC1HDR2G NB2309AI1HDG NB2309AI1HDR2G NB2309AC1DTG NB2309AC1DTR2G NB2309AI1DTG NB2309AI1DTR2G NB2309AC1HDTG NB2309AC1HDTR2G NB2309AI1HDTG NB2309AI1HDTR2G Marking 2309AC1G 2309AC1G 2309AI1G 2309AI1G 2309AC1HG 2309AC1HG 2309AI1HG 2309AI1HG 2309AC1 2309AC1 2309AI1 2309AI1 2309AC1H 2309AC1H 2309AI1H 2309AI1H Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) SOIC−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) Shipping† 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 48 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel Availability Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB2309A PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE A 16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 9 2X L/2 J1 B − U− L PIN 1 IDENT. 1 8 SECTION N−N J N 0.15 (0.006) T U S 0.25 (0.010) M A −V− N F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E http://onsemi.com 8 ÇÉ Ç ÇÉ ÇÉ Ç ÇÉ −W− NB2309A PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE J − A− 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 − B− 1 8 P 8 PL 0.25 (0.010) M B S G F K C −T− SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S Pentium is a registered trademark of Intel Corporation. Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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