3.3V / 2.5V / 1.8V / 1.5V
2:1:5 LVCMOS Fanout Buffer
NB3F8L3005C
Description
The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOx supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or a differential/SE Clock /
Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or
SSTL and Single−Ended levels. The MUX control line, SEL selects
CLK/CLK, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (Hi−Z) when Low per
Table 4.
Outputs consist of five single−ended LVCMOS outputs.
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MARKING
DIAGRAM
1
QFN24
G SUFFIX
CASE 485DJ
Features
A
L
Y
W
G
• Five LVCMOS / LVTTL Outputs up to 200 MHz
• Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, or
•
•
•
•
•
•
•
•
•
•
LVCMOS/LVTTL
Crystal Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 156.25 MHz, (12 kHz – 20 MHz):
0.03 ps (Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
♦ Single 3.3 V ± 5%
♦ Single 2.5 V ± 5%
♦ Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial Temperature Range: −40°C to 85°C
These are Pb−Free Devices
Applications
•
•
•
•
April, 2021 − Rev. 2
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
End Products
•
•
•
•
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
© Semiconductor Components Industries, LLC, 2015
NB3F8L
3005C
ALYWG
G
1
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
Publication Order Number:
NB3F8L3005C/D
NB3F8L3005C
BANK A
VDD
VDDOA
GND
Q0
SEL
Q1
CLK
CLK
XTAL_IN
BANK B
OSC
XTAL_OUT
VDDOB
Q2
Q3
Q4
SYNC
OE
OE
VDD
SEL
CLK
CLK
GND
Figure 1. Simplified Logic Diagram
24
23
22
21
20
19
Exposed Pad
(EP)
GND
1
18
VDDOB
VDDOA
2
17
Q4
Q0
3
16
GND
GND
4
15
Q3
Q1
5
14
VDD0B
VDDOA
6
13
Q2
11
12
GND
10
GND
9
XTAL_OUT
8
XTAL_IN
GND
7
VDD
NB3F8L3005C
Figure 2. Pinout Configuration (Top View)
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NB3F8L3005C
Table 1. PIN DESCRIPTION
Input
Default
Number
Name
Type
Description
3, 5
Q0, Q1
LVCMOS
Outputs − Bank A
13, 15, 17
Q2, Q3, Q4
LVCMOS
Outputs − Bank B
2, 6
VDDOA
Power
Positive Supply Pins for Bank A Outputs Q0 − Q1
14, 18
VDDOB
Power
Positive Supply Pins for Bank B Outputs Q2 − Q4
1, 4, 7, 11,
12, 16, 19
GND
GND
Ground Supply
VDD Positive Supply pin for Core and Inputs.
8, 23
VDD
Power
9
XTAL_IN
XTAL OSC / CLK Input
10
XTAL_OUT
XTAL OSC Output
20
CLK
Diff / SE Input
Pullup /
Pulldown
Inverting differential clock input
21
CLK
Diff / SE Input
Pulldown
Non-inverting clock input
22
SEL
LVCMOS / LVTTL
Input
Pulldown
Input clock select. See Table 3 for function. Input Pulldown
24
OE
LVCMOS / LVTTL
Input
Pulldown
Output Enable Control. See Table 4 for function.
−
EP
−
Crystal Oscillator Interface or External Clock Source at
LVCMOS Levels
Crystal Interface
The Exposed Pad (EP) on the QFN−24 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die,
and must be electrically connected to GND.
1. All VDD, VDDOx and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each VDD and VDDOx
with 0.01 mF CAP to GND.
Table 2. PIN CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
CIN
Input Capacitance
4
pF
RPU
Input Pullup Resistor
50
kW
RPD
Input Pulldown Resistor
50
kW
CPD
Power Dissipation Capacitance (per output)
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
pF
ROUT
Output Impedance
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
W
20
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3
NB3F8L3005C
FUNCTION TABLES
Table 3. CLOCK ENABLE (SELx) FUNCTION TABLE
SEL Input
Table 5. CLK INPUT VS. OUTPUT STATUS
Selected Input Clock
Input Condition
Output
0
CLK/CLK
CLK/CLK = OPEN
Logic LOW
1
Crystal Osc Input
CLK/CLK = GND
Undefined
CLK = HIGH; CLK = LOW
Logic HIGH
CLK = LOW; CLK = HIGH
Logic LOW
Table 4. CLOCK OUTPUT ENABLE (OE) FUNCTION
TABLE
OE Input
Qn Outputs
0
Disabled, High Impedance
1
Outputs Enabled
Table 6. CRYSTAL CHARACTERISTICS
Parameter
Min
Max
Unit
50
MHz
Equivalent Series Resistance (ESR)
50
W
Shunt Capacitance
7
pF
100
mW
Mode of Oscillation
Typ
Fundamental
Frequency
10
Drive Power
Table 7. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
>2 kV
200 V
QFN24
MSL 1
Moisture Sensitivity Level (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
474
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 8. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
VDD,
VDDOx
Positive Power Supply
VI
Input Voltage
XTAL_IN
Diff, SELx, OE Inputs
VO
Output Voltage
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction−to−Ambient)
QFN24
QFN24
θJC
Thermal Resistance (Junction−to−Case)
QFN24
Condition
Rating
Unit
GND = 0 V
4.6
V
0 v VI v VDD
–0.5 v VI v VDD + 0.5
V
– 0.5 v VO v VDDOx + 0.5
V
−65 to +150
_C
0 lfpm
500 lfpm
37
32
_C/W
(Note 3)
11
_C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3F8L3005C
Table 9. POWER SUPPLY CHARACTERISTICS VDD ≥ VDDO; VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5%
(2.375 V to 2.625 V) and VDDOx = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V)
or 1.5 V ± 0.15 V (1.35 V to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
IDD
VDD Power Supply Current
IDDO
VDDO Power Supply
Current
IDD +
IDDO
Total Device Current with
Loads on All Outputs
Min
Typ
Max
Unit
fIN = 0 MHz
VDDO = 3.3 V, fIN = 100 MHz
VDDO = 2.5 V, fIN = 100 MHz
30
30
20
38
mA
OE = 0, no load
VDDO = 3.3 V, OE = 1, fIN = 100 MHz
VDDO = 2.5 V, OE = 1, fIN = 100 MHz
0.1
7
5
mA
OE = 1, fIN = 100 MHz
OE = 0
48
16
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. DC CHARACTERISTICS TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min
VIH
LVCMOS / LVTTL Input High Voltage
(OE, SEL)
VDD = 3.3 V ±5%
VDD = 2.5 V ± 5%
VIL
LVCMOS / LVTTL Input Low Voltage
(OE, SEL)
VDD = 3.3 V ±5%
VDD = 2.5 V ± 5%
IIH
Input High Current
IIL
Input Low Current
VOH
Output High Voltage
VOL
Output Low Voltage
OE, SEL
CLK/CLK
VDD = VIN = 3.465 V
VDD = VIN = 3.465 V or 2.625 V
OE, SEL
CLK
CLK
VDD = 3.465 V; VIN = 0.0 V
VDD = 3.465 V or 2.625 V VIN = 0.0 V
VDD = 3.465 V or 2.625 V VIN = 0.0 V
Typ
Max
Unit
1.6
1.3
VDD + 0.3
VDD + 0.3
V
−0.3
−0.3
0.8
0.4
V
100
100
−5
−5
−150
5
VDDO
− 0.1
mA
mA
V
VDDOx = 3.3 V ± 5% or 2.5 V ± 5%
0.5
VDDOx = 1.8 V ± 0.2 V
0.4
VDDOx = 1.5 V ± 0.15 V
0.37
V
VPP
Peak−to−Peak Input Voltage
VIL > −0.3 V
CLKx/CLKx
VDD = 3.3 V ±5% or VDD = 2.5 V ± 5%
0.15
1.3
V
VIHCMR
Input High Level Common Mode
Range
VCM = VIH; VIL > −0.3 V CLKx/CLKx
VDD = 3.3 V ±5% or VDD = 2.5 V ± 5%
0.5
VDD − 0.85
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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NB3F8L3005C
Table 11. AC CHARACTERISTICS VDD ≥ VDDO; VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V)
and VDDOx = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V
(1.35 V to 1.65 V); TA = −40°C to 85°C
Symbol
fMAX
tsk(o)
tJITTERF
Parameter
Output Frequency
Test Conditions
Min
50
MHz
Using External
Clock Source
(Note 4)
DC
200
MHz
25
ps
10
Input clock from
CLK/CLK
VDDOx = 3.3 V ± 5%
0.03
VDDOx = 2.5 V ± 5%
0.03
VDDOx = 1.8 V ± 0.2 V
0.03
VDDOx = 1.5 V ± 0.15 V
0.03
VDDOx = 3.3 V ± 5%
0.03
VDDOx = 2.5 V ± 5%
0.03
VDDOx = 1.8 V ± 0.2 V
0.03
VDDOx = 1.5 V ± 0.15 V
0.03
VDDOx = 3.3 V ± 5%
0.03
VDDOx = 2.5 V ± 5%
0.03
VDDOx = 1.8 V ± 0.2 V
0.03
Input clock from
crystal
VDDOx = 1.5 V ± 0.15 V
odc
PSRR
Unit
10
External clock
over drives
crystal interface
tR / tF
Max
Using External
Crystal
Output Skew (Notes 5 and 6)
Additive RMS
Phase Jitter
(Integrated
12 kHz − 20 MHz)
fC = 156.25 MHz
Typ
Output Rise/Fall Time (20% and 80%)
CL = 10 pF
0.03
VDDOx = 3.3 V ± 5%
150
350
500
VDDOx = 2.5 V ± 5%
150
350
500
VDDOx = 1.8 V ± 0.2 V
150
350
600
VDDOx = 1.5 V ± 0.15 V
150
350
600
VDDOx = 3.3 V ± 5%
45
55
Output Duty Cycle
Power Supply
Ripple Rejection
ps
VDDOx = 2.5 V ± 5%
40
60
VDDOx = 1.8 V ± 0.2 V
40
60
VDDOx = 1.5 V ± 0.15 V
40
60
100 kHz, 100 mVPP
Ripple Injected on VDD,
VDDO = 2.5 V
−44
ps
%
dBc
tEN
Output Enable
Time (Note 7)
OE
4
cycles
tDIS
Output Disable
Time (Note 7)
OE
4
cycles
MUX_ISOLATION
MUX_ISOLATION
155.52 MHz
55
dB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. XTAL_IN can be overdriven relative to a signal a crystal would provide.
5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2.
6. This parameter is defined in accordance with JEDEC Standard 65.
7. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information
8. AC parameters for LVCMOS are dependent upon output capacitive loading.
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NB3F8L3005C
PARAMETER MEASUREMENT INFORMATION
VDD = +3.3 V ±5%
VDD = +2.5 V ±5%
VDDOx = VDD = +3.3 V ±5%
VDDOx = VDD = +2.5 V ±5%
SCOPE
Qx
Qx
Z = 50 W
LVCMOS
SCOPE
Z = 50 W
LVCMOS
50 W
50 W
GND
GND
3.3 V Core / 3.3 V Output Load AC Test Circuit
2.5 V Core / 2.5 V Output Load AC Test Circuit
VDD = +3.3 V ±5%
VDD = +3.3 V ±5%
VDDOx = +2.5 V ±5%
VDDOx = +1.8 V ±0.1 V
SCOPE
Qx
Qx
Z = 50 W
LVCMOS
SCOPE
Z = 50 W
LVCMOS
50 W
50 W
GND
GND
3.3 V Core / 2.5 V Output Load AC Test Circuit
3.3 V Core / 1.8 V Output Load AC Test Circuit
VDD = +3.3 V ±5%
VDD = +2.5 V ±5%
VDDOx = +1.5 V ±0.15 V
VDDOx = +1.8 V ±0.1 V
SCOPE
Qx
LVCMOS
SCOPE
Qx
Z = 50 W
Z = 50 W
LVCMOS
50 W
50 W
GND
GND
3.3 V Core / 1.5 V Output Load AC Test Circuit
2.5 V Core / 1.8 V Output Load AC Test Circuit
VDD = +2.5 V ±5%
VDDOx = +1.5 V ±0.15 V
SCOPE
Qx
LVCMOS
Z = 50 W
50 W
GND
2.5 V Core / 1.5 V Output Load AC Test Circuit
Figure 3. Operational Supply and Termination Test Conditions
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NB3F8L3005C
PARAMETER MEASUREMENT INFORMATION
VDDOx/2
VDD
Qx
CLK
Xpoint
VPP
VCMR
CLK
VDDOx/2
Qv
GND
tsk(0)
Differential Input Level
Within Device Output Skew
VDD
VDD/2
OE
tEN tDIS
VDDOx/2
tPW
Qx
VOH
VDDOx/2
Qx
VDDOx/2
0V
tPeriod
VOL
odc = (tPW / tPeriod) x 100%
Output Enable /Disable
(OE HIGH = Enabled)
Output Duty Cycle / Pulse Width / Period
80%
Qx
80%
20%
tR
Amplitud e (dB)
Spectrum of Output Signal Qx
20%
tF
A0
MUX_ISOL = A0 - A1
MUX selects
static input
A1
Output Rise/Fall Time
MUX selects
active inpu t clock
signal
fc
(Fundamental)
Frequ ency (Hz)
MUX Isolation
Figure 4. Operational Waveforms and MUX Input Isolation Plot
APPLICATION INFORMATION
Recommendations for Unused LVCMOS Output Pins
LVCMOS Control Pins
Inputs:
All control pins have internal pulldowns; additional
resistance is not required but can be added for additional
protection. A 1 kW resistor can be used.
CLK/CLK Inputs
For applications not requiring the use of the differential
input, both CLK and CLK can be left floating. Though not
required, but for additional protection, a 1 kW resistor can be
tied from CLK to ground.
Power Supplies
VDD is the power supply for the core and input circuitry.
VDDOA and VDDOB are two separate positive power
supplies for two banks of outputs:
VDDOA pins 2 and 6 are connected internally for outputs
Q0 − Q1.
VDDOB pins 14 and 18 are connected internally for outputs
Q2 − Q4.
Crystal Inputs
For applications not requiring the use of the crystal
oscillator input, both XTAL_IN and XTAL_OUT can be left
floating. Though not required, but for additional protection,
a 1 kW resistor can be tied from XTAL_IN to ground.
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NB3F8L3005C
Differential Input with Single−Ended Interconnect
amplitude in half. Termination may be done by using Rs or
by using R1 and R2. First, Rs = 0 and then R3 and R4 in
parallel should equal the transmission line impedance. For
most 50 W applications, R1 and R2 can be 100 W. The
differential input can handle full rail LVCMOS signaling,
but it is recommended that the amplitude be reduced. The
datasheet specifies a differential amplitude which needs to
be doubled for a single ended equivalent stimulus. VILmin
cannot be less than −0.3 V and VIHmax cannot be more than
VDD + 0.3 V. The datasheet specifications are characterized
and guaranteed by using a differential signal.
Refer to Figure 5 to interconnect a single−ended to a
Differential Pair of inputs. The reference bias voltage VREF
= VDD/2 is generated by the resistor divider of R3 and R4.
Bypass capacitor (C1) can filter noise on the DC bias. This
bias circuit should be located as close to the input pin as
possible. Adjust R1 and R2 to common mode voltage of the
signal input swing to preserve duty cycle.
This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition,
matched termination by R1 and R2 will attenuate the signal
VDD
Single
Ended RO
Driver
VDD
Rs
R1
100 W
VDD
R3
1 kW
Zo = 50 W
Z0 = RO + Rs
CLKx
Differential In
R2
100 W
GND = 0.0
R4
1 kW
GND = 0.0
CLKx
C1
0.1 mF
GND = 0.0
Figure 5. Differential Input with Single−ended Interconnect
Crystal Input Interface
CLOCK Overdriving the XTAL Interface
The device has been characterized with 18 pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 6 below as 15 pF were determined using an 18 pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
The XTAL_IN input can accept a single−ended LVCMOS
signal through an AC coupling capacitor. A general
LVCMOS interface diagram is shown in Figure 7 and a
general LVPECL interface in Figure 8. The XTAL_OUT
pin must be left floating. The maximum amplitude of the
input signal should not exceed 2 V and the input edge rate
can be as slow as 10 ns. This configuration requires that the
output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 W applications,
R1 and R2 can be 100 W. This can also be accomplished by
removing R1 and making R2 50 W. By overdriving the
crystal oscillator, the device will be functional, but note, the
device performance is guaranteed by using a quartz crystal.
Figure 6. Crystal Input Interface
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NB3F8L3005C
VDD
LVMOS
VDD
R1
100 W
Rs
C1
0.1 mF
XTAL_IN
Zo = 50 W
RO
Z0 = RO + Rs
R2
100 W
GND = 0.0 V
NC
XTAL_OUT
GND = 0.0 V
Figure 7. General Diagram for LVCMOS Driver to XTAL Input Interface Use Rs or R1 / R2
VDD
C1
0.1 mF
XTAL_IN
Zo = 50 W
LVPECL
Zo = 50 W
NC
50 W
XTAL_OUT
50 W
GND = 0.0 V
VTT = VDD − 2.0 V
Figure 8. General Diagram for LVPECL Driver to XTAL Input Interface
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NB3F8L3005C
Differential Clock Input Interface
input interfaces suggested here are examples only. If the
driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the
driver component to confirm the driver termination
requirements.
The CLK / CLK accept LVDS, LVPECL, SSTL, HCSL
differential signals. Signals must meet the VPP and VCMR
input requirements. Figures 9 to 13 show interface
examples for the CLK / CLK input with built−in 50 W
terminations driven by the most common driver types. The
VDD = +3.3 V
VDD = +3.3 V
VDD = +3.3 V
Qx
125 W
125 W
CLKx
Zo = 50 W
LVPECL
CLKx
Zo = 50 W
Qx
VDD = +3.3 V
84 W
VDD = +3.3 V
CLKx
Qx
Zo = 50 W
LVPECL
Differential
In
Qx
84 W
GND = 0.0 V
GND = 0.0 V
CLKx
Zo = 50 W
50 W
GND = 0.0 V
VDD = +3.3 V
Figure 10. CLK / CLK Input Driven by 3.3 V
LVPECL Driver (“Y” Parallel Termination)
VDD = +3.3 V
VDD = +3.3 V
HCSL
CLKx
Zo = 50 W
VDD = +3.3 V
Qx
CLKx
Zo = 50 W
Qx 33 W (Opt)
50 W
GND = 0.0 V
GND = 0.0 V
Figure 9. CLK / CLK Input Driven by 3.3 V LVPECL
Driver (Thevenin Parallel Termination)
Qx 33 W (Opt)
50 W
50 W
GND = 0.0 V
Differential
In
LVDS
Differential
In
CLKx
Zo = 50 W
100 W
Zo = 50 W
CLKx
Differential
In
Qx
50 W
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
Figure 11. CLK / CLK Input Driven by a 3.3 V
HCSL Driver
Figure 12. CLK / CLK Input Driven by 3.3 V
LVDS Driver
VDD = +2.5 V
VDD = +3.3 V
VDD = +2.5 V
Qx
120 W
120 W
CLKx
Zo = 50 W
SSTL
CLKx
Zo = 50 W
Qx
Differential
In
120 W
120 W
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
Figure 13. CLK / CLK Input Driven by 2.5 V SSTL Driver
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NB3F8L3005C
VFQFN EPAD Thermal Release Path
to ground through these vias. The vias act as “heat pipes”.
The number of vias (i.e. “heat pipes”) is application specific
and dependent upon the package power dissipation as well
as electrical conductivity requirements. Thus, thermal and
electrical analysis and/or testing are recommended to
determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias
is incorporated in the land pattern. It is recommended to use
as many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13 mils
(0.30 to 0.33 mm) with 1 oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during
the soldering process which may result in voids in solder
between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only.
In order to maximize both the removal of heat from the
package and the electrical performance, a land pattern must
be incorporated on the Printed Circuit Board (PCB) within
the footprint of the package corresponding to the exposed
metal pad or exposed heat slug on the package, as shown in
Figure 14. The solderable area on the PCB, as defined by the
solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should
be designed on the PCB between the outer edges of the land
pattern and the inner edges of pad pattern for the leads to
avoid any shorts. While the land pattern on the PCB provides
a means of heat transfer and electrical grounding from the
package to the board through a solder joint, thermal vias are
necessary to effectively conduct from the surface of the PCB
to the ground plane(s). The land pattern must be connected
Figure 14. Suggested Assembly for Exposed Pad Thermal Release Path – Cut−away View (not to scale)
ORDERING INFORMATION
Package
Shipping†
NB3F8L3005CMNTXG
QFN24
(Pb−Free)
3000 / Tape & Reel
NB3F8L3005CMNTBG
QFN24
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN24, 4x4, 0.5P
CASE 485DJ
ISSUE O
DATE 28 OCT 2013
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.10 C
2X
ÉÉ
ÉÉ
ÇÇÇ
ÉÉÉ
ÉÉÉ
EXPOSED Cu
MOLD CMPD
ÉÉ
ÇÇ
ÇÇ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A3
A1
DETAIL B
E
ALTERNATE
CONSTRUCTIONS
0.10 C TOP VIEW
L
(A3)
DETAIL B
A
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L
L1
0.10 C
DETAIL A
0.08 C
NOTE 4
SIDE VIEW
A1
D2
DETAIL A
C
24X
7
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
13
E2
24
24X
b
0.10 C A B
BOTTOM VIEW
0.05 C
NOTE 3
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
4.30
XXXXXX
XXXXXX
ALYWG
G
XXXXXX= Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
1
e
e/2
GENERIC
MARKING DIAGRAM*
1
L
MILLIMETERS
MIN
MAX
0.80
0.90
0.00
0.05
0.20 REF
0.20
0.30
4.00 BSC
2.40
2.60
4.00 BSC
2.40
2.60
0.50 BSC
0.30
0.50
--0.15
24X
0.62
2.66
1
2.66 4.30
PKG
OUTLINE
24X
0.32
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON79518F
QFN24, 4X4, 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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