NB3F8L3010CMNG

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Other names and brands may be claimed as the property of others. 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer NB3F8L3010C Description The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOn supplies which must be equal or less than VDD. A Mux selects between a Crystal input, or either of two differential/SE Clock / Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The MUX control lines, SEL0 and SEL1, select CLK0/CLK0, CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is disabled when a Clock input is selected. Output enable pin, OE, synchronously forces a High Impedance state (HZ) when Low per Table 4. Outputs consist of 10 single−ended LVCMOS outputs. Features • • • • • • • • • • • • Ten CMOS / LVTTL Outputs up to 200 MHz Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL Crystal Oscillator Interface Crystal Input Frequency Range: 10 MHz to 50 MHz Output Skew: 10 ps Typical Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps (Typical) Synchronous Output Enable Output Defined Level When Input is Floating Power Supply Modes: ♦ Single 3.3 V ♦ Single 2.5 V ♦ Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply ♦ Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply ♦ Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply ♦ Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply ♦ Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply Two Separate Output Bank Power Supplies Industrial temp. range -40°C to 85°C These are Pb−Free Devices www.onsemi.com MARKING DIAGRAM 1 1 32 QFN32 G SUFFIX CASE 488AM A WL YY WW G NB3F8L 3010C AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information page 12 of this data sheet. Applications • • • • Clock Distribution Networking and Communications High End Computing Wireless and Wired Infrastructure End Products • • • • Servers Ethernet Switch/Routers ATE Test and Measurement © Semiconductor Components Industries, LLC, 2016 December, 2019 − Rev. 8 1 Publication Order Number: NB3F8L3010C/D NB3F8L3010C BANK A VDD Q0 VDDOA VDDOB GND Q1 SEL0 Q2 SEL1 Q3 CLK0 CLK0 Q4 CLK1 CLK1 XTAL_IN BANK B OSC XTAL_OUT Q5 Q6 Q7 Q8 Q9 SYNC OE GND OE SEL0 SEL1 CLK1 CLK1 GND GND 32 31 30 29 28 27 26 25 Figure 1. Simplified Logic Diagram Exposed Pad (EP) Q0 1 24 Q9 VDDOA 2 23 VDDOB Q1 3 22 Q8 GND 4 21 GND 20 Q7 NB3F8L3010C 18 Q6 Q4 8 17 Q5 CLK0 XTAL_IN GND GND 16 7 GND 15 Q3 14 VDDOB CLK0 13 19 XTAL_OUT 12 6 11 VDDOA VDD 10 5 9 Q2 Figure 2. Pinout Configuration (Top View) www.onsemi.com 2 NB3F8L3010C Table 1. PIN DESCRIPTION Input Default Number Name Type Description 1, 3, 5, 7, 8 Q0, Q1, Q2, Q3, Q4 LVCMOS Outputs − Bank A 17, 18, 20, 22, 24 Q5, Q6, Q7, Q8, Q9 LVCMOS Outputs − Bank B 2, 6 VDDOA Power Positive Supply Pins for Bank A Outputs Q0 − Q4 19, 23 VDDOB Power Positive Supply Pins for Bank B Outputs Q5 − Q9 4, 9, 15, 16, 21, 25, 26, 32 GND GND Ground Supply VDD Positive Supply pin for Core and Inputs. 10 VDD Power 11 XTAL_IN XTAL OSC / CLK Input 12 XTAL_OUT XTAL OSC Output 13 CLK0 Diff / SE Input Pulldown Non-inverting clock/data input 0. 14 CLK0 Diff / SE Input Pullup / Pulldown Inverting differential clock input 0. 27 CLK1 Diff / SE Input Pullup / Pulldown Inverting differential clock input 1 28 CLK1 Diff / SE Input Pulldown Non-inverting clock/data input 1 29 SEL1 LVCMOS / LVTTL Input Pulldown Input clock select. See Table 3 for function. Input Pulldown 30 SEL0 LVCMOS / LVTTL Input Pulldown Input clock select. See Table 3 for function. Input Pulldown 31 OE LVCMOS / LVTTL Input Pulldown Output Enable Control. See Table 4 for function. − EP − Crystal Oscillator Interface or External Clock Source at LVCMOS Levels Crystal Oscillator Interface The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is electrically connected to the die, and must be electrically connected to GND. 1. All VDD, VDDOn and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each VDD and VDDOn with 0.01 mF CAP to GND. Table 2. PIN CHARACTERISTICS Symbol CIN R Parameter Min Typ Max Unit Input Capacitance 4 pF Input Pulldown Resistor; Input Pulldown Resistor 50 kW CPD Power Dissipation Capacitance (per output) VDDO = 3.3 V VDDO = 2.5 V VDDO = 1.8 V VDDO = 1.5 V pF ROUT Output Impedance VDDO = 3.3 V VDDO = 2.5 V VDDO = 1.8 V VDDO = 1.5 V W 20 www.onsemi.com 3 NB3F8L3010C FUNCTION TABLES Table 3. CLOCK ENABLE (SELx) FUNCTION TABLE Table 5. DIFF IN/OUT TABLE (Diff or S.E.) SEL[1:0] Input Selected Input Clock Input Condition Output 00 CLK0/CLK0 CLK0/1; CLK0/1 = OPEN Logic LOW 01 CLK1/CLK1 CLK0/1; CLK0/1 = GND Undefined 10 Crystal Osc Input CLK0/1 = HIGH; CLK0/1 = LOW Logic HIGH 11 Crystal Osc Input CLK0/1 = LOW; CLK0/1 = HIGH Logic LOW Table 4. CLOCK OUTPUT ENABLE (OE) FUNCTION TABLE OE Input Q[9:0] Output 0 High Impedance 1 Outputs Enabled Table 6. CRYSTAL CHARACTERISTICS Parameter Min Mode of Oscillation Typ Max Unit 50 MHz 50 W Fundamental Frequency 10 Equivalent Series Resistance (ESR) Shunt Capacitance Drive Power 7 pF 100 mW Table 7. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 2) Flammability Rating >2 kV 200 V QFN32 Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 474 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 8. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition Rating Unit GND = 0 V 4.6 V VDD, VDDOn Positive Power Supply VI Input Voltage XTAL_IN Diff, SELx, OE Inputs VO Output Voltage – 0.5 v VO v VDDOn + 0.5 V TA Operating Temperature Range, Industrial −40 to +85 _C Tstg Storage Temperature Range −65 to +150 _C θJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 31 27 _C/W θJC Thermal Resistance (Junction−to−Case) (Note 3) 12 _C/W 0 v VI v VDD –0.5 v VI v VDD + 0.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). www.onsemi.com 4 NB3F8L3010C Table 9. POWER SUPPLY DC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V to 1.65 V); TA = −40°C to 85°C Parameter Symbol IDD IDDO Test Conditions VDD Power Supply Current OE = 0, no load 3.3 V ± 5%; VDDOn = 3.3 V ± 5% or 2.5 V ± 5% or 1.8 V ± 0.2 V or 1.5 V ± 0.15 V 2.5 V ± 5%; VDDOn = 2.5 V ± 5% or 1.8 V ± 0.2 V or 1.5 V ± 0.15 V VDDO Power Supply Current OE = 0, no load 3.3 V ± 5%; VDDOn = 3.3 V ± 5% or 2.5 V ± 5% or 1.8 V ± 0.2 V or 1.5 V ± 0.15 V 2.5 V ± 5%; VDDOn = 2.5 V ± 5% or 1.8 V ± 0.2 V or 1.5 V ± 0.15 V Min Typ Max Unit 30 50 mA 5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Table 10. DC CHARACTERISTICS TA = −40°C to 85°C Symbol Parameter Test Conditions Min VIH LVCMOS / LVTTL Input High Voltage (OE, SELx) VDD = 3.3 V ±5% VDD = 2.5 V ± 5% VIL LVCMOS / LVTTL Input Low Voltage (OE, SELx) VDD = 3.3 V ±5% VDD = 2.5 V ± 5% IIH Input High Current IIL Input Low Current VOH VOL OE, SELx, CLKx/CLKx OE, SELx CLKx CLKx Max Unit 2 1.7 VDD + 0.3 VDD + 0.3 V −0.3 −0.3 0.8 0.7 V VDD = VIN = 3.465 V VDD = VIN = 3.465 V or 2.625 V 150 150 VDD = 3.465 V; VIN = 0.0 V VDD = 3.465 V or 2.625 V VIN = 0.0 V VDD = 3.465 V or 2.625 V VIN = 0.0 V −5 −5 −150 VDDOn = 3.3 V ± 5% 2.6 VDDOn = 2.5 V ± 5% 1.8 VDDOn = 1.8 V ± 0.2 V 1.2 VDDOn = 1.5 V ± 0.15 V 0.9 Output High Voltage (Note 4) Output Low Voltage (Note 4) Typ mA mA V VDDOn = 3.3 V ± 5% or 2.5 V ± 5% 0.5 VDDOn = 1.8 V ± 0.2 V 0.4 VDDOn = 1.5 V ± 0.15 V 0.37 V VPP Peak−to−Peak Input Voltage VIL > −0.3 V CLKx/CLKx VDD = 3.3 V ±5% or VDD = 2.5 V ± 5% 0.15 1.3 V VIHCMR Input High Level Common Mode Range VCM = VIH; VIL > −0.3 V CLKx/CLKx VDD = 3.3 V ±5% or VDD = 2.5 V ± 5% 0.5 VDD − 0.85 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Outputs terminated with 50 W to VDDOn/2. See Parameter Measurement Information.. Table 11. AC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V to 1.65 V); TA = −40°C to 85°C Symbol fMAX Parameter Output Frequency Test Conditions Min Typ Max Unit Using External Crystal 10 50 MHz Using External Clock Source (Note 5) DC 200 MHz www.onsemi.com 5 NB3F8L3010C Table 11. AC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V to 1.65 V); TA = −40°C to 85°C Symbol Parameter tsk(o) Output Skew (Notes 6 and 7) tJITTERF Additive RMS Phase Jitter (Integrated 12 kHz * 20 MHz) (Note 8) Test Conditions Input clock from CLK0/CLK0 or CLK1/CLK1 Max Unit 10 55 ps VDDOn = 3.3 V ± 5% 0.03 VDDOn = 2.5 V ± 5% 0.03 0.03 VDDOn = 1.5 V ± 0.15 V 0.03 VDDOn = 3.3 V ± 5% 0.03 VDDOn = 2.5 V ± 5% 0.03 VDDOn = 1.8 V ± 0.2 V 0.03 VDDOn = 1.5 V ± 0.15 V 0.03 VDDOn = 3.3 V ± 5% 0.03 VDDOn = 2.5 V ± 5% 0.03 VDDOn = 1.8 V ± 0.2 V 0.03 VDDOn = 1.5 V ± 0.15 V 0.03 Input clock from crystal odc Typ VDDOn = 1.8 V ± 0.2 V External clock over drives crystal interface tR / tF Min Output Rise/Fall Time (20% and 80%) ps VDDOn = 3.3 V ± 5% 150 350 500 VDDOn = 2.5 V ± 5% 150 350 500 VDDOn = 1.8 V ± 0.2 V 150 350 600 VDDOn = 1.5 V ± 0.15 V 150 350 600 VDDOn = 3.3 V ± 5% 45 55 VDDOn = 2.5 V ± 5% 40 60 VDDOn = 1.8 V ± 0.2 V 40 60 VDDOn = 1.5 V ± 0.15 V 40 60 Output Duty Cycle ps % tEN Output Enable Time (Note 9) OE 4 cycles tDIS Output Disable Time (Note 9) OE 4 cycles MUX_ISOLATION MUX_ISOLATION 155.52 MHz 55 dB NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 5. XTAL_IN can be overdriven relative to a signal a crystal would provide. 6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOn/2. 7. This parameter is defined in accordance with JEDEC Standard 65. 8. See phase noise plot. 9. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information www.onsemi.com 6 NB3F8L3010C PARAMETER MEASUREMENT INFORMATION VDD = +1.65 V ±5% VDD = +1.25 V ±5% VDDOn = VDD = +1.65 V ±5% VDDOn = VDD = +1.25 V ±5% SCOPE Qx SCOPE Qx Z = 50 W LVCMOS Z = 50 W LVCMOS 50 W 50 W GND = +1.65 V ±5% GND = +1.25 V ±5% 3.3 V Core / 3.3 V Output Load AC Test Circuit 2.5 V Core / 2.5 V Output Load AC Test Circuit (Terminating to VDDOn/2) (Terminating to VDDOn/2) VDD = +2.05 V ±5% VDD = +2.4 V ±5% VDDOn = +1.25 V ±5% VDDOn = +0.9 V ±0.1 V SCOPE Qx SCOPE Qx Z = 50 W LVCMOS Z = 50 W LVCMOS 50 W 50 W GND = +1.25 V ±5% GND = +0.9 V ±0.1 V 3.3 V Core / 2.5 V Output Load AC Test Circuit 3.3 V Core / 1.8 V Output Load AC Test Circuit (Terminating to VDDOn/2) (Terminating to VDDOn/2) VDD = +2.55 V ±5% VDD = +1.6 V ±5% VDDOn = +0.75 V ±0.15 V VDDOn = +0.9 V ±0.1 V SCOPE Qx SCOPE Qx Z = 50 W LVCMOS Z = 50 W LVCMOS 50 W 50 W GND = +0.75 V ±0.15 V GND = +0.9 V ±0.1 V 3.3 V Core / 1.5 V Output Load AC Test Circuit 2.5 V Core / 1.8 V Output Load AC Test Circuit (Terminating to VDDOn/2) (Terminating to VDDOn/2) VDD = +1.75 V ±5% VDDOn = +0.75 V ±0.15 V SCOPE Qx Z = 50 W LVCMOS 50 W GND = +0.75 V ±0.5 V 2.5 V Core / 1.5 V Output Load AC Test Circuit (Terminating to VDDOn/2) Figure 3. Operational Supply and Termination Test Conditions www.onsemi.com 7 NB3F8L3010C PARAMETER MEASUREMENT INFORMATION VDDOn/2 VDD Qx CLK Xpoint VPP VCMR CLK VDDOn/2 Qv GND tsk(0) Differential Input Level Within Device Output Skew VDD VDD/2 OE tEN tDIS tPW Qx VOH tPeriod VDDOn/2 VOL VDDOn/2 Qx VDDOn/2 0V odc = (tPW / tPeriod) x 100% Output Enable /Disable (OE HIGH = Enabled) Output Duty Cycle / Pulse Width / Period 80% Qx 80% 20% tR Amplitud e (dB) Spectrum of Output Signal Qx 20% tF A0 MUX_ISOL = A0 - A1 MUX selects static input A1 Output Rise/Fall Time MUX selects active inpu t clock signal fc (Fundamental) Frequ ency (Hz) MUX Isolation Figure 4. Operational Waveforms and MUX Input Isolation Plot APPLICATION INFORMATION Recommendations for Unused LVCMOS Output Pins LVCMOS Control Pins Inputs: All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1 kW resistor can be used. CLK/CLK Inputs For applications not requiring the use of the differential input, both CLK and CLK can be left floating. Though not required, but for additional protection, a 1 kW resistor can be tied from CLK to ground. Power Supplies VDD is the power supply for the core and input circuitry. VDDOA and VDDOB are two separate positive power supplies for two banks of outputs: VDDOA pins 2 and 6 are connected internally for outputs Q0 − Q4. VDDOB pins 19 and 23 are connected internally for outputs Q5 − Q9. Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1 kW resistor can be tied from XTAL_IN to ground. LVCMOS Outputs A 33 W series terminating resistor may be used on each clock output if the trace is longer than 1 inch. www.onsemi.com 8 NB3F8L3010C Differential Input with Single−Ended Interconnect amplitude in half. Termination may be done by using Rs or by using R1 and R2. First, Rs = 0 and then R3 and R4 in parallel should equal the transmission line impedance. For most 50 W applications, R1 and R2 can be 100 W. The differential input can handle full rail LVCMOS signaling, but it is recommended that the amplitude be reduced. The datasheet specifies a differential amplitude which needs to be doubled for a single ended equivalent stimulus. VILmin cannot be less than −0.3 V and VIHmax cannot be more than VDD + 0.3 V. The datasheet specifications are characterized and guaranteed by using a differential signal. Refer to Figure 5 to interconnect a single−ended to a Differential Pair of inputs. The reference bias voltage VREF = VDD/2 is generated by the resistor divider of R3 and R4. Bypass capacitor (C1) can filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. Adjust R1 and R2 to common mode voltage of the signal input swing to preserve duty cycle. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination by R1 and R2 will attenuate the signal VDD Single Ended RO Driver VDD Rs R1 100 W VDD R3 1 kW Zo = 50 W Z0 = RO + Rs CLKx Differential In R2 100 W GND = 0.0 R4 1 kW GND = 0.0 CLKx C1 0.1 mF GND = 0.0 Figure 5. Differential Input with Single−ended Interconnect Crystal Input Interface CLOCK Overdriving the XTAL Interface The device has been characterized with 18 pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 6 below as 15 pF were determined using an 18 pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The XTAL_IN input can accept a single−ended LVCMOS signal through an AC coupling capacitor. A general LVCMOS interface diagram is shown in Figure 7 and a general LVPECL interface in Figure 8. The XTAL_OUT pin must be left floating. The maximum amplitude of the input signal should not exceed 2 V and the input edge rate can be as slow as 10 ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 W applications, R1 and R2 can be 100 W. This can also be accomplished by removing R1 and making R2 50 W. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Figure 6. Crystal Input Interface www.onsemi.com 9 NB3F8L3010C VDD LVMOS VDD R1 100 W Rs C1 0.1 mF XTAL_IN Zo = 50 W RO Z0 = RO + Rs R2 100 W GND = 0.0 V XTAL_OUT GND = 0.0 V Figure 7. General Diagram for LVCMOS Driver to XTAL Input Interface Use Rs or R1 / R2 VDD C1 0.1 mF XTAL_IN Zo = 50 W LVPECL Zo = 50 W XTAL_OUT 50 W 50 W GND = 0.0 V VTT = VDD − 2.0 V Figure 8. General Diagram for LVPECL Driver to XTAL Input Interface www.onsemi.com 10 NB3F8L3010C Differential Clock Input Interface input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The CLK / CLK accept LVDS, LVPECL, SSTL, HCSL differential signals. Signals must meet the VPP and VCMR input requirements. Figures 9 to 13 show interface examples for the CLK / CLK input with built−in 50 W terminations driven by the most common driver types. The VDD = +3.3 V VDD = +3.3 V VDD = +3.3 V Qx 125 W 125 W CLKx Zo = 50 W LVPECL CLKx Zo = 50 W Qx VDD = +3.3 V 84 W VDD = +3.3 V CLKx Qx Zo = 50 W LVPECL Differential In Qx 84 W GND = 0.0 V GND = 0.0 V CLKx Zo = 50 W 50 W GND = 0.0 V VDD = +3.3 V Figure 10. CLK / CLK Input Driven by 3.3 V LVPECL Driver (“Y” Parallel Termination) VDD = +3.3 V VDD = +3.3 V CLKx Zo = 50 W 50 W CLKx Zo = 50 W LVDS Differential In 100 W Zo = 50 W CLKx Differential In Qx 50 W GND = 0.0 V VDD = +3.3 V Qx CLKx Zo = 50 W HCSL Qx 33 W (Opt) GND = 0.0 V GND = 0.0 V Figure 9. CLK / CLK Input Driven by 3.3 V LVPECL Driver (Thevenin Parallel Termination) Qx 33 W (Opt) 50 W 50 W GND = 0.0 V Differential In GND = 0.0 V GND = 0.0 V GND = 0.0 V GND = 0.0 V Figure 11. CLK / CLK Input Driven by a 3.3 V HCSL Driver Figure 12. CLK / CLK Input Driven by 3.3 V LVDS Driver VDD = +2.5 V VDD = +3.3 V VDD = +2.5 V Qx 120 W 120 W CLKx Zo = 50 W SSTL CLKx Zo = 50 W Qx Differential In 120 W 120 W GND = 0.0 V GND = 0.0 V GND = 0.0 V Figure 13. CLK / CLK Input Driven by 2.5 V SSTL Driver www.onsemi.com 11 NB3F8L3010C VFQFN EPAD Thermal Release Path to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) is application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13 mils (0.30 to 0.33 mm) with 1 oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 14. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected Figure 14. Suggested Assembly for Exposed Pad Thermal Release Path – Cut−away View (not to scale) ORDERING INFORMATION Package Shipping† NB3F8L3010CMNG QFN32 (Pb−Free) 74 Units / Rail NB3F8L3010CMNR4G QFN32 (Pb−Free) 1000 / Tape & Reel NB3F8L3010CMNTWG QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 NB3F8L3010C PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488EW ISSUE O A D PIN ONE LOCATION NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B ÉÉ ÉÉ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C 0.15 C TOP VIEW A 0.10 C (A3) A1 0.08 C 9 32X L SEATING PLANE C SIDE VIEW NOTE 4 RECOMMENDED SOLDERING FOOTPRINT* K D2 5.30 3.35 17 8 1 25 e e/2 32X 0.63 1 E2 32 MILLIMETERS MAX MIN 0.80 1.00 −−− 0.05 0.20 REF 0.30 0.18 5.00 BSC 3.25 2.95 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 3.35 32X BOTTOM VIEW b 0.10 M C A B 0.05 M C NOTE 3 PACKAGE OUTLINE 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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