NB3H5150
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150 is a high performance Multi−Rate Clock generator
which simultaneously synthesizes up to four different frequencies
from a single PLL using a 25 MHz input reference. The reference
frequency can be provided by a crystal, LVCMOS/LVTTL, LVPECL,
HCSL or LVDS differential signals. The REFMODE pin will select
the reference source.
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 25 MHz, 33.33 MHz, 50 MHz,
100 MHz, 125 MHz, or 156.25 MHz and have ultra−low noise/jitter
performance of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
following integer and FRAC−N frequencies in pin−strap mode:
33.33 MHz, 66.66 MHz, 100 MHz, 106.25 MHz, 125 MHz,
133.33 MHz, 155.52 MHz, 156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used to load register
files into the NB3H5150 to program a variety of functions including
the frequencies and output levels of each output which can be
individually enabled and disabled.
Features
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MARKING
DIAGRAM*
1
1
32
A
WL
YY
WW
G
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of
this data sheet.
• Flexible Input Reference − 25 MHz Crystal, Oscillator,
• 1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
•
•
•
•
•
•
•
•
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Single−Ended or Differential Clock
Four Independent User−Programmable Clock
Frequencies from 25 MHz to 250 MHz
Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
Independent Power Supply for each Output Bank
300 ps max Output Rise and Fall Times, LVPECL
1000 ps max Output Rise and Fall Times, LVCMOS
300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
© Semiconductor Components Industries, LLC, 2016
December, 2018 − Rev. 4
•
•
•
155.52 MHz
I2C / SMBus Compatible Interface
−40°C to +85°C Ambient Operating Temperature
Zero ppm Multiplication Error
Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
32−Pin QFN, 5 mm x 5 mm
This is a Pb−Free Device
Applications
•
•
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1
Telecom
Networking
Ethernet
SONET
Publication Order Number:
NB3H5150/D
NB3H5150
VDD AVDD1
AVDD2
AVDD3
REF (I2C Mode)
CLK_XTAL1
CLK_XTAL2
VDDO1
PLL
XTAL
OSC
Integer N
DIV1
CLK1A
CLK1B
VDDO2
Integer N
DIV2
VDDO3
SDA
SCL/PD
MMC
CLK2A
CLK2B
Integer N
DIV3
Configuration Table
&
I2C Interface
VDDO4
Integer N or
Fractional N
DIV4
REFMODE
LDOs
FTM
FS4B
FS4A
FS2
FS3
LDO1 LDO2 LDO3 LDO4
FS1
CLK3A
CLK3B
29
28
VDDO1
LDO2
30
CLK1B
AVDD1
31
CLK1A
LDO1
32
AVDD2
CLK_XTAL1
Figure 1. Simplified Block Diagram of NB3H5150
27
26
25
Exposed Pad (EP)
CLK_XTAL2
1
24
FTM
REFMODE
2
23
CLK2B
SDA
3
22
CLK2A
SCL/PD
4
21
VDDO2
VDD
5
20
VDDO3
FS1
6
19
CLK3A
FS2
7
18
CLK3B
FS3
8
17
MMC
12
13
14
15
16
LDO3
CLK4A
CLK4B
VDDO4
FS4B
11
AVDD3
10
LDO4
9
FS4A
NB3H5150
Figure 2. 32−Lead QFN Pinout (Top View)
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2
CLK4A
CLK4B
NB3H5150
Table 1. PIN DESCRIPTION
Pin
Name
I/O
1
CLK_XTAL2
Crystal or
LVPECL/LVDS
Input
Description
2
REFMODE
LVTTL/LVCMOS
Input
Reference Input Select to either use a crystal, or overdrive with a single−ended or
differential input; see Table 2. Internal pull−down.
3
SDA
LVTTL/LVCMOS
Input
Serial Data Input for I2C/SMBus compatible; Defaults High when left open; internal pull−up.
5V tolerant.
4
SCL/PD
LVTTL/LVCMOS
Input
Serial Clock Input for I2C/SMBus compatible; Defaults High when left open; internal
pull−up.
SCL/PD is also a device power−down pin (when High) in pin−strap mode only. 5V tolerant.
5
VDD
Power
6
FS1
LVTTL/LVCMOS
Input
Frequency Select 1 for DIV1, CLK1A & CLK1B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
7
FS2
LVTTL/LVCMOS
Input
Frequency Select 2 for DIV2, CLK2A & CLK2B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
8
FS3
LVTTL/LVCMOS
Input
Frequency Select 3 for DIV3, CLK3A, & CLK3B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
9
FS4A
LVTTL/LVCMOS
Input
Frequency Select 4A for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
10
FS4B
LVTTL/LVCMOS
Input
Frequency Select 4B for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
Crystal Output or Differential Clock Input (complementary); If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
3.3 V / 2.5 V Positive Supply Voltage for the Inputs and Core
11
LDO4
Power
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
12
AVDD3
Power
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD3 = VDD.
13
LDO3
Power
1.8V LDO − Install Power Conditioning Bypass Capacitor to Ground
14
CLK4A
Output
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 4
Output
15
CLK4B
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 4 Output
16
VDDO4
Power
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK4A/4B Outputs
17
MMC
LVTTL/LVCMOS
Input
18
CLK3B
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 3 Output
19
CLK3A
Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 3
Output
20
VDDO3
Power
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK3A/3B Outputs
21
VDDO2
Power
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK2A/2B Outputs
22
CLK2A
Output
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 2
Output
23
CLK2B
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 2 Output
24
FTM
25
VDDO1
Power
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK1A/1B Outputs
26
CLK1B
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 1 Output
27
CLK1A
Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 1
Output
28
AVDD2
Power
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD2 = VDD.
29
LDO2
Power
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
30
AVDD1
Power
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD1 = VDD.
31
LDO1
Power
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
Mix Mode Control Pin for use as a combination of FSn settings and I2C setting for the
CLK(n) outputs in the I2C mode; see Table 5. No logic level default; use a RPull−up resistor
for High or a RPull−down resistor for Low.
Factory Test Mode. Must connect this pin to Ground.
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NB3H5150
Table 1. PIN DESCRIPTION
Pin
Name
I/O
32
CLK_XTAL1
Crystal or
LVTTL/LVCMOS
or LVPECL/LVDS
Input
EP
Exposed Pad
Ground
Description
Crystal Input or Single−Ended or Differential Clock Input; If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
Ground – Negative Power Supply is connected via the Exposed Pad .
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat
sinking conduit. The pad is electrically connected to the die,carries all power supply return
currents and must be electrically connected to GND.
1. All VDD, AVDDn, VDDOn, EP (GND) pins must be externally connected to a power supply for proper operation. VDD and AVDDn must all
be at the same voltage.
NB3H5150 BASIC OPERATION
The I2C interface pins, SCL and SDA, are used to load
register files into the NB3H5150.
These register files will configure the internal registers to
achieve an expanded selection of output frequencies and
levels combinations for each of the four output blocks.
Subsequent changes in the registers can then be performed
with another register file to modify any of the output
frequencies or output modes.
Introduction
The NB3H5150 is a Multi−Rate Clock Generator. The
clock reference for the PLL can be either a 25 MHz crystal,
single−ended LVCMOS or LVTTL signal or a differential
LVPECL, LVDS or HCSL signal.
There are two modes of operation for the NB3H5150,
Pin−Strap and I2C.
In the Pin−Strap Mode, the user can select any of the
defined output frequencies for each of the four output banks
as specified in Tables 3 and 4 via the three−level Frequency
Select pins: FS1, FS2, FS3, FS4A and FS4B.
In the I2C mode, the user can select one of the approved
register files. Each register file is an expanded selection of
output frequencies and level combinations, output
enable/disable and bypass mode functions.
OE, Output Enable
An OE, Output Enable/Disable function is available only
in the I2C mode by loading a register file, such that any
individual output bank can be enabled or disabled. In
LVCMOS modes outputs will disable LOW for CLKnA and
CLKnB, while the LVPECL mode outputs will disable
CLKnA = Low and CLKnB = High.
CLKnA & CLKnB − Output Frequency and Output
Level Selection
Mixed Mode Control (MMC)
In the I2C mode, the Mixed Mode Control (MMC) pin is
used for a combination of FSn settings and I2C settings to
control the CLK(n) outputs’ function as defined in Table 5.
There are four output banks: CLK1A&B, CLK2A&B and
CLK3A&B are integer only divider outputs, whereas
CLK4A&B can be set or programmed as an integer or
fractional divider.
The output levels for each output bank can be LVPECL
(differential) or LVCMOS (two single−ended). Output
Enable / Disable functions are available in I2C only.
CLK1, 2, 3 and 4 outputs are not phase−aligned, in PLL
or PLL bypass modes.
REFMODE – Select a Crystal or External Clock Input
Interface (See Table 2)
The REFMODE pin will select the reference input for the
CLK_XTAL1 and CLK_XTAL2 pins to use either a crystal,
an overdriven single−ended or differential input.
When using a crystal, set the REFMODE pin to a LOW.
The CLK_XTAL1 and CLK_XTAL2 input pins will accept
a 25 MHz crystal.
When using a direct−coupled differential input, set the
REFMODE pin to a HIGH.
Power−On Output Default
Upon power−up, all four outputs will be forced to and held
at static LVPECL levels (CLKnA = Low, CLKnB = High)
until the PLL is stable. The PLL will be stable before any of
the output Clocks, CLKnx, are enabled.
SDA & SCL/PD - Serial Data Interface – I2C
The NB3H5150 incorporates a two−wire Serial Data
Interface to expand the flexibility and function of the
NB3H5150 clock generator.
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NB3H5150
When REFMODE is HIGH, the CLK_XTAL1 and
CLK_XTAL2 differential input pins have internal AC
coupling capacitors selected with self−bias circuity for the
differential input buffer. This differential buffer will directly
accept any differential signal including LVPECL, LVDS,
HCSL or CML. Drive the CLK_XTAL1 pin with the true
signal and the CLK_XTAL2 pin with the complementary
signal.
When overdriving the CLK_XTAL1 input pin with a
single−ended signal set REFMODE to a HIGH, and connect
CLK_XTAL2 to Ground. The input has internal AC
coupling capacitor with self−bias circuitry.
Table 2. CRYSTAL INPUT INTERFACE AND REFMODE TRUTH TABLE
Input Mode Crystal/External Clock
REFMODE
CLK_XTAL1
CLKb_XTAL2
Crystal
LOW
Use a Crystal
Use a Crystal
Any Differential Input
HIGH
Overdrive with True Input
Overdrive with Complementary Input
Single−Ended Input
HIGH
Overdrive
Connect to Ground
LVCMOS Outputs
EP Exposed Pad
LVCMOS outputs are powered with VDDOn = 3.3 V,
2.5 V or 1.8 V
A 33 series terminating resistor may be used on each
clock output if the metal trace is longer than one inch.
Any unused LVCMOS output can be left floating, but
there should be no metal trace attached to the package pin.
The exposed pad on the bottom side of the package must
be connected to Ground.
LDO Pins
The NB3H5150 has integrated low noise 1.8 V
Low−Drop−Out (LDO) voltage regulators which provide
power internal to the NB3H5150.
The LDOs require decoupling capacitors in the range of
1 F to 10 F for compensation and high frequency PSR.
When powered−down, the device turns off the LDOs and
enters a low power shutdown mode consuming less than
1 mA.
LVPECL Differential Outputs
The differential LVPECL outputs are powered with
VDDO = 3.3 V or 2.5 V and must be properly loaded. See
Figure 10.
Any unused differential output pair should either be left
floating or terminated.
FTM
This is a Factory Test Mode pin and must be connected to
the Ground of the application for proper operation.
REF Out
In the PLL bypass mode available via I2C, the input
reference frequency can be routed to CLK1A and CLK1B as
phase aligned LVCMOS or differential LVPECL outputs
with the same frequency. The output frequency and duty
cycle equals the input frequency and duty cycle.
PIN−STRAP / FSn Frequency Select MODE: (see
Tables 3 and 4)
The NB3H5150 can be configured to operate in pin−strap
mode where the control pins FSnA/B can be set to generate
the necessary clock outputs of the device.
Prerequisites:
♦ SDA and SCL/PD must be Low at all times while in
pin−strap mode to enable FS control. If SDA ever
goes High, pin−strap is exited and the only way to
go back is to power cycle the device.
♦ Mixed Mode Control pin (MMC) level will be
IGNORED.
Power Supplies
The NB3H5150 has several power supply pins:
• VDD is the supply voltage for the input and digital core
circuitry.
• AVDD1, AVDD2 and AVDD3 powers the core analog
circuits. VDD = AVDD1 = AVDD2 = AVDD3.
• VDDO1, VDDO2, VDDO3 and VDDO4 are individual
power supplies for each of the four CLKnA/B output
banks.
Upon power−up, all four VDDOn pins must be connected
to a power supply, even if only one output is being used.
Any combination of VDD and VDDOn power supply
voltages is allowed.
A power supply filtering scheme in Figure 8 is
recommended for best device performance.
When all VDD, AVDDn and VDDOn pins reach their
minimum voltage per Table 8, the NB3H5150 will operate
at the proper output frequencies.
Sequencing:
1. Upon device power−up (assuming SCL is LOW)
a. All four CLK(n) frequency and output type
selections will be pre−loaded according to the
FS pin settings, but all four outputs will be held
at static LVPECL levels (CLKnA = Low,
CLKnB = High) until the PLL has become
stable.
b. After the PLL is stable, all CLK(n) output type
selections (i.e. LVPECL or LVCMOS) will
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NB3H5150
be aware that subsequent change to the FS pin
should only change frequency, and not output type.
3. Power off/on cycle will repeat the entire sequence
4. Power Down
To initiate the Power−Down mode, the SDA pin
must be LOW and remain LOW. If the SCL/PD
pin is taken HIGH at any time, the device enters a
complete power−down mode with a current
consumption of less than 1 mA for the entire
device. When SCL/PD is subsequently taken
LOW, the device will function as though power
were removed and re−applied. That is, sequencing
will begin at #1.
Power−down is also available via I2C with a
register file.
become effective and will begin to output the
selected frequencies.
2. Subsequent changes to any FS pin(s) will cause
the associated CLK(n) output(s) to momentarily
go to static levels, and then to resume at the new
frequency; CLK(n) will follow the FS(n) pin
programmable Tables 3 and 4 for output
frequencies and interface levels.
Note that in changing from LVPECL to LVCMOS
(or vice−versa), output logic levels cannot be
guaranteed. This is because the receiver inputs are
not likely to change in a given application, and the
LVPECL output loading in the application will
also not change. It is logical to presume that the
output type will be predetermined and fixed.
Therefore, in a system/application, the user should
FS(n) Pin Programmable Selection of Output Frequencies and Levels
Table 3. NB3H5150 − CLK1A:3A & CLK1B:3B OUTPUT FREQUENCY SELECT
TABLE WITH 25 MHz CRYSTAL
Logic Level
FS1 (CLK1)
(MHz)
FS2 (CLK2)
(MHz)
FS3 (CLK3)
(MHz)
Low
50.00 (LVCMOS)
156.25 (LVPECL)
156.25 (LVPECL)
Mid / Float*
33.33 (LVCMOS)
25.00 (LVPECL)
125.00 (LVCMOS)
High
25.00 (LVCMOS)
125.00 (LVPECL)
100.00 (LVPECL)
*(Default)
Table 4. NB3H5150 − CLK4A & CLK4B OUTPUT FREQUENCY SELECT TRUTH
TABLE (MHz) WITH 25 MHz CRYSTAL*
FS4A
FS4B
CLK4 (MHz)
Divider Type
Low
Low
33.33 (LVCMOS)
Integer
Low
Mid / Float
66.66 (LVCMOS)
Fractional
Low
High
133.33 (LVCMOS)
Fractional
Mid / Float
Low
155.52 (LVPECL)
Fractional
Mid / Float*
Mid / Float*
156.25 (LVPECL)
Integer**
Mid / Float
High
125.00 (LVPECL)
Integer**
High
Low
106.25 (LVPECL)
Fractional
High
Mid / Float
100.00 (LVCMOS)
Integer**
High
High
161.1328 (LVPECL)
Fractional
*(Default)
**These frequency selections are not recommended for use. They have potential to start up at incorrect frequency (2 or 2.5X desired frequency). Multiple power cycles may be required to
achieve the correct frequency.
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NB3H5150
I2C MODE: (see Table 5)
respective FS1, FS2 and FS3 pin selection in
Table 3.
CLK4A/4B outputs remain at Static
LVPECL Levels.
After power up, changes to all pins will be
ignored except the SDA and SCL inputs.
iv. The FS4A and FS4B pins set the bus address
when MMC pin is LOW (see Table 5, I2C
Device Address Table).
c. The I2C interface can now be used to load
register files into the NB3H5150. In I2C Mode,
configuration of Output Enables, output
frequency, output levels of each output, specific
block power−down control, bypass mode, etc.
are all possible.
d. Any outputs which were held in static level
mode (described above) will be released for
operation.
CLK(n) outputs will be active at the programmed
frequencies and levels.
CLK(n) outputs will react to any subsequent changes to the
I2C bus.
If any output channel is not programmed, then output is
loaded from FSn pins.
A Power Cycle will clear all previous register information
and I2C mode will repeat to number 1 in the power up
sequence.
To simplify device configuration, ON Semiconductor
provides desktop software, that can be downloaded from
http://www.onsemi.com/pub/Collateral/NB3H5150_GUI.
ZIP which will operate in conjunction with the NB3H5150
evaluation board (EVB). The NB3H5150 GUI manual can
also be found on the web site.
When the software is connected to an NB3H5150 EVB,
it can control the selection of numerous clock output
frequencies for each of the four CLK outputs and the output
type as well as Output Enable/Disable.
Some features that are not available in pin−strap mode can
be obtained in I2C mode, such as Output Enable/Disable,
By−Pass mode and Power−Down. In addition, output
frequency and output levels can also be I2C controlled.
The NB3H5150 I2C Programming Guide can be found on
the NB3H5150 web site. This application note provides
details on configuring the NB3H5150 by writing to registers
in the NB3H5150 with approved register files through the
I2C/SMBus interface.
http://www.onsemi.com/pub/Collateral/NB3H5150%20I2
C%20PROGRAMMING%20GUIDE%20%20..PDF
Register Files can be generated by the factory upon
request.
Prerequisites:
• SDA and SCL must be connected to I2C SMBus
• SDA must be logic High.
1. Upon device power−up.
a. All four frequencies and output type selections
will be preloaded according to the FSn pin
settings, but all four outputs will be held at
static LVPECL levels until the PLL has become
stable.
NOTE: After power up, changes to FS pins
will be blocked from controlling device
operation.
b. Once the PLL is stable, the Mixed Mode
Control pin (MMC) is checked:
i. If MMC is LOW, all CLK(n) outputs will
remain at static LVPECL levels.
ii. If MMC is HIGH and FS4A is LOW, CLK1,
CLK2, and CLK3 outputs will remain at
static LVPECL levels.
CLK4A/4B output frequency and output
levels will become active after PLL
stabilization time according to FS4A and
FS4B pin selection in Table 4.
After power up, changes to all pins will be
ignored.
iii. If MMC is HIGH and FS4A MID or HIGH,
CLK1, CLK2, and CLK3 output frequency
and type will become active after PLL
stabilization time according to their
I2C Programmable Selection of Output Frequency and
Level
Each register file can be loaded from GUI into the demo
board, or loaded into the I2C port of the device.
Table 5. SDA, SCL AND MMC CONTROL PINS FOR OUTPUT FUNCTION
Outputs (Note 2)
Mode
SDA
SCL/PD
MMC
Comments
CLK1, CLK2,
CLK3
Pin−Strap FS Mode
L
L
X
Normal Operation
Toggle per Table 3
Toggle per Table 4
Power−Down
L
H
X
Off
Off
CLK4
2. All outputs are static until after the PLL is stable.
3. Any changes to the device configuration after power−up are made by reading and writing to registers through the I2C interface.
4. Don’t care state unless device address is matched by controller address.
X = don’t care
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NB3H5150
Table 5. SDA, SCL AND MMC CONTROL PINS FOR OUTPUT FUNCTION
Outputs (Note 2)
CLK1, CLK2,
CLK3
CLK4
Active Per I2C Map
Active Per I2C Map
L
Static LVPECL
Logic Levels
Static LVPECL
Logic Levels
H
Note 4
H
FS4A = L
Static LVPECL
Logic Levels
Active per Table 4
H
Note 4
H
FS4A =
M or H
Active per Table 3
Static LVPECL
Logic Levels
Mode
SDA
SCL/PD
MMC
Comments
I2C
(Note 3)
Dynamic
Dynamic
X
I2C Mode Is Active After
Mixed Mode Power−Up
Sequence
H
Note 4
H
Note 4
H
Note 4
H
Note 4
Mixed Mode
2. All outputs are static until after the PLL is stable.
3. Any changes to the device configuration after power−up are made by reading and writing to registers through the I2C interface.
4. Don’t care state unless device address is matched by controller address.
X = don’t care
Table 6. ATTRIBUTES
ESD Protection
Characteristics
Value
Human Body Model
Machine Model
Charge Device Model
> 2 kV
> 150 V
> 500 V
Moisture Sensitivity (Note 5)
32−QFN
Level 1
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
245, 894
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, see Application Note AND8003/D.
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NB3H5150
Table 7. MAXIMUM RATINGS
Symbol
Condition
Rating
Unit
Positive Power Supply – Core
GND = 0 V
3.63
V
AVDDn
Positive Power Supply – Analog
GND = 0 V
3.63
V
VDDOn
Positive Power Supply – Outputs
GND = 0 V
3.63
V
Positive Input/Output Voltage
GND = 0 V
−0.5 to VDD
+0.5
V
VI
Positive Input Voltage SDA and SCL
GND = 0 V
5.5
V
TA
Operating Temperature Range
QFN−32
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
VDD
VIO
Parameter
θJ
Maximum Junction Temperature
θJA
Thermal Resistance (Junction−to−Ambient) (Note 6)
QFN−32
QFN−32
125
°C
31
27
°C/W
°C/W
θJC
Thermal Resistance (Junction−to−Case) (Note 6)
QFN−32
12
°C/W
TJ
Tsol
Maximum Junction Temperature
125
°C
Wave Solder Pb−Free, 10 sec
265
°C
0 lfpm
500 lfpm
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. JEDEC standard multilayer board – 2S2P (2 signal, 2 power).
Table 8. DC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDOn = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C
Characteristic
Symbol
Min
Typ
Max
Unit
3.135
2.375
3.135
2.375
1.71
3.3
2.5
3.3
2.5
1.8
3.465
2.625
3.465
2.625
1.89
V
60
75
55
70
75
90
70
85
POWER SUPPLY / CURRENT (Note 12)
VDD/AVDDn
VDDOn
Core Power Supply
Output Power Supply
VDD = AVDDn = 3.3 V
VDD = AVDDn = 2.5 V
VDDOn = 3.3 V
VDDOn = 2.5 V
VDDOn = 1.8 V (LVCMOS only)
IDD/IADDn
Core and Input Power Supply Current for VDD and AVDDn
VDD = 3.3 V
CLK4 Integer
CLK4 Frac−N
CLK4 Integer
VDD = 2.5 V
CLK4 Frac−N
IDDOn
Output Buffer Power Supply Current for VDDOn
Incremental IDDO Current by One Output Bank and Output Type
LVPECL − One differential LVPECL output pair (CLKnA & CLKnB)
Frequency Independent
VDDO = 3.3 V
VDDO = 2.5 V
LVCMOS − Two LVCMOS outputs (CLKnA & CLKnB)
IDDPWRDN
mA
mA
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
Power Down Current SCL/PD = High
40
40
50
50
20
17
15
25
23
21
100
A
LVPECL OUTPUTS (Note 7 and 8) VDDOn = 3.3 V ±5% or 2.5 V ±5%; See Figure 10
VOH
Output HIGH Voltage
VDDO − 1.200
VDDO − 0.895
V
VOL
Output LOW Voltage
VDDO − 2.000
VDDO − 1.600
V
900
mV
VSWING
VOUT PK−PK Voltage Swing
550
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720
NB3H5150
Table 8. DC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDOn = 3.3 V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C
Symbol
Characteristic
Min
Typ
Max
Unit
LVCMOS OUTPUT; See Figure 12
VOH
Output HIGH Voltage IOH = 12 mA
VDDO – 0.5
VDDO
V
VOL
Output LOW Voltage IOL = 12 mA
GND
0.5
V
ROUT
Output Impedance
15
CRYSTAL INPUT DRIVEN SINGLE−ENDED (REFMODE = 1) (see Figure 3 and 5) (Note 9)
VIHSE
CLK_XTAL1 Single−Ended Input HIGH Voltage
200
VDD
mV
VILSE
CLK_XTAL1 Single−Ended Input LOW Voltage
GND
VIHSE − 200
mV
Input Threshold Reference Voltage Range
100
VDD − 100
mV
Single−Ended Input Voltage (VIH – VIL)
200
VDD
mV
Vth
VISE
CRYSTAL INPUTS DRIVEN DIFFERENTIALLY (REFMODE = 1) (see Figure 4 and 6) (Note 11)
VIHD
Differential Input HIGH Voltage
100
VDD
mV
VILD
Differential Input LOW Voltage
GND
VIHD – 100
mV
VID
Differential Input Voltage (VIHD – VILD)
100
VDD
mV
Input Common Mode Range (Differential Configuration)
(Note 10) (Figure 8)
50
VDD − 50
mV
IIH
Input HIGH Current CLK_XTAL1 and CLKb_XTAL2
−10
10
A
IIL
Input LOW Current CLK_XTAL1 & CLKb_XTAL2
−10
10
A
VCMR
LVCMOS − CONTROL AND SDA & SCL/PD INPUTS
VIH
Input HIGH Voltage for MMC & REFMODE Pins
VDD = 3.3 V
VDD = 2.5 V
2.1
1.75
VDD
V
VIH
Input HIGH Voltage for SDA & SCL/PD Pins
VDD = 3.3 V
VDD = 2.5 V
2.1
1.75
5.5
V
VIL
Input LOW Voltage for Control Pins and SDA & SCL/PD VDD = 3.3 V
VDD = 2.5 V
GND
0.7
0.7
V
IIH
Input HIGH Current
−150
150
A
IIL
Input LOW Current
−150
150
A
VIHtri
VIMtri
Tri−Level Input High Voltage (FSn pins)
VDD x 75%
VDD
VDD = 3.3 V
2.48
VDD
VDD = 2.5 V
1.88
VDD
VDD x 40%
VDD x 60%
1.32
1.98
Tri−Level Input Med Voltage (FSn pins)
VDD = 3.3 V
VDD = 2.5 V
VILtri
1.00
1.67
GND
VDD x 25%
VDD = 3.3 V
0.00
0.83
VDD = 2.5 V
0.00
0.63
Tri−Level Input Low Voltage (FSn pins)
V
V
V
V
RIN
Input Impedance
10
k
CIN
Input Capacitance − Crystal pins; REFMODE = H
2
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. LVPECL Outputs loaded with 50 to VDDO – 2 V for proper operation.
8. LVPECL Output parameters vary 1:1 with VDDO.
9. VIH, VIL, Vth, and VISE parameters must be complied with simultaneously.
10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VDD.
11. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
12. IDD / VDD is independent of IDDOn/ VDDOn
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NB3H5150
Table 9. AC CHARACTERISTICS
VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDO = 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C (Note 13)
Characteristic
Symbol
fCLKIN
fINBP
External Clock / Crystal Input Frequency − PLL Mode
External Clock Input Frequency – PLL Bypass Mode
fin = fout
I2C
Mode;
fCLK1,2,3
CLK1, CLK2, CLK3 Typical Output Clock Frequencies; fin = 25 MHz
fCLK4
CLK4 Outputs Typical Output Clock Frequencies; fin = 25 MHz
Resolution of 1 Hz
Integer
Frac−N
fSDA/SCL
tPWSCL
Min
Typ
Max
Unit
−1000 ppm
25
+1000 ppm
MHz
50
MHz
1
Serial Data and Clock Rates
Serial Clock Pulse Width
100k
bps
ns
100
tDC
Output Clock Duty Cycle (Crystal or Reference Duty Cycle = 50%)
PLL Mode;
