NB3L208KMNG

NB3L208K 2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer Description The NB3L208K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides eight identical copies operating up to 350 MHz. The NB3L208K is optimized for ultra−low phase noise, propagation delay variation and low output–to–output skew, and is DB800H compliant. As such, system designers can take advantage of the NB3L208K’s performance to distribute low skew clocks across the backplane or the motherboard making it ideal for Clock and Data distribution applications such as PCI Express, FBDIMM, Networking, Mobile Computing, Gigabit Ethernet, etc. Output drive current is set by connecting a 475 W resistor from IREF (Pin 27) to GND per Figure 11. Outputs can also interface to LVDS receivers when terminated per Figure 12. Features www.onsemi.com MARKING DIAGRAM 1 1 32 QFN32 G SUFFIX CASE 488AM A WL YY WW G NB3L 208K AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION ©Maximum Input Clock Frequency > 350 MHz ©2.5 V © 5% / 3.3 V © 10% Supply Voltage Operation ©8 HCSL Outputs ©DB800H Compliant ©PCIe Gen 3, Gen 4 Compliant ©Individual OE Control Pin for Each Bank of 2 Outputs ©100 ps Max Output−to−Output Skew Performance ©1 ns Typical Propagation Delay ©500 ps Typical Rise and Fall Times ©80 fs Maximum Additive RMS Phase Jitter ©−40© C to +85© C Ambient Operating Temperature ©QFN 32−pin Package, 5 mm x 5 mm ©These Devices are Pb−Free and are RoHS Compliant See detailed ordering and shipping information page 12 of this data sheet. Typical Applications ©PCI Express ©FBDIMM ©Mobile Computing ©Networking ©Gigabit Ethernet © Semiconductor Components Industries, LLC, 2015 October, 2017 − Rev. 3 1 Publication Order Number: NB3L208K/D NB3L208K VDD VDD_O OE#_[1:0] DIF_0 DIF_0# DIF_1 DIF_1# OE#_[3:2] DIF_2 DIF_2 # DIF_3 DIF_3 # CLK_IN CLK_IN# OE#_[5:4] DIF_4 DIF_4# DIF_5 DIF_5# OE#_[7:6] DIF_6 DIF_6 # DIF_7 DIF_7# IREF RREF VDD_0 25 OE#_[1:0] 28 GND_0 OE#_[3:2] 29 IREF OE#_[5:4] 30 26 GND_0 31 27 VDD_0 32 Figure 1. Simplified Block Diagram Exposed Pad (EP) DIF_0 1 24 DIF_4 DIF_0# 2 23 DIF_4# DIF_1 3 22 DIF_5 DIF_1# 4 21 DIF_5# DIF_2 5 20 DIF_6 DIF_2# 6 19 DIF_6# DIF_3 7 18 DIF_7 DIF_3# 8 17 DIF_7# 10 11 12 13 14 15 16 OE#_[7:6] CLK_IN CLK_IN# GND VDD GND_0 VDD_0 VDD_0 9 NB3L208K Figure 2. 32−Pin QFN Pinout (Top View) www.onsemi.com 2 NB3L208K Table 1. PIN DESCRIPTION Pin Number Pin Name I/O 1 DIF_0 O, DIF 0.7 V Differential True Output 2 DIF_0# O, DIF 0.7 V Differential Complementary Output 3 DIF_1 O, DIF 0.7 V Differential True Output 4 DIF_1# O, DIF 0.7 V Differential Complementary Output 5 DIF_2 O, DIF 0.7 V Differential True Output 6 DIF_2# O, DIF 0.7 V Differential Complementary Output 7 DIF_3 O, DIF 0.7 V Differential True Output 8 DIF_3# O, DIF 0.7 V Differential Complementary Output 9 VDD_O Power Power supply for outputs 10 OE#_[7:6] I, SE LVTTL / LVCMOS active low input for enabling output pair DIF_6/6# & DIF_7/7#. 0 enables outputs, 1 disables outputs. Internal pull down. 11 CLK_IN I, DIF Differential True input 12 CLK_IN# I, DIF Differential Complementary input 13 GND Power Ground 14 VDD Power Core power supply 15 GND_O Power Ground for outputs 16 VDD_O O, DIF Power supply for outputs 17 DIF_7# O, DIF 0.7 V Differential Complementary Output 18 DIF_7 O, DIF 0.7 V Differential True Output 19 DIF_6# O, DIF 0.7 V Differential Complementary Output 20 DIF_6 O, DIF 0.7 V Differential True Output 21 DIF_5# O, DIF 0.7 V Differential Complementary Output 22 DIF_5 O, DIF 0.7 V Differential True Output 23 DIF_4# O, DIF 0.7 V Differential Complementary Output 24 DIF_4 O, DIF 0.7 V Differential True Output 25 VDD_O Power Power supply for outputs 26 GND_O Power Ground for outputs 27 IREF I 28 OE#_[1:0] I, SE LVTTL / LVCMOS active low input for enabling output pair DIF_0/0# & DIF_1/1#. 0 enables outputs, 1 disables outputs. Internal pull down. 29 OE#_[3:2] I, SE LVTTL / LVCMOS active low input for enabling output pair DIF_2/2# & DIF_3/3#. 0 enables outputs, 1 disables outputs. Internal pull down. 30 OE#_[5:4] I, SE LVTTL / LVCMOS active low input for enabling output pair DIF_4/4# & DIF_5/5#. 0 enables outputs, 1 disables outputs. Internal pull down. 31 GND_O Power Ground for outputs 32 VDD_O Power Power supply for outputs EP Exposed Pad Thermal Description A precision resistor is attached to this pin to set the differential output current. Use RREF = 475 W, 1% for 100 W trace, with 50 W termination. Use RREF = 412 W, 1% for 85 W trace, with 43 W termination. The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. www.onsemi.com 3 NB3L208K Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model > 2000 V RPD − Pull−down Resistor 50 kW Moisture Sensitivity (Note 1) QFN−32 Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 1344 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. ABSOLUTE MAXIMUM RATINGS Symbol VDD VDD_O Parameter Min Max Unit Core Supply Voltage − 4.6 V I/O Supply Voltage − 4.6 V VIH Input High Voltage (Note 2) VIL Input Low Voltage IOUT Maximum Output Current − 4.6 V −0.5 − V − 24 mA TA Operating Temperature Range −40 to +85 © C Tstg Storage Temperature Range −65 to +150 © C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) qJC Tsol 0 lfpm 500 lfpm 31 27 © C/W Thermal Resistance (Junction−to−Case) (Note 3) 12 © C/W Wave Solder 265 © C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Maximum VIH is not to exceed maximum VDD. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 4 NB3L208K Table 4. DC CHARACTERISTICS VDD = VDD_O = 3.3 V © 10% or 2.5 V © 5%, TA = −40© C to 85© C Symbol Characteristics Min Typ Max Unit VDD = 3.3 V © 10% 5% VDD = 2.5 V © 2.970 2.375 3.3 2.5 3.630 2.625 V VDD_O = 3.3 V © 10% VDD_O = 2.5 V © 5% 2.970 2.375 3.3 2.5 3.630 2.625 V 170 210 mA Standby Current, all OE pins de−asserted with inputs @ 350 MHz 50 65 mA Incremental output current for additional pair of outputs; One OE Enabled 30 45 mA 80 110 mA 850 mV POWER SUPPLY CURRENT VDD VDD_O Core Power Supply Voltage Output Power Supply Voltage IDD + IDD_O Total Power Supply Current (all outputs active @ 350 MHz, RREF = 412 W, RL = 43 W) Istdby lincr Istdby + lincr Standby Current plus incremental current for one additional pair of differential outputs; One OE Enabled @ 350 MHz HCSL OUTPUTS (Notes 4, 5) VOH Output HIGH Voltage 660 VOL Output LOW Voltage −150 Output Swing (Single−Ended) Output Swing (Differential) 400 800 VOUT mV 750 1500 mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 4 and 6) VIH CLK_IN/CLK_IN# Single-ended Input HIGH Voltage 0.5 VDD V VIL CLK_IN/CLK_IN# Single-ended Input LOW Voltage GND VIH − 0.3 V Vth Input Threshold Reference Voltage Range (Note 7) 0.25 VDD − 1.0 V Single-ended Input Voltage (VIH − VIL) 0.5 VDD V VISE DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 8) (Figures 5 and 7) VIHD Differential Input HIGH Voltage 0.5 VDD − 0.85 V VILD Differential Input LOW Voltage 0 VIHD − 0.25 V VID Differential Input Voltage (VIHD − VILD) 0.25 1.3 V Input Common Mode Range (Differential Configuration) (Note 9) (Figure 8) 0.5 VDD − 0.85 V Input Leakage Current 0 < VIN < VDD (Note 10) −5 5 mA VIHCMR IIL LVTTL / LVCMOS INPUTS (OE#_x) VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage −0.3 0.8 V IIL Input LOW Current (VIN = GND) −10 +10 mA IIH Input HIGH Current (VIN = VDD) 100 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Test configuration is RS = 33.2 W, RL = 49.9, CL = 2 pF, RREF = 475 W. 5. Measurement taken from Single−Ended waveform unless specified otherwise. 6. VIH, VIL, Vth and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. The common mode voltage is defined as VIH. 10. Does not include inputs with pulldown resistors. www.onsemi.com 5 NB3L208K Table 5. AC TIMING CHARACTERISTICS VDD = VDD_O = 3.3 V © 10% or 2.5 V © 5%, TA = −40© C to 85© C (Note 15) Symbol Fmax Trise/Tfall Output Slew Rate DTrise/DTfall Slew Rate Matching Characteristics Min Maximum Input Frequency 350 Rise Time / Fall Time (Notes 13, 17 and 33) (Figure 13) 175 Output Slew Rate (Notes 13 and 17) 0.5 Typ Max 500 Rise/Fall Time Variation (Notes 17 and 26) (Notes 18, 27 and 28) 700 ps 2.0 V/ns 125 20% ps mV Vhigh Voltage High (Notes 17, and 20) (Figure 14) 660 700 850 Vlow Voltage Low (Notes 17, and 21) (Figure 14) −150 0 +150 Input Slew Rate (Note 29 and 32) 0.35 Vcross absolute Absolute Crossing Point Voltages (Notes 12, 17 and 24) Relative Crossing Point Voltages can be calculated (Notes 16, 17 and 24) (Figure 16) 250 Total DVcross Duty Cycle mV V/ns Total Variation of Vcross Over All Edges (Notes 17 and 25) (Note 18) (Figure 15) Unit MHz 45 550 mV 140 mV 55 % Vovs Maximum Voltage (Overshoot) (Notes 17 and 22) (Figure 14) Vhigh + 0.3 V Vuds Maximum Voltage (Undershoot) (Notes 17 and 23) (Figure 14) Vlow − 0.3 V Vrb Ringback Voltage (Note 17) (Figure 14) Toe_lat tpd 0.2 OE Latency (Note 11) 6 V 12 Cycles 0.6 1.0 1.4 ns Output−to−Output Skew across all 8 outputs DIF_[7:0] (Notes 30 and 31) 0 30 100 ps TSKEW(0−0) Output−to−Output Skew between 2 output pairs controlled by the same OE DIF_[7:0] (Notes 30 and 31) 0 5 20 ps tJITTERf Additive RMS Phase Jitter fcarrier = 156.25 MHz, 12 kHz − 20 MHz Integrated Range (Figure 3) 46 80 fs tjPCIeG3 Additive RMS Phase Jitter PCIe Gen 3 (PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz) (Notes 34 and 35) 0.07 0.4 ps tjPCIeG4 Additive RMS Phase Jitter PCIe Gen 4 (PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz) (Notes 34 and 35) 0.07 0.4 ps tSKEW Input−to−Output Delay CLK_IN, DIF_[7:0] (Note 31) 4 N/A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 11. Time from deassertion until outputs are >200 mV. 12. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#. 13. Measured from VOL = 0.175 V to VOH = 0.525 V. Only valid for Rising Clock and Falling Clock#. 14. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing 15. Test configuration is RS = 33.2 W, RP = 49.9, CL = 2 pF, RREF = 475 W. 16. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhigh avg − 0.700). Vcross(rel) Max = 0.550 − 0.5 (0.700 – Vhigh avg), (see Figure 16 for further clarification). 17. Measurement taken from Single Ended waveform. 18. Measurement taken from differential waveform. 19. Unless otherwise noted, all specifications in this table apply to all frequencies. 20. Vhigh is defined as the statistical average High value as obtained by using the Oscilloscope Vhigh Math function. 21. Vlow is defined as the statistical average Low value as obtained by using the Oscilloscope Vlow Math function. 22. Overshoot is defined as the absolute value of the maximum voltage. 23. Undershoot is defined as the absolute value of the minimum voltage. 24. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 25. DVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed variance in Vcross for any particular system. 26. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max. 27. Matching applies to rising edge rate for clock and falling edge rate for Clock#. It is measured using a © 75 mV window centered on the average crosspoint where clock rising meets Clock# falling. The median crosspoint is used to calculate the voltage threshold the oscilloscope is to use for the edge rate calculations. 28. Slew Rate matching is derived using the following, 2 * (Trise – Tfall) / (Trise + Tfall). 29. Input slew rate is based on single ended measurement. This is the minimum input slew rate at which the NB3L208K devices are guaranteed to meet all performance specifications. 30. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 31. Measured from differential cross−point to differential cross−point with scope averaging on to find mean value. 32. The differential input clock is expected to be sourced from a high performance clock oscillator. 33. Measured at 3.3 V ©10% with typical HCSL input levels. 34. See http://www.pcisig.com for complete specs 35. For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jitter)2 - (input jitter)2 www.onsemi.com 6 NB3L208K Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature To obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is similar or greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. The above phase noise data was captured using Agilent E5052A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The additive RMS phase jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 45.7 fs. The additive RMS phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. Additive RMS phase jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 45.7 fs + Ǹ73.7 fs 2 * 57.8 fs 2 www.onsemi.com 7 NB3L208K CLK_IN VIH Vth CLK_IN VIL CLK_IN# CLK_IN# Vth Figure 4. Differential Input Driven Single−Ended VDD Vthmax Figure 5. Differential Inputs Driven Differentially VIHmax VILmax VIH Vth VIL Vth CLK_IN# CLK_IN VIHmin Vthmin Figure 6. Vth Diagram VDD VILDmax CLK_IN# CLK_IN VIHDtyp VID = VIHD − VILD VILDtyp GND VILD Figure 7. Differential Inputs Driven Differentially VIHDmax VIHCMR MAX VIHCMR MIN VIHD VILmin GND VIHCMR VID = |VIHD(IN) − VILD(IN)| VIHDmin CLK_IN# CLK_IN DIF_n# DIF_n VINPP = VIH(CLK_IN) − VIL(CLK_IN) VOUTPP = VOH(DIF_n) − VOL(DIF_n) tPHL VILDmin tPLH Figure 8. VIHCMR Diagram Figure 9. AC Reference Measurement www.onsemi.com 8 NB3L208K DIF_n RS1 Z0 = 50 W Receiver HCSL Driver RS2 Z0 = 50 W DIF_n# IREF CL1 2 pF RL1 50 W CL2 2 pF RL2 50 W RREF A. Connect 475 W resistor RREF from IREF pin to GND. B. RS1, RS2: 33 W for Test and Evaluation. Select to Minimizing Ringing. C. CL1, CL2: Receiver Input Simulation (for test only not added to application circuit. D. RL1, RL2 Termination and Load Resistors Located at Received Inputs. Figure 10. Typical Termination Configuration for Output Driver and Device Evaluation 3.3 V IREF IOUT C1 VMirror MIref 2R MMir MOUTB MOUT MDum R OUT ~1.1 V Out_predrv OUT RREF Figure 11. HCSL Simplified Output Structure www.onsemi.com 9 NB3L208K NB3L208K Qx HCSL Device Zo = 50 W 100 W Qx 100 W Zo = 50 W RL = 150 W IREF RREF LVDS Device RL = 150 W GND Figure 12. HCSL Interface Termination to LVDS MEASUREMENT POINTS FOR DIFFERENTIAL TRise (Clock) VOH = 0.525 V VCross VOL = 0.175 V TFall (Clock#) Figure 13. Single−Ended Measurement Points for Trise, Tfall Vovs Vhigh Vrb Vrb Vlow Vuds Figure 14. Single−Ended Measurement Points for Vovs, Vuds, Vrb www.onsemi.com 10 NB3L208K TPeriod High Duty Cycle% Low Duty Cycle% Skew measurement point 0.000 V Figure 15. Differential (CLOCK – CLOCK#) Measurement Points (Tperiod, Duty Cycle) Vcross(rel) Max 550 500 450 Crossing Point (mV) For Vhigh > 700mV Use Equ. 2 For Vhigh < 700mV Use Equ. 1 400 350 Vcross(rel) Min 300 250 200 625 650 675 700 725 750 775 800 825 850 Vhigh Average (mV) Equ 1: Vcross(rel) Max = 0.550 − 0.5(0.7 − Vhigh avg) Equ 2: Vcross(rel) Min = 0.250 + 0.5(Vhigh avg − 0.7) Figure 16. Vcross Range Clarification (Note 36) 36. The picture above illustrates the effect of Vhigh above and below 700 mV on the Vcross range. The purpose of this is to prevent a 250 mV Vcross with an 850 mV Vhigh. In addition, this prevents the case of a 550 mV Vcross with a 660 mV Vhigh. The actual specification for Vcross is dependent upon the measured amplitude of Vhigh. www.onsemi.com 11 NB3L208K Signal and Feature Operation Table 6. OE# FUNCTIONALITY (Notes 37, 38 and 39) CLK_IN / CLK_IN# OE# (Pin) DIF DIF # Notes Running 1 Low Low 37 Running 0 Running Running Not Running x x x 37. The outputs are tri−stated, but the termination networks pull them low 38. OE# pins are asynchronous asserted−low signals. 39. Each OE# pin controls two pair of DIF outputs. OE# Assertion (Transition from ‘1’ to ‘0’) OE# De−Assertion (Transition from ‘0’ to ‘1’) All differential outputs that were tri−stated (low due to termination pull down) will resume normal operation in a glitch free manner. The latency from the assertion to active outputs is 4 − 12 DIF clock periods. Note: Input clock must remain running for a minimum of 12 clock cycles. The maximum latency from the de−assertion to tristated (low due to termination pull down) outputs is 12 DIF clock periods. Table 7. NB3L208K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS Board Target Trace/Term Z Reference R, Iref = VDD/(3*RREF) Output Current VOH @ Z Rs Rp 100 W Differential 50 W Single−Ended RREF = 475 W 1%, IREF = 2.32 mA IOH = 6 * IREF 0.7 V @ 50 33 W 5% 50 W 5% 85 W Differential 43 W Single−Ended RREF = 412 W, 1%, IREF = 2.67 mA IOH = 6 * IREF 0.7V @ 43.2 27 W 5% 43 W 5% ORDERING INFORMATION Package Shipping† NB3L208KMNG QFN32 (Pb−Free) 74 Units / Rail NB3L208KMNTXG QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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