2.5 V / 3.3 V / 5.0 V
1:4 Clock Fanout Buffer
NB3L553
Description
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for
clock distribution in mind. The NB3L553 specifically guarantees low
output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
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MARKING DIAGRAMS*
Features
•
•
•
•
•
•
•
•
•
•
Input/Output Clock Frequency up to 200 MHz
Low Skew Outputs (35 ps), Typical
RMS Phase Jitter (12 kHz – 20 MHz): 29 fs (Typical)
Output goes to Three−State Mode via OE
Operating Range: VDD = 2.375 V to 5.25 V
5 V Tolerant Input Clock ICLK
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
8
SOIC−8
D SUFFIX
CASE 751
8
1
3L553
ALYW
G
1
3L553
A
L
Y
W
G
1
DFN8
MN SUFFIX
CASE 506AA
1
Q1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
6P MG
G
6P = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Q2
ICLK
Q3
*For additional marking information, refer to
Application Note AND8002/D.
Q4
PINOUT DIAGRAM
OE
VDD
Figure 1. Block Diagram
Q0
Q1
GND
1
8
2
7
3
6
4
5
OE
Q3
Q2
ICLK
ORDERING INFORMATION
Package
Shipping†
NB3L553DG
SOIC−8
(Pb−Free)
98 Units/Rail
NB3L553DR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
NB3L553MNR4G
DFN−8
(Pb−Free)
1000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
March, 2021 − Rev. 11
1
Publication Order Number:
NB3L553/D
NB3L553
Table 1. OE, OUTPUT ENABLE FUNCTION
OE
Function
0
Disable
1
Enable
Table 2. PIN DESCRIPTION
Pin #
Name
Type
Description
1
VDD
Power
2
Q0
(LV)CMOS/(LV)TTL Output
Clock Output 0
3
Q1
(LV)CMOS/(LV)TTL Output
Clock Output 1
4
GND
Power
5
ICLK
(LV)CMOS Input
6
Q2
(LV)CMOS/(LV)TTL Output
Clock Output 2
7
Q3
(LV)CMOS/(LV)TTL Output
Clock Output 3
8
OE
(LV)TTL Input
−
EP
Thermal Exposed Pad
Positive supply voltage (2.375 V to 5.25 V)
Negative supply voltage; Connect to ground, 0 V
Clock Input. 5.0 V tolerant
VDD for normal operation. Pin has no internal pullup or pull down resistor for open
condition default. Use from 1 to 10 kOhms external resistor to force an open condition default state.
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
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2
NB3L553
Table 3. MAXIMUM RATINGS
Symbol
VDD
Parameter
Positive Power Supply
Condition 1
Condition 2
Rating
Unit
GND = 0 V
−
6.0
V
OE
ICLK
GND = 0 V and
VDD = 2.375 V to 5.25 V
GND – 0.5 v VI v VDD + 0.5
GND – 0.5 v VI v 5.75
V
−
−
≥ −40 to ≤ +85
°C
VI
Input Voltage
TA
Operating Temperature Range,
Industrial
Tstg
Storage Temperature Range
−
−
−65 to +150
°C
qJA
Thermal Resistance
(Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
SOIC−8
41 to 44
°C/W
qJA
Thermal Resistance
(Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
DFN8
35 to 40
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 2 kV
> 150 V
> 2 kV
Level 1
UL−94 code V−0 @ 0.125 in
531 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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3
NB3L553
Table 5. DC CHARACTERISTICS (VDD = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
IDD
Power Supply Current @ 135 MHz, No Load
VOH
Output HIGH Voltage – IOH = −16 mA
VOL
Output LOW Voltage – IOL = 16 mA
Min
Typ
Max
Unit
−
25
30
mA
1.7
−
−
V
−
−
0.4
V
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD÷2)+0.5
−
5.0
V
VIL, ICLK
Input LOW Voltage, ICLK
−
−
(VDD÷2)−0.5
V
VIH, OE
Input HIGH Voltage, OE
1.8
−
VDD
V
VIL, OE
Input LOW Voltage, OE
−
−
0.7
V
ZO
Nominal Output Impedance
−
20
−
W
CIN
Input Capacitance, ICLK, OE
−
5.0
−
pF
IOS
Short Circuit Current
−
± 28
−
mA
Min
Typ
Max
Unit
DC CHARACTERISTICS (VDD = 3.15 V to 3.45 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
IDD
Power Supply Current @ 135 MHz, No Load
VOH
Output HIGH Voltage – IOH = −25 mA
VOL
Output LOW Voltage – IOL = 25 mA
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
−
35
40
mA
2.4
−
−
V
−
−
0.4
V
VDD − 0.4
−
−
V
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD÷2)+0.7
−
5.0
V
VIL, ICLK
Input LOW Voltage, ICLK
−
−
(VDD÷2)−0.7
V
VIH, OE
Input HIGH Voltage, OE
2.0
−
VDD
V
VIL, OE
Input LOW Voltage, OE
0
−
0.8
V
ZO
Nominal Output Impedance
−
20
−
W
CIN
Input Capacitance, OE
−
5.0
−
pF
IOS
Short Circuit Current
−
± 50
−
mA
Min
Typ
Max
Unit
−
45
85
mA
2.4
−
−
V
−
−
0.4
V
VDD − 0.4
−
−
V
DC CHARACTERISTICS (VDD = 4.75 V to 5.25 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
IDD
Power Supply Current @ 135 MHz, − No Load
VOH
Output HIGH Voltage – IOH = −35 mA
VOL
Output LOW Voltage – IOL = 35 mA
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD÷2) + 1
−
5.0
V
VIL, ICLK
Input LOW Voltage, ICLK
−
−
(VDD÷2) − 1
V
VIH, OE
Input HIGH Voltage, OE
2.0
−
VDD
V
VIL, OE
Input LOW Voltage, OE
−
−
0.8
V
ZO
Nominal Output Impedance
−
20
−
W
CIN
Input Capacitance, OE
−
5.0
−
pF
IOS
Short Circuit Current
−
± 80
−
mA
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4
NB3L553
Table 6. AC CHARACTERISTICS; VDD = 2.5 V +5% (VDD = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Min
Typ
Max
Unit
fin
Input Frequency
Characteristic
−
−
200
MHz
tr/tf
Output rise and fall times; 0.8 V to 2.0 V
−
1.0
1.5
ns
tpd
Propagation Delay, CLK to Qn (Note 4)
2.2
3.0
5.0
ns
tskew
Output−to−output skew; (Note 5)
−
35
50
ps
tskew
Device−to−device skew, (Note 5)
−
−
500
ps
AC CHARACTERISTICS; VDD = 3.3 V +5% (VDD = 3.15 V to 3.45 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
fin
Characteristic
Conditions
Input Frequency
fcarrier = 100 MHz
Min
Typ
Max
Unit
−
−
200
MHz
−
18
−
fs
tjitter (f)
RMS Phase Jitter (Integrated 12 kHz −
20 MHz) (See Figures 2 and 3)
tr/tf
Output rise and fall times; 0.8 V to 2.0 V
−
0.6
1.0
ns
tpd
Propagation Delay, CLK to Qn (Note 4)
2.0
2.4
4.0
ns
tskew
Output−to−output skew; (Note 5)
−
35
50
ps
tskew
Device−to−device skew, (Note 5)
−
−
500
ps
AC CHARACTERISTICS; VDD = 5.0 V +5% (VDD = 4.75 V to 5.25 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
fin
Characteristic
Min
Input Frequency
fcarrier = 100 MHz
Min
Typ
Max
Unit
−
−
200
MHz
−
29
−
fs
tjitter (f)
RMS Phase Jitter (Integrated 12 kHz −
20 MHz) (See Figures 2 and 3)
tr/tf
Output rise and fall times; 0.8 V to 2.0 V
−
0.3
0.7
ns
tpd
Propagation Delay, CLK to Qn (Note 4)
1.7
2.5
4.0
ns
tskew
Output−to−output skew; (Note 5)
−
35
50
ps
tskew
Device−to−device skew, (Note 5)
−
−
500
ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Outputs loaded with external RL = 33 W series resistor and CL = 15 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should
be connected between VDD and GND.
4. Measured with rail−to−rail input clock
5. Measured on rising edges at VDD ÷ 2 between any two outputs with equal loading.
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5
NB3L553
Figure 2. Phase Noise Plot at 100 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3L553 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded area) is 18 fs (RMS Phase Jitter of the input source is 75.40 fs and Output (DUT+Source) is 93.16 fs).
Figure 3. Phase Noise Plot at 100 MHz at an Operating Voltage of 5 V, Room Temperature
The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3L553 device measured with an input
source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz;
as shown in the shaded area) is 29 fs (RMS Phase Jitter of the input source is 75.40 fs and Output (DUT+Source) is 103.85 fs).
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE F
DATE 04 MAY 2016
1
SCALE 4:1
D
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
A
B
L1
ÇÇ
ÇÇ
ÇÇ
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÇÇ
ÉÉ
ÇÇ
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
ÇÇ
A3
MOLD CMPD
A1
DETAIL B
0.08 C
(A3)
NOTE 4
SIDE VIEW
DETAIL A
ALTERNATE
CONSTRUCTIONS
A1
C
D2
8X
4
1
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
L
5
8
e/2
e
8X
0.90
b
0.05 C
8X
0.50
2.30
1
0.10 C A B
8X
0.30
NOTE 3
BOTTOM VIEW
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
1
1.30
PACKAGE
OUTLINE
E2
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.30 REF
0.25
0.35
−−−
0.10
XXMG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON18658D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN8, 2.0X2.0, 0.5MM PITCH
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2016
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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