NB3L853141DTR2G

2.5 V/3.3 V 1:5 LVPECL Fanout Buffer NB3L853141 Description The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L853141 features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The SEL pin will select the differential clock inputs, CLK0 & CLK0, when LOW (or left open and pulled LOW by the internal pull−down resistor). When SEL is HIGH, the single−ended CLK1 input is selected. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. www.onsemi.com MARKING DIAGRAM NB3L 3141 ALYW TSSOP−20 DT SUFFIX CASE 948E A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Features • 700 MHz Maximum Clock Output Frequency • CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL, • • • • • • • • • • • LVHSTL, SSTL, LVCMOS CLK1 can Accept LVCMOS and LVTTL Five Differential LVPECL Clock Outputs 1.5 ns Maximum Propagation Delay Operating Range: VCC = 2.375 V to 3.8 V LVCMOS Compatible Control Inputs Selectable Differential or LVCMOS Clock Inputs Synchronous Clock Enable 30 ps Max. Skew Between Outputs −40°C to +85°C Ambient Operating Temperature Range TSSOP−20 Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • Computing and Telecom • Routers, Servers and Switches • Backplanes © Semiconductor Components Industries, LLC, 2015 May, 2021 − Rev. 3 D EN Q Q0 Q0 CLK0 0 CLK0 Q1 Q1 + Q2 1 CLK1 Q2 Q3 SEL Q3 Q4 Q4 Figure 1. Simplified Logic Diagram of NB3L853141 ORDERING INFORMATION Device Package Shipping† NB3L853141DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NB3L853141/D NB3L853141 VCC EN VCC NC CLK1 CLK0 CLK0 NC 20 19 18 17 16 15 14 13 SEL VEE 12 Table 1. FUNCTION TABLE 11 CLK0 CLK1 SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK0 or CLK1 X = Don’t Care 1 2 3 4 5 6 7 8 9 10 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Note: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 2. PIN DESCRIPTION Open Default Pin Number Name I/O Description 1 Q0 LVPECL Output Non−Inverted Differential Clock Output 2 Q0 LVPECL Output Inverted Differential Clock Output 3 Q1 LVPECL Output Non−Inverted Differential Clock Output 4 Q1 LVPECL Output Inverted Differential Clock Output 5 Q2 LVPECL Output Non−Inverted Differential Clock Output 6 Q2 LVPECL Output Inverted Differential Clock Output 7 Q3 LVPECL Output Non−Inverted Differential Clock Output 8 Q3 LVPECL Output Inverted Differential Clock Output 9 Q4 LVPECL Output Non−Inverted Differential Clock Output 10 Q4 LVPECL Output Inverted Differential Clock Output 11 VEE Power 12 SEL LVCMOS / LVTTL Input 13 NC 14 CLK0 Multi−Level Input High Inverted Differential Clock Input. Internal Pull−up Resistor. 15 CLK0 Multi−Level Input Low Non−Inverted Differential Clock Input. Internal Pull−down Resistor. 16 CLK1 LVCMOS/LVTTL Input Low Single−ended Clock Input. Internal Pull−down Resistor. 17 NC 18 VCC Power 19 EN LVCMOS/LVTTL Input 20 VCC Power Negative Supply Voltage Low Clock Select Input. When HIGH, selects CLK1 input. When LOW, selects CLK0, CLK0 inputs. Internal Pull−down Resistor. No Connect No Connect Positive Supply Voltage Low Synchronous Clock Enable Input. When Low, outputs are enabled. When High, outputs are disabled Low. Internal Pull−down Resistor. Positive Supply Voltage All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 mF to GND. www.onsemi.com 2 NB3L853141 Table 3. ATTRIBUTES (Note 1) Characteristics Value ESD Protection Human Body Model Machine Model > 2 kV > 200 V RPU − Pull−up Resistor 50 kW RPD − Pull−down Resistor 50 kW Moisture Sensitivity (Note 1) TSSOP−20 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL*94 code V*0 @ 0.125 in Transistor Count 300 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 4.6 V −0.5 to VCC + 0.5 V 50 100 mA mA VCC LVPECL Mode Power Supply VEE = 0 V VI LVPECL Mode Input Voltage VEE = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 50 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W Tsol Wave Solder