NB3L8533DTG

NB3L8533 2.5V/3.3V Differential 2:1 MUX to 4 LVPECL Fanout Buffer Description The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L8533 features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential clock inputs, CLK and CLK, when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the Differential PCLK and PCLK inputs are selected. The common enable (CLK_EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. www.onsemi.com MARKING DIAGRAM TSSOP−20 DT SUFFIX CASE 948E A WL YY WW G Features • • • • • • • • • • • • • 650 MHz Maximum Clock Output Frequency CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL Four Differential LVPECL Clock Outputs 1.5 ns Maximum Propagation Delay Operating Range: VCC = 2.375 V to 3.630 V LVCMOS Compatible Control Inputs Selectable Differential Clock Inputs Synchronous Clock Enable 30 ps Max. Skew Between Outputs −40°C to +85°C Ambient Operating Temperature Range TSSOP−20 Package These are Pb−Free Devices NB3L 8533 ALYW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package + CLK_EN D Q Q0 Q0 CLK 0 CLK Q1 Q1 + Q2 PCLK Q2 1 PCLK Q3 + Q3 CLK_SEL Figure 1. Simplified Logic Diagram of NB3L8533 Applications • Computing and Telecom • Routers, Servers and Switches • Backplanes © Semiconductor Components Industries, LLC, 2014 December, 2014 − Rev. 1 ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. 1 Publication Order Number: NB3L8533/D NB3L8533 VEE 1 20 Q0 CLK_EN 2 19 Q0 CLK_SEL 3 18 VCC CLK 4 17 Q1 CLK 5 16 Q1 PCLK 6 15 Q2 PCLK 7 14 Q2 nc 8 13 VCC nc 9 12 Q3 10 11 Q3 VCC Figure 2. Pinout Diagram (Top View) Table 1. FUNCTIONS Inputs CLK_EN CLK_SEL 0 0 Outputs Input Function Output Function Qx Qx 0 CLK input selected Disabled LOW HIGH 1 PCLK Inputs Selected Disabled LOW HIGH 1 0 CLK input selected Enabled CLK Invert of CLK 1 1 PCLK Inputs Selected Enabled PCLK Invert of PCLK 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. Table 2. PIN DESCRIPTION Open Default Pin Number Name I/O Description 1 VEE Power 2 CLK_EN LVCMOS/LVTTL Input Pull-up Synchronized Clock Enable when HIGH. When LOW, outputs are disabled (Qx HIGH, Qx LOW) 3 CLK_SEL LVCMOS/LVTTL Input Pull-down Clock Input Select (HIGH selects PCLK, LOW selects CLK input) 4 CLK Input Pull-down Non−inverted Differential Clock Input. Float open when unused. 5 CLK Input Pull-up 6 PCLK Input Pull-down 7 PCLK Input Pull-up 8 NC 9 NC 10 VCC Power 11 Q3 LVPECL Output Complement Differential Output 12 Q3 LVPECL Output True Differential Output 13 VCC Power 14 Q2 LVPECL Output Complement Differential Output 15 Q2 LVPECL Output True Differential Output 16 Q1 LVPECL Output Complement Differential Output 17 Q1 LVPECL Output True Differential Output 18 VCC Power 19 Q0 LVPECL Output Complement Differential Output 20 Q0 LVPECL Output True Differential Output Negative (Ground) Power Supply pin must be externally connected to power supply to guarantee proper operation. Inverted Differential Clock Input. Float open when unused. Non−inverted Differential Clock Input. Float open when unused. Inverted Differential Clock Input. Float open when unused. No Connect No Connect Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. www.onsemi.com 2 NB3L8533 Table 3. ATTRIBUTES (Note 2) Characteristics ESD Protection Value Human Body Model Machine Model > 2 kV > 200 V RPU − Pull−up Resistor 50 kW RPD − Pull−down Resistor 50 kW Moisture Sensitivity (Note 2) Flammability Rating TSSOP−20 Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 289 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit 4.6 V −0.5 to VCC + 0.5 V 50 100 mA mA VCC Positive Power Supply Voltage VEE = 0 V VI Input Voltage VEE = 0 V Iout Output Current Continuous Surge TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 TSSOP−20 140 50 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W Tsol Wave Solder 265 °C VI ≤ VCC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 NB3L8533 Table 5. DC CHARACTERISTICS VCC = 2.375 V to 3.630 V; VEE = 0 V; TA = −40°C to +85°C (Note 3) Symbol Characteristic Min Typ Max Unit 3.630 V 40 mA POWER SUPPLY VCC Power Supply Voltage IEE Power Supply Current (Outputs Open) 2.375 LVPECL OUTPUTS (Note 4) VOH Output HIGH Voltage VCC−1.4 VCC−0.9 V VOL Output LOW Voltage VCC−2.0 VCC−1.7 V 0.6 1.0 V VSWING Output Voltage Swing, Peak−to−Peak DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 5) (Note 7) VIHD Differential Input HIGH Voltage CLK PCLK 0.5 1.5 VCC−0.85 V VILD Differential Input LOW Voltage CLK PCLK 0 0.5 VIHD−0.15 VIHD−0.30 V VCMR Common Mode Input Voltage; (Note 8) CLK/CLKb PCLK/PCLKb 0.5 1.5 VCC–0.85 V VID Differential Input Voltage (VIHD−VILD) CLK/CLKb PCLK/PCLKb 0.15 0.3 1.3 1.0 V IIH Input HIGH Current VIN = VCC = 3.630 V CLK, PCLK CLKb, PCLKb 150 5 mA IIL Input LOW Current VIN = 0 V, VCC = 3.630 V CLK, PCLK CLKb, PCLKb mA −5 −150 LVCMOS/LVTTL INPUTS (CLK_EN, CLK_SEL) VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current VIN = VCC = 3.630 V CLK_EN CLK_SEL IIL Input Low Current VIN = 0 V, VCC = 3.630 V CLK_EN CLK_SEL 2.0 VCC+0.3 −0.3 0.8 V 5 150 mA −150 −5 V mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and Output parameters vary 1:1 with VCC. 4. LVPECL outputs loaded with 50 W to VCC − 2 V for proper operation. 5. VIH, VIL, Vth and VISE parameters must be complied with simultaneously. 6. Vth is applied to the complementary input when operating in single−ended mode. 7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 8. The common mode voltage is defined as VIH. www.onsemi.com 4 NB3L8533 Table 6. AC CHARACTERISTICS, VCC = 2.375 V to 3.630 V, TA = −40°C to +85°C (Note 9) Symbol fMAX FN Characteristic Phase Noise, fC = 156.25 MHz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz tPLH, tPHL Propagation Delay to Differential Outputs, @ 50 MHz (Figures 6 and 7) (VCC = 3.3 V) t∫FN Additive Phase Jitter, RMS; fC = 156.25 MHz, Integration Range: 12 kHz − 20 MHz tsk(o) tsk (pp) VINpp tr/tf ODC Min Typ Maximum Input Clock Frequency: VOUTpp ≥ 300 mV Note 10 Note 11 Offset from Carrier CLK/CLK to Q/Q PCLK/PCLK to Q/Q Max Unit 650 MHz −124.4 −136.1 −144.2 −153.3 −156.2 −156.2 −156.4 1.0 dBc/ Hz 1.55 0.05 ns ps Output−to−output skew; (Note 12) 30 ps Part−to−Part Skew; (Note 13) 150 ps 150 1300 mV 250 600 ps 47 53 % Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) Output rise and fall times, 20% to 80%, @ 50 MHz Qn, Qn Output Clock Duty Cycle Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. All parameters measured at fMAX unless noted otherwise. The cycle−to−cycle jitter on the input will equal the jitter on the output. The part does not add jitter 9. Measured using a VINPPmin source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50 W to VCC − 2 V. 10. Measured from the differential input crossing point to the differential output crossing point. 11. Measured from VCC /2 input crossing point to the differential output crossing point. 12. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 13. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 14. Output voltage swing is a single−ended measurement operating in differential mode. 15. Input voltage swing is a single−ended measurement operating in differential mode. www.onsemi.com 5 NB3L8533 Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature To obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. The above phase noise data was captured using Agilent E5052A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The RMS Phase Jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 51.76 fs. The additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. RMS additive jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 51.76 fs + Ǹ100.24 fs 2 * 85.84 fs 2 www.onsemi.com 6 NB3L8533 VCC CLK PCLK VID VCMR CLK PCLK VEE Figure 4. VCMR Diagram VID = ⎜ VIHD(IN) − VILD(IN)⎜ IN VIHD IN VILD Figure 5. Differential Inputs Driven Differentially IN VCC / 2 VINPP = VIH(IN) − VIL(IN) IN VCC / 2 CLK_SEL tpd Q tpd Qx Q Qx tPHL tPLH Figure 7. CLK_SEL to Qx Timing Diagram Figure 6. AC Reference Measurement Figure 8. Differential Input Driven Single−ended Differential Clock Input to Accept Single−ended Input as a bypass capacitor. Locate these components close the device pins. R1 and R2 must be adjusted to position Vref to the center of the input swing on CLK. Figure 8 shows how the CLK input can be driven by a single−ended Clock signal. C1 is connected to the Vref node www.onsemi.com 7 NB3L8533 Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Package Shipping† NB3L8533DTG TSSOP−20 (Pb−Free) 75 Units / Rail NB3L8533DTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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