NB3L8543SDTR2G

NB3L8543S 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select www.onsemi.com Description The NB3L8543S is a high performance, low skew 1−to−4 LVDS Clock Fanout Buffer. The NB3L8543S features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential CLK and CLK inputs when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the differential PCLK and PCLK inputs are selected. The common clock enable pin, CLK_EN, is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse on the outputs during asynchronous assertion/deassertion of the clock enable pin. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Four Differential LVDS Output Pairs Two Selectable Differential Clock Inputs CLK/CLK Can Accept LVPECL, LVDS, HCSL, SSTL and HSTL PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL Maximum Output Frequency: 650 MHz Additive Phase Jitter, RMS: 50 fs (typical) Output Skew: 40 ps (maximum) Part−to−part Skew: 200 ps (maximum) Propagation Delay: 1.9 ns (maximum) Operating Range: VDD = 2.5 V ±5% or 3.3 V ±10% −40°C to +85°C Ambient Operating Temperature Range TSSOP−20 Package These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 October, 2014 − Rev. 1 NB3L 8543 ALYWG G TSSOP−20 DT SUFFIX CASE 948E A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) + D CLK_EN Features • • • • • • • • • • • • • MARKING DIAGRAM 1 Q Q0 Q0 CLK 0 CLK Q1 Q1 + Q2 PCLK PCLK CLK_SEL Q2 1 Q3 + + Q3 OE Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. Publication Order Number: NB3L8543E/D NB3L8543S GND 1 20 Q0 CLK_EN 2 19 Q0 CLK_SEL 3 18 VDD CLK 4 17 Q1 CLK 5 16 Q1 PCLK 6 15 Q2 PCLK 7 14 Q2 OE 8 13 GND GND 9 12 Q3 10 11 Q3 VDD Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Open Default Number Name I/O Description 1, 9, 13 GND Power 2 CLK_EN NC Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are disabled (Qx HIGH, Qx LOW). See Figure 3. 3 CLK_SEL NC Pulldown Clock Input Select (HIGH selects PCLK/PCLK, LOW selects CLK/ CLK input 4 CLK Input Pulldown True Standard Clock Input. Float open when unused. 5 CLK Input Pullup Invert Standard Clock Inputs. Float open when unused. 6 PCLK Input Pulldown True Peripheral Clock Input. Float open when unused. 7 PCLK Input Pullup Invert Peripheral Clock Inputs. Float open when unused. 8 OE NC Pullup Output Enable Control. When HIGH, the outputs are active and enabled. When LOW, the outputs are high impedance disabled. 10 ,18 VDD Power Positive Power Supply pin must be externally connected to power supply to guarantee proper operation. 11, 14, 16, 19 Q[3:0] Output Invert LVDS Outputs 12, 15, 17, 20 Q[3:0] Output True LVDS Outputs Negative (Ground) Power Supply pins must be externally connected to power supply to guarantee proper operation. www.onsemi.com 2 NB3L8543S Table 2. FUNCTIONS Inputs Outputs OE CLK_EN CLK_SEL Input Function 0 X X 1 0 0 CLK input selected 1 0 1 1 1 1 1 Output Function Qx Qx HI−Z HI−Z Disabled LOW HIGH PCLK Input Selected Disabled LOW HIGH 0 CLK input selected Enabled CLK Invert of CLK 1 PCLK Input Selected Enabled PCLK Invert of PCLK 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. Figure 3. CLK_EN TIMING DIAGRAM www.onsemi.com 3 NB3L8543S Table 3. ATTRIBUTES (Note 2) Characteristics Value Internal Input Pullup Resistor 50 kW Internal Input Pulldown Resistor 50 kW ESD Protection Human Body Model Machine Model > 2 kV > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level 1 Flammability Rating Oxygen Index UL 94 V−0 @ 0.125 in 28 to 34 Transistor Count 430 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition 1 VDD Supply Voltage Vin Input Voltage Cin Input Capacitance ID Output Current TA Operating Temperature Range, Industrial Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) (Note 4) Tsol Wave Solder Condition 2 Rating Unit 4.6 V –0.5 v VI v VDD + 0.5 V 4 pF 10 15 mA −40 to v +85 °C −65 to +150 °C TSSOP−20 140 50 °C/W °C/W TSSOP−20 23 to 41 °C/W 265 °C Continuous Surge Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). www.onsemi.com 4 NB3L8543S Table 5. DC CHARACTERISTICS VDD = 2.5 V ±5% or 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C (Note 5) Symbol Characteristic Min Typ Max Unit 2.97 2.375 3.3 2.5 3.63 2.625 V 50 mA VDD + 0.3 V POWER SUPPLY VDD Power Supply Voltage IDD Power Supply Current VDD = 3.3 V VDD = 2.5 V LVCMOS/LVTTL INPUTS (CLK_EN, CLK_SEL, OE) VIH Input HIGH Voltage VDD = 3.3 V VDD = 2.5 V VIL Input LOW Voltage VDD = 3.3 V VDD = 2.5 V 0.8 0.7 V IIH Input High Current (VDD = VIN = 3.63 V) CLK_EN, OE CLK_SEL 5 150 mA IIL Input LOW Current (VDD = 3.63 V, VIN = 0 V) CLK_EN, OE CLK_SEL 2 1.7 −150 −5 mA DIFFERENTIAL INPUTS (see Figures 5 and 6) (Note 8) VIHD Differential Input HIGH Voltage CLK PCLK 0.5 1.5 VDD−0.85 VDD V VILD Differential Input LOW Voltage CLK PCLK 0 0.5 VIHD−0.15 VIHD V VID Differential Input Voltage (VIHD − VILD) CLK PCLK 0.15 0.30 1.3 1.0 V VIHCMR Common Mode Input Voltage; (Note 9) CLK PCLK 0.5 1.5 VDD–0.85 VDD V 150 5 mA IIH Input HIGH Current VDD = VIN = 3.63 V CLK, PCLK CLK, PCLK IIL Input LOW Current VDD = 3.63 V, VIN = 0 V CLK, PCLK CLK, PCLK −5 −150 mA LVDS OUTPUTS VOD DVOD VOS DVOS Differential Output Voltage 200 VOD Magnitude Change Differential Output Voltage Offset Voltage 1.125 VOS Magnitude Change IOZ Output High Impedance Leakage Current IOS Output Short Circuit Current VOH Output HIGH Voltage VOL Output LOW Voltage 300 360 mV 0 40 mV 1.25 1.375 V 5 25 mV −10 +10 −5 1.34 0.9 1.06 mA mA 1.6 V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Outputs terminated 100 W across Qx and Qx, see Figure 4. DC Measurements per Figure 10 reference. 6. Vth, VIH, VIL, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. The common mode voltage is defined as VIH. www.onsemi.com 5 NB3L8543S Table 6. AC CHARACTERISTICS VDD = 2.5 V ±5% or 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C (Note 10) Symbol fMAX Characteristic Min Maximum Operating Frequency, VOUTPP ≥ 200 mV tPD Propagation Delay tŕfn Additive Phase Jitter, RMS; fC = 156.25 MHz Integration Range: 12 kHz − 20 MHz Typ Unit 650 500 MHz 0.9 1.9 ns 0.05 Output−to−Output Skew Within A Device tSKEWD−D Device−to−Device Skew, similar path and conditions ODC Max 0 0 ps tSKEWO−O tr/tf VDD = 3.3 V VDD = 2.5 V 15 Output rise and fall times @ 50 MHz, 20% to 80% VDD = 3.3 V VDD = 2.5 V Output Clock Duty Cycle 40 ps 200 ps 150 150 250 500 550 ps 45 50 55 % Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Outputs terminated100 W across Qx and Qx, see Figure 4. Measured from differential crosspoints to differential crosspoints, see Figure 11. 2.05 V ±0.165 V VDD GND V Figure 4. Typical Test Setup and Termination for Evaluation. The VDD of 2.05 V ±0.165 V and GND of −1.25 V Split supply allows a direct connection to an oscilloscope 50 W impedance input module. www.onsemi.com 6 NB3L8543S IN IN Figure 5. Differential Inputs Driven Differentially VDD VIHCMRmax IN IN VIHDmax VILDmax IN VID = |VIHD(IN) − VILD(IN)| VIHCMR VIHD VIHCMRmin VILD VID = VIHD − VILD VIHDtyp VILDtyp IN VIHDmin VILDmin GND Figure 7. VIHCMR Diagram Figure 6. Differential Inputs Driven Differentially IN VDD / 2 VINPP = VIH(IN) − VIL(IN) IN VDD / 2 SEL tpd Q tpd Qx Q Qx tPHL tPLH Figure 9. SEL to Qx Timing Diagram Figure 8. AC Reference Measurement www.onsemi.com 7 NB3L8543S Figure 10. DC Measurement Reference www.onsemi.com 8 NB3L8543S Figure 11. AC Measurement Reference Figure 12. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature www.onsemi.com 9 NB3L8543S Figure 13. Differential Input Interface From LVPECL, CML, LVDS, HSTL, SSTL, or HCSL Figure 14. Differential Input Driven Single−ended Differential Clock Input to Accept Single−ended Input as a bypass capacitor. Locate these components close the device pins. R1 and R2 must be adjusted to position Vref to the center of the input swing on CLK. Figure 14 shows how the CLK input can be driven by a single−ended Clock signal. C1 is connected to the Vref node ORDERING INFORMATION Package Shipping† NB3L8543SDTG TSSOP−20 (Pb−Free) 75 Units / Rail NB3L8543SDTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 NB3L8543S PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D 0.100 (0.004) −T− SEATING H DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT* PLANE 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 11 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB3L8543S ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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