NB3N3001

NB3N3001 3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output Description The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock generator. It accepts a standard 26.5625 MHz fundamental mode AT cut parallel resonant crystal as the reference source for its integrated crystal oscillator and low noise phase−locked loop (PLL) and produces user selectable clock frequencies of either 106.25 MHz or 212.5 MHz. In addition, the PLL circuitry will generate a 50% duty cycle square−wave through a pair of differential LVPECL clock outputs. Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to 10 MHz. The LVPECL output drivers can be disabled to high impedance with the OE pin set LOW. The NB3N3001 operates from a single +3.3 V supply, and is available in both plastic package and die form. The operating temperature range is from −40°C to +85°C. The NB3N3001 device provides the optimum combination of low cost, flexibility, and high performance which makes it ideal for Fibre−Channel applications. Features http://onsemi.com MARKING DIAGRAM 301 YWW AG TSSOP−8 DT SUFFIX CASE 948S A Y WW G = Assembly Location = Year = Work Week = Pb−Free Package • • • • • • • • • • • • PureEdge Clock Family Provides Accuracy and Precision Selectable Output Frequency of 106.25 MHz or 212.5 MHz Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal Fully Integrated Phase−Lock−Loop with Internal Loop Filter Differential 3.3 V LVPECL Outputs Exceeds Bellcore and ITU Jitter Generation Specification RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal (637 kHz − 10 MHz): 0.3 ps (Typical) RMS Phase Noise at 106.25 MHz Phase Noise: Offset Noise Power 100 Hz −108 dBc/Hz 1 kHz −122 dBc/Hz 10 kHz −135 dBc/Hz 100 kHz −135 dBc/Hz Operating Range: VCC = 3.135 V to 3.465 V −40°C to +85°C Ambient Operating Temperature Small Footprint 8−pin TSSOP Package This is a Pb−Free Device ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. FSEL XIN 26.5625 MHz XOUT M = B32 Crystal Oscillator Phase Detector Charge Pump VCO 850 MHz N =B8 orB4 LVPECL Output Q 212.5 MHz or Q 106.25 MHz Figure 1. Logic Diagram © Semiconductor Components Industries, LLC, 2006 1 October, 2006 − Rev. 1 Publication Order Number: NB3N3001/D NB3N3001 VCCA 1 8 VCC Table 1. Output Frequency Select VEE 2 7 Q FSEL 0 6 Q 1 XIN 4 5 FSEL NOTE: Input crystal = 26.5625 MHz 212.5 Output Frequency (MHz) 106.25 NB3N3001 XOUT 3 Figure 2. Pinout (Top View) Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Symbol VCCA VEE XOUT XIN FSEL Q Q VCC Type Power Power Input Input LVTTL/LVCMOS Input Output Output Power Description Positive analog power supply pin. Connected to VCC with filter components (See Figure 8). Negative supply pin. Crystal input (OUT). Crystal input (IN). Frequency select pin. Defaults LOW when left open. Internal pull down resistor to VEE. Inverted differential output. Typically terminated with 50 W to VCC−2.0 V. Noninverted differential output. Typically terminated with 50 W to VCC−2.0 V. Positive digital core power supply pin. Connected to 3.3 V. Table 3. ATTRIBUTES Characteristic ESD Protection Moisture Sensitivity (Note 1) Human Body Model Machine Model Pb−Free Pkg, TSSOP−8 Value > 6 kV > 200 V Level 3 UL 94 V−0 @ 0.125 in 4150 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol VCC VI IO qJA TSTG Supply Voltage Inputs Output Current Thermal Resistance (Junction−to−Ambient) Storage Temperature Continuous Surge 0 Lfpm 500 Lfpm Parameter Value 4.6 −0.5 to VCC + 0.5 50 100 142 103 −65 to 150 Unit V V mA °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NB3N3001 Table 5. POWER SUPPLY DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C) Symbol VCC VCCA ICCA IEE Parameter Core Supply Voltage Analog Supply Voltage Analog Supply Current Power Supply Current Included in IEE Conditions Min 3.135 3.135 Typ 3.3 3.3 19 27 Max 3.465 3.465 23 31 Unit V V mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 6. LVPECL DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C) Symbol VOH VOL VSWING Parameter Output High Voltage (Note 2) Output Low Voltage (Note 2) Peak−to−Peak Output Voltage Swing Conditions Min VCC − 1.4 VCC − 2.0 0.6 0.75 Typ Max VCC − 0.9 VCC − 1.7 1.0 Unit V V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Outputs terminated with 50 W to VCC − 2.0 V. See Figures 4 and 12. Table 7. LVTTL/LVCMOS DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C) Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current FSEL FSEL VCC = VIN = 3.465 V VCC = 3.465 V, VIN = 0 V −5.0 Conditions Min 2.0 −0.3 Typ Max VCC + 0.3 0.8 150 Unit V V mA mA Table 8. PIN CHARACTERISTICS Symbol CIN RPD Parameter Input Capacitance Input Pull Down Resistor Conditions Min Typ 4 100 Max Unit pF kW Table 9. CRYSTAL CHARACTERISTICS (Fundamental Mode 18 pF Parallel Resonant Crystal) Parameter Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Conditions Min Typ 26.5625 50 7.0 Max Unit MHz W pF http://onsemi.com 3 NB3N3001 Table 10. AC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C (Note 4)) Symbol fOUT tjit(∅) Parameter Output Frequency RMS Phase Jitter (Random) (Note 3) Conditions 24 MHz − 30 MHz Crystal (Typ. 25 MHz − 26.5625 MHz) 106.25 MHz; Integration Range: 637 kHz −10 MHz 212.5 MHz; Integration Range: 637 kHz −10 MHz tR/tF odc Output Rise/Fall Time Output Duty Cycle 20% to 80% (See Figure 7) (See Figure 6) 275 48 Min Typ 106.25/ 212.5 0.3 0.3 600 52 ps % Max Unit MHz ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Please refer to the Phase Noise Plot. 4. Output terminated with 50 W to VCC− 2.0 V. See Figures 4 and 12. NOISE POWER (dBc) OFFSET FREQUENCY (Hz) Figure 3. Typical Phase Noise at 106.25 MHz http://onsemi.com 4 NB3N3001 PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot VCC LVPECL Z = 50 W VEE 50 W −1.3 V " 0.165 V f1 Offset Frequency f2 Q Q SCOPE 50 W Noise Power Z = 50 W Phase Noise Mask RMS + Area Under the Masked Phase Noise Plot Figure 4. Output Load AC Test Circuit (Split Power Supply) Figure 5. RMS Phase Jitter Q Q Q Pulse Width tPERIOD odc + tPW tPERIOD Clock Outputs 20% Q tR tF 80% 80% VSWING 20% Figure 6. Output Duty Cycle/Pulse Width/Period Figure 7. Output Rise/Fall Time http://onsemi.com 5 NB3N3001 APPLICATION INFORMATION Power Supply Filtering The NB3N3001 is a mixed analog/digital product, and as such, it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB3N3001 also generates sub−nanosecond output edge rates, and therefore, a good power supply bypassing scheme is a must. The NB3N3001 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCCA). The simplest form of noise isolation is a power supply filter on the VCCA pin. Figure 8 illustrates a typical power supply filter scheme. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. The purpose of this design technique is to try and isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase−locked loop. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise−related problems in most designs. Crystal Oscillator Input Interface Figure 9 illustrates a parallel resonant crystal with its associated load capacitors. The capacitor values shown were determined using a 26.5625 MHz, 18 pF parallel resonant crystal and were chosen to minimize the ppm error. Capacitor values can be adjusted slightly for different board layouts to optimize accuracy. 3.3 V VCC 0.01 mF 10 W VCCA 0.01 mF 10 mF Figure 8. Power Supply Filtering XOUT C1 33 pF X1 18 pF Parallel Crystal XIN C2 27 pF The NB3N3001 features an integrated crystal oscillator to minimize system implementation costs. The oscillator circuit is a parallel resonant circuit and thus, for optimum performance, a parallel resonant crystal should be used. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the NB3N3001 as possible to avoid any board level parasitics. Surface mount crystals are recommended, but not required. Figure 9. Crystal Input Interface APPLICATION SCHEMATIC Figure 10 shows a schematic example of the NB3N3001. An example of LVPECL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the AND8020 Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for generating 106.25 MHz output frequency. The C1 = 27 pF and C2 = 33 pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. VCC VCC R2 10 C3 10 mF VCCA C4 0.01 mF 1 U1 VCCA 2V EE 3X OUT 4 XIN 8 VCC 7 Q Q6 FSEL 5 Q VCC R3 ZO = 50 W 133 R5 133 + Q ZO = 50 W R4 82.5 − R6 82.5 C2 33 pF 18 pF X1 C1 27 pF VCC = 3.3 V C5 0.1 m Figure 10. Typical Application Schematic http://onsemi.com 6 NB3N3001 PC Board Layout Example Figure 11 shows a representative board layout for the NB3N3001. There exists many different potential board layouts and the one pictured is but one. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through−hole HC49 package. The footprints of other components in this example are listed in Table 11. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. The important aspect of the layout in Figure 11 is the low impedance connections between VCC and GND for the bypass capacitors. Combining good quality general purpose chip capacitors with good PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NB3N3001 outputs. It is imperative that low inductance chip capacitors are used. It is equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors. Thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. Fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. The voltage amplitude across the crystal is relatively small. It is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. Table 11. Footprint Table Reference C1, C2 C3 C4, C5 R2 Size 0402 0805 0603 0603 C2 C1 Figure 11. PC Board Layout Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC − 2.0 V Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NB3N3001DTG NB3N3001DTR2G Package TSSOP8 4.4 mm (Pb−Free) TSSOP8 4.4 mm (Pb−Free) Shipping † 100 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NB3N3001 PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE B 8x K REF 0.10 (0.004) M 0.20 (0.008) T U S TU S V S 2X L/2 8 5 L 1 PIN 1 IDENT 4 B −U− J J1 K1 K 0.20 (0.008) T U S A −V− C SECTION N−N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 −−− 1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ −−− 2.20 −−− 3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 −−− 0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −−− 0.087 −−− 0.126 0.076 (0.003) D −T− SEATING PLANE G DETAIL E P N P1 N ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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