NB3N3020 3.3 V, LV-PECL/LV-CMOS Clock Multiplier
Description
The NB3N3020 is a high precision, low phase noise selectable clock multiplier. The device takes a 5 – 27 MHz fundamental mode parallel resonant crystal or a 2 − 210 MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS/LVTTL output at a selectable clock output frequency which is a multiple of the input clock frequency. Three tri−level (Low, Mid, High) LVCMOS/LVTTL single ended select pins set one of 26 possible clock multipliers. An LVCMOS/LVTTL output enable (OE) tri−states clock outputs when low. This device is housed in 5 mm x 4.4 mm narrow body TSSOP 16 pin package.
Features
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16 1 TSSOP−16 DT SUFFIX CASE 948F A L Y W G 16 NB3N 3020 ALYWG G
1
• • • • • •
• •
Selectable Clock Multiplier External Loop Filter is Not Required LV−PECL Differential Output LVCMOS/ LVTTL Outputs RMS Period Jitter of 5 ps Jitter or Low Phase Noise at 125 MHz [25 MHz Input]: Offset Noise Power 100 Hz -95 dBc/Hz 1 kHz -107 dBc/Hz 10 kHz -112 dBc/Hz 100 kHz -117 dBc/Hz 1 MHz -117 dBc/Hz 10 MHz -134 dBc/Hz Operating Range 3.3 V ±10% Industrial Temperature Range −40°C to +85°C
= Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
VDD X1/CLK X2 Sel2 Sel1 Sel0 OE1 GND 1 16 OE2 VDD CLK2 CLK2 GND VDD CLK1 GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 0
1
Publication Order Number: NB3N3020/D
NB3N3020
VDD 5−27 MHz Crystal or 2 – 210 MHz Clock X1 / CLK GND OE2
X2
Clock Buffer/ Crystal Oscillator
Pre Sca ler
Phase Detector
Loop Filter
VCO
LV−PECL Output
CLK2 CLK2
%N
LV−CMOS/ LV−TTL Output
CLK1
Select Control Block
Sel0 Sel1 Sel2
OE1
Figure 1. NB3N3020 Simplified Logic Diagram
Table 1. Pin Description
Pin 6 5 4 1, 11, 15 2 3 7, 16 Name Sel0 Sel1 Sel2 VDD X1/CLK X2 OE1, OE2 GND CLK2 CLK2 CLK1 I/O Tri−Level Input Tri−Level Input Tri−Level Input Power Supply Input Input Input Description Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2 for details. Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2 for details. Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2 for details. Positive supply voltage pins are connected to +3.3 V supply voltage. Crystal or Clock input. Connect to 5 − 27 MHz crystal source or 2 – 210 MHz single−ended clock. See Table 2. Crystal input. Connect to a 5 – 27 MHz crystal or leave unconnected for clock input. See Table 2. Output enable input that tri−states clock outputs when low. Internal pull−up resistor to VDD. OE1 is designated to control LV CMOS output synchronously and OE2 is designated to control LV PECL output synchronously. See operation details in device operation. Ground 0 V. These pins provide GND return path for the devices. Non−inverted clock output. Clock frequency equals input frequency times multiplier. Inverted clock output. Clock frequency equals input frequency times multiplier. Clock Output. Clock frequency equals input frequency times multiplier.
8, 9, 12 13 14 10
Power Supply LVPECL Output LVPECL Output LVTTL/ LVCMOS Output
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NB3N3020
Table 2. Output Frequency Clock Multiplier Select Table
Sel2 L L L L L L L L L M M M M M M M M M H H H H H H H H H Sel1 L L L M M M H H H L L L M M M H H H L L L M M M H H H Sel0 L M H L M H L M H L M H L M H L M H L M H L M H L M H CLK1, CLK2, CLK2 Low (Power Down) Input X 1 Input X 1.33 Input X 1.5 Input X 1.6 Input X 1.875 Input X 2 Input X 2.33 Input X 2.4 Input X 2.5 Input X 2.66 Input X 3 Input X 3.125 Input X 3.2 Input X 3.33 Input X 3.75 Input X 4 Input X 5 Input X 6 Input X 6.25 Input X 6.33 Input X 8 Input X 8.33 Input X 10 Input X 12 Input X 12.5 Input X 16 Clock Input Range [MHz] − 25 − 210 15 −157.5 10 − 140 25 – 131.25 40 − 112 25 − 105 15 − 90 25 – 87.5 10 − 84 15 − 78.75 15 − 70 40 – 67.20 25 – 65.63 15 − 63 20 − 56 2 – 25 6 − 42 5 − 35 20 – 33.6 15 – 33.16 5 – 26.25 15 – 25.2 5 − 21 5 – 17.5 10 – 16.8 5 − 13.125 Crystal Input Range [MHz] − 25 − 27 15 − 27 10 − 27 25 − 27 − 25 − 27 15 − 27 25 − 27 10 − 27 15 − 27 15 − 27 − 25 − 27 15 − 27 20 − 27 5 − 25 6 − 27 5 − 27 20 − 27 15 – 27 5 – 26.25 15 – 25.2 5 − 21 5 – 17.5 10 – 16.8 5 – 13.125
L – Low, M – Mid, H − High
Recommended Crystal Parameters
Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25°C Temperature Stability Aging C0/C1 Ration
Device Operation
Fundamental AT−Cut 5 − 27 MHz 16 − 20 pF 7 pF Max 35 W Max ±20 ppm ±30 ppm ±20 ppm 250 Max
input as determined by the tri−level select inputs [Sel0, Sel1, Sel2].
Clock Multiplication
NB3N3020 is a clock multiplier with the clock multiplier selected by the tri level select inputs [Sel0, Sel1, Sel2]. NB3N3020 has a LVTTL/LVCMOS output [CLK1] and a LVPECL clock output [CLK2, CLK2].
Output Enable
The NB3N3020 is a Clock multiplier. The device can take crystal or clock input and generates LVPECL and LVCMOS/ LVTTL clock outputs which are multiples of the
The device has an output enable [OE] which is used to tri−state the outputs. OE1 controls the CLK1 clock output where as OE2 controls the CLK2, CLK2 clock outputs. When OE1or OE2 are disabled, the respective clock output(s) are tri−stated. In this mode of operation, PLL is still running, with the respective clock outputs tri−stated. When the OE1 or OE2 are enabled, the clock outputs
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NB3N3020
become active synchronous to the internal PLL output clock and do not create any glitches or runt pulses during the transition. In power down mode, the outputs are tri−stated regardless of the state of the OE1, OE2.
Changing Clock Multiplier
for clock and crystal input for specific multipliers are determined by Table 3.
Power Up
The clock output frequency can be dynamically changed using Sel0, Sel1, Sel2 pins. When the clock frequency is changed, the clock outputs move from one frequency to another and the PLL locks to the new frequency within a settling time of 3 msec. There is no glitch during this transition when the clock outputs are active {not tri−stated by OE1, OE2}.
Crystal/ Clock Input
When the NB3N3020 is powered up, it takes 10 msec for the PLL’s to stabilize and lock to the desired frequency of operation as selected by Sel0, Sel1, Sel2. During this time period, there may be glitches in the clock outputs.
Power Down:
The device takes in a 5 – 27 MHz crystal input or 2 – 210 MHz clock input. Once powered up, the input frequency is fixed and should not be changed dynamically. The input cannot accept a spread spectrum clock and needs a fixed frequency clock for device operation. The input frequencies
The device can be powered down when the Sel0, Sel1, Sel2 pins are all connected to GND. In this mode of operation, PLL is turned off and the device consumes less than 5 mA of current. There may be a glitch in clock outputs when the device is powering down. In power down mode, the outputs are tri−stated regardless of the state of the OE1, OE2. In the cases where the application requires glitch−less transitions, in order to avoid glitches it is recommended to use synchronous OE signaling to mask glitches to the clock outputs.
Table 3. Attributes
Characteristics ESD Protection Human Body Model Value 2 kV Level 1 UL−94 code V−0 A 1/8″ 28 to 34 8287 Devices
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
Table 4. Maximum Ratings (Note 2)
Symbol VDD VI Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage (VIN) LV PECL Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Wave Solder 0 LFPM 500 LFPM (Note 3) TSSOP – 16 TSSOP – 16 TSSOP − 16 Condition 1 GND = 0 V GND = 0 V Continuous Surge GND ≤ VI ≤ VDD Condition 2 Rating 4.6 −0.5 V to VDD + 0.5 V 25 50 −40 to +85 −65 to +150 138 108 33 to 36 265 Units V V mA °C °C °C/W °C/W °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3N3020
Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C)
Symbol VDD IDD IDDOE IDDOFF VIH VIL VIH VIL VIM VOH VOL VOH VOL Power Supply Voltage Power Supply Current (Note 4) Power Supply Current when OE1, OE2 is Set Low Power Supply Current when PLL is powered off by Sel0, Sel1, Sel2 Input HIGH Voltage (X1/CLK, OE1, OE2) Input LOW Voltage (X1/CLK, OE1, OE2) Input HIGH Voltage (Sel0, Sel1, Sel2) Input LOW Voltage (Sel0, Sel1, Sel2) Input Mid Voltage (Sel0, Sel1, Sel2) (When left open, defaults to VDD/2 Output HIGH Voltage for CLK2, CLK2 (See Figure 3) Output LOW Voltage for CLK2, CLK2 (See Figure 3) Output HIGH Voltage for CLK1 [IOH = −12 mA] Output LOW Voltage for CLK1 [IOL = 12 mA] VDD – 1.145 VDD – 2.090 2.4 0.4 2000 GND − 300 0.72 VDD GND − 300 VDD/2 VDD – 0.895 VDD – 1.600 Characteristic Min 2.97 Typ 3.3 60 50 5 VDD + 300 800 VDD + 300 800 Max 3.63 75 Unit V mA mA mA mV mV mV mV mV V V V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measurement taken at 125 MHz with LV−PECL & LV−CMOS/ LV−TTL outputs not terminated.
Table 6. AC Characteristics (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C) (Note 5)
Symbol fCLKIN fCLKIN fCLKOUT FNOISE Crystal Input Frequency Clock Input Frequency Output Clock Frequency Phase−Noise Performance (fCLKout = 125 MHz, 25 MHz input) @ 100 Hz offset from carrier @ 1 kHz offset from carrier @ 10 kHz offset from carrier @ 100 kHz offset from carrier @ 1 MHz offset from carrier @ 10 MHz offset from carrier Tjitter p−p Tjitter rms Tjitter p−p Tjitter rms Cycle to Cycle Jitter peak to peak (Note 6) fCLKout= 125 MHz, 25 MHz input Cycle to Cycle Jitter rms (Note 6) fCLKout= 125 MHz, 25 MHz input Period Jitter peak to peak (Note 7) fCLKout= 125 MHz, 25 MHz input Period Jitter rms (Note 7) fCLKout= 125 MHz, 25 MHz input Start up time from power up OE Output Enable/Disable Time PLL settling time 5. Measurement taken with outputs terminated with 50 ohms to VDD − 2 V. See Figure 2. 6. Sampled with 1000 cycles 7. Sampled with 10000 cycles −95 −107 −112 −117 −117 −134 20 5.0 15 3.0 10 10 3 36 9.0 20 5.0 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ms us ms Characteristic Min 5.0 2.0 Typ Max 27 210 210 Unit MHz MHz MHz
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Table 6. AC Characteristics (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C) (Note 5)
Symbol tDUTY_CYCLE tR tF tR tF tR/ tF Characteristic Output Clock Duty Cycle (Measured at cross point for LV PECL clock output and VDD/2 for LVCMOS/ LVTTL clock output) Output Rise Time (Note 5) (Measured from 20% to 80%. Figure 2) LV PECL Output Output Fall Time (Note 5) (Measured from 20% to 80%. Figure 2) LV PECL Output Output Rise Time (Measured from 0.8 to 2 V, no load) LVCMOS/ LV TTL Output Output Fall Time (Measured from 2.0 V to 0.8 V, no load) LVCMOS/ LV TTL Output Input Rise time/ Fall time for LV CMOS/ LV TTL clock input [X1/CLK] 0 Min 45 Typ 50 340 340 Max 55 700 700 1500 1500 1500 Unit % ps ps ps ps ps
5. Measurement taken with outputs terminated with 50 ohms to VDD − 2 V. See Figure 2. 6. Sampled with 1000 cycles 7. Sampled with 10000 cycles NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
LV − PECL Driver
CLK2
Z = 50 W Z = 50 W RL = 50 W RL = 50 W
Receiver Device
CLK2b
VDD − 2 V
Figure 2. Typical Termination for Output Driver for Device Evaluation
VDD − 0.9 V
80%
80%
20% VDD − 1.7 V
20%
tR
340 ps
340 ps
tF
Figure 3. LV−PECL Output Parameter Characteristics
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NB3N3020
PACKAGE DIMENSIONS
TSSOP−16 CASE 948F−01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
2X
L/2
16
9
J1 B −U−
SECTION N−N J N
L
PIN 1 IDENT. 1 8
0.15 (0.006) T U
S
A −V−
N F DETAIL E
C 0.10 (0.004) −T− SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ
0.25 (0.010) M
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
−W−
0.65 PITCH
DIMENSIONS: MILLIMETERS
NB3N3020
ORDERING INFORMATION
Device NB3N3020DTG NB3N3020DTR2G Package TSSOP−16 (Pb−Free) TSSOP−16 (Pb−Free) Shipping† 96 Units / Rail 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB3N3020/D
