NB3N501DG

NB3N501 3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier Description http://onsemi.com The NB3N501 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3−level select inputs (S0, S1). It accepts a standard fundamental mode crystal or an external reference clock signal. Phase−Locked−Loop (PLL) design techniques are used to produce a low jitter, TTL level clock output up to 160 MHz with a 50% duty cycle. An Output Enable (OE) pin is provided, and when asserted low, the clock output goes into tri−state (high impedance). The NB3N501 is commonly used in electronic systems as a cost efficient replacement for crystal oscillators MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 3N501 A L Y W G Features • • • • • • • • • • • • • Clock Output Frequencies up to 160 MHz Nine Selectable Multipliers of the Input Frequency Operating Range: VDD = 3.3 V ±10% or 5.0 V ±5% Low Jitter Output of 25 ps One Sigma (rms) Zero ppm Clock Multiplication Error 45% − 55% Output Duty Cycle TTL/CMOS Output with 25 mA TTL Level Drive Crystal Reference Input Range of 5 − 27 MHz Input Clock Frequency Range of 2 − 50 MHz OE, Output Enable with Tri−State Output 8−Pin SOIC Industrial Temperature Range −40°C to +85°C These are Pb−Free Devices 8 1 1 3N501 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. VDD X1/ICLK Crystal Oscillator crystal or clock CLX2 CLX1 X2 ÷P Charge Pump Phase Detector Multiplier Select ÷M S1 S0 TTL/ CMOS Output CLKOUT Feedback OE GND © Semiconductor Components Industries, LLC, 2013 November, 2013 − Rev. 2 VCO Figure 1. NB3N501 Logic Diagram 1 Publication Order Number: NB3N501/D NB3N501 Table 1. CLOCK MULTIPLIER SELECT TABLE S1* S0* CLKOUT Multiplier L L 4X Input L M 5.3125X Input L H 5X Input M L 6.25X Input M M 2X Input M H 3.125X Input H L 6X Input H M 3X Input H H 8X Input X1/CLK 1 8 X2 VDD 2 7 OE GND 3 6 S0 S1 4 5 CLKOUT Figure 2. NB3N501 Package Pinout, 8−Pin (150 mil) SOIC *Pins S1 and S0 default to M when open L = GND H = VDD M = OPEN (unconnected; will default to VDD/2) Table 2. PIN DESCRIPTION Pin # Name I/O Description 1 X1/CLK Input 2 VDD Power supply Positive supply voltage 3 GND Power supply 0 V. Ground. 4 S1 Three level Input 5 CLKOUT CMOS/TTL Output 6 S0 Three level Input Multiplier select pin − connect to VDD, GND or float 7 OE CMOS/TTL Input Output Enable. CLKOUT is high impedance when OE is low. Internal pullup 8 X2 Crystal Crystal or external reference clock input Multiplier select pin − connect to VDD, GND or float Clock output Crystal input – Leave open when providing an external clock reference Table 3. COMMON OUTPUT FREQUENCY EXAMPLES Table 3. COMMON OUTPUT FREQUENCY EXAMPLES Output Frequency (MHz) Input Frequency (MHz) S1, S0 Output Frequency (MHz) Input Frequency (MHz) S1, S0 20 10 M, M 64 16 0, 0 24 12 M, M 66.66 16.66 0, 0 30 10 1, M 72 12 1, 0 32 16 M, M 75 12 M, 0 33.33 16.66 M, M 80 10 1, 1 16.66 0, 1 37.5 12 M, 1 83.33 40 10 0, 0 90 15 1, 0 48 12 0, 0 100 20 0, 1 50 16.66 1, M 106.25 20 0, M 60 10 1, 0 120 15 1, 1 62.5 20 M, 1 125 20 M, 0 http://onsemi.com 2 NB3N501 Table 4. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model Charged Device Model > 1 kV > 150 V > 1 kV SOIC−8 Level 1 Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0 @ 0.125 in Transistor Count 9727 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter VDD Positive Power Supply VIO Input and Output Voltages TA Condition 1 Condition 2 GND = 0 V Rating Unit 7 V −0.5 V v VIO v VDD + 0.5 V Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) SOIC−8 41 to 44 °C/W Tsol Wave Solder 265 °C Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB3N501 Table 6. DC CHARACTERISTICS VDD = 3.3 V ± 10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min 4.75 3.0 Max Unit 5.25 3.6 V Operating Voltage at 100 MHz (with 20 MHz crystal) IDD Power Supply Current – Inputs and outputs open, CLKOUT operating at 100 MHz (with 20 MHz crystal) VCC = 5 V VCC = 3.3 V VOH Output HIGH Voltage IOH = −4 mA CMOS High VOH Output HIGH Voltage IOH = −25 mA TTL High VOL Output LOW Voltage IOL = 25 mA VIH Input HIGH Voltage, CLK only (pin 1) VIL Input LOW Voltage, CLK only (pin 1) VIH Input HIGH Voltage, S0, S1 VIL Input LOW Voltage, S0, S1 VIH Input HIGH Voltage, OE (pin 7) VIL Input LOW Voltage, OE (pin 7) Cin Input Capacitance, S0, S1 and OE 4 pF ISC Output Short Circuit Current ±70 mA On Chip Pullup Resistor 270 kW Nominal Output Impedance 20 W RPU VCC = 5 V VCC = 3.3 V Typ VDD mA 20 15 VDD − 0.4 V 2.4 V 0.4 (VDD / 2) + 1 V V (VDD / 2) − 1 VDD − 0.5 V V 0.5 2.0 V V 0.8 V 3. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where CL is the specified crystal load capacitance: Crystal capacitance (pF) = (CL − 5) X 2. So, for a crystal with 16 pF load capacitance, use two 22 pF capacitors. Table 7. AC CHARACTERISTICS VDD = 3.3 V ± 10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, TA = −40°C to +85°C Symbol fXtal Characteristic Min Typ Max Unit Crystal Input Frequency (Note 4) 5 27 MHz Clock Input Frequency 2 50 MHz fOUT Output Frequency Range fOUTMIN ≤ fIN x Multiplier ≤ fOUTMAX VDD = 4.75 to 5.25 V (5.0 V ± 5%) VDD = 3.0 to 3.6 V (3.3 V ± 10%) 13 13 160 100 DC Output Clock Duty Cycle at VDD / 2 45 OEH Output enable time, OE high to output on 50 ns OEL Output disable time, OE low to tri−state 50 ns Period Jitter (rms, 1 s) 25 ps Total Period Jitter, (peak−to−peak) ±70 ps 1 ns fCLKIN tjitter (rms) tjitter (pk−to−pk) tr/tf Output rise/fall time (0.8 V to 2.0 V) (measured with 15 pF load) 50 55 MHz % 4. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where CL is the specified crystal load capacitance: Crystal capacitance (pF) = (CL − 12) X 2. So, for a crystal with 16 pF load capacitance, use two 8 pF capacitors. http://onsemi.com 4 NB3N501 APPLICATIONS INFORMATION High Frequency CMOS/TTL Oscillators Crystal Load Capacitors The NB3N501, along with a low frequency fundamental mode crystal, can build a high frequency TTL output oscillator. For example, a 20 MHz crystal connected to the NB3N501 with the 5X output selected (S1 = L, S0 = H) produces an 100 MHz CMOS/TTL output clock. The total on chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL − 12 pF) * 2. In this equation, CL = crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16 − 12) x 2 = 8]. Decoupling and External Components The NB3N501 requires a 0.01 mF decoupling capacitor to be connected between VDD and GND on pins 2 and 3. It must be connected close to the NB3N501 to minimize lead inductance. Control input pins can be connected to device pins VDD or GND, or to the VDD and GND planes on the board. Series Termination Resistor A 33 W terminating resistor can be used next to the CLK pin for trace lengths over one inch. ORDERING INFORMATION Package Shipping† NB3N501DG SOIC−8 (Pb−Free) 98 Units / Rail NB3N501DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 5 NB3N501 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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