NB3N51044DTR2G

NB3N51044 3.3 V, Crystal to 100 MHz / 125 MHz Quad HCSL / LVDS Clock Generator The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs (See Figure 10 for LVDS interface) of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network. All clock outputs can be individually enabled / disabled through hardware input pins OE[3:0]. In addition, device can be reset using Master Reset input pin MR_OE#. www.onsemi.com MARKING DIAGRAM TSSOP−28 DT SUFFIX CASE 948AA Features • • • • • • • • • • • • • Uses 25 MHz Fundamental Crystal or Reference Clock Input Four Low Skew HCSL or LVDS Outputs Output Frequency Selection of 100 MHz or 125 MHz Individual OE Tri−States Outputs Master Reset and BYPASS Modes PCIe Gen 1, Gen 2, Gen 3, Gen 4 Compliant Typical Phase Jitter @ 125 MHz (Integrated 1.875 MHz to 20 MHz): 0.2 ps Typical Cycle−Cycle Jitter @ 100 MHz (10k cycles): 20 ps Phase Noise @ 100 MHz: Offset Noise Power 100 Hz −101 dBc/Hz 1 kHz −123 dBc/Hz 10 kHz −133 dBc/Hz 100 kHz −136 dBc/Hz 1 MHz −141 dBc/Hz 10 MHz −155 dBc/Hz Operating Supply Voltage Range 3.3 V ±5% Industrial Temperature Range −40°C to +85°C Functionally Compatible with ICS841604I with enhanced performance These are Pb−Free Devices NB3N5 1044G ALYW A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Applications • • • • • End Products Networking Consumer Computing and Peripherals Industrial Equipment PCIe Clock Generation Gen 1, Gen 2, Gen 3 and Gen 4 © Semiconductor Components Industries, LLC, 2014 September, 2017 − Rev. 2 • • • • 1 Switch and Router Set Top Box, LCD TV Servers, Desktop Computers Automated Test Equipment Publication Order Number: NB3N51044/D NB3N51044 BLOCK DIAGRAM VDD BYPASS MR_OE# HCSL buffer CLK3 CLK3 OE3 HCSL buffer XIN 0 25 MHz Crystal XOUT Clock Buffer/ Cystal Oscillator Charge Pump Phase Detector 1 VCO Output Divider ($N) CLK2 OE2 HCSL buffer REF_IN CLK2 Feedback Divider CLK1 CLK1 OE1 CLK0 HCSL buffer CLK0 OE0 GND REF_SEL F_SEL Figure 1. Block Diagram PIN CONFIGURATION REF_SEL 1 28 VDD REF_IN 2 27 BYPASS VDD 3 26 IREF GND 4 25 F_SEL XIN 5 24 VDD XOUT 6 23 CLK3 MR_OE# 7 22 CLK3 VDD 8 21 CLK2 OE3 9 20 CLK2 OE2 10 19 GND OE1 11 18 CLK1 OE0 12 17 CLK1 GND 13 16 CLK0 VDD 14 15 CLK0 NB3N51044 Figure 2. Pin Configuration (Top View) www.onsemi.com 2 IREF NB3N51044 PIN DESCRIPTION Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 REF_SEL Input LVCMOS/ LVTTL level input to select input reference source. Pulldown with crystal as default reference input source. 2 REF_IN Input 25 MHz single−ended reference input clock. 3 VDD Power Positive supply voltage pin connected to +3.3 V typical supply voltage. 4 GND Ground Power supply ground 0 V. This pin provides GND return path for the device. 5 XIN Input 6 XOUT Output 7 MR_OE# Input 8 VDD Power 9 OE3 Input LVCMOS/ LVTTL level interface active High output enable pin for CLK3. Pulldown with default Low and output disabled. 10 OE2 Input LVCMOS/ LVTTL level interface active High output enable pin for CLK2. Pulldown with default Low and output disabled. 11 OE1 Input LVCMOS/ LVTTL level interface active High output enable pin for CLK1. Pulldown with default Low and output disabled. 12 OE0 Input LVCMOS/ LVTTL level interface active High output enable pin for CLK0. Pulldown with default Low and output disabled. 13 GND Ground Power supply ground 0 V. This pin provides GND return path for the device. 14 VDD Power Positive supply voltage pin connected to +3.3 V typical supply voltage. 15 CLK0 HCSL or LVDS Noninverted clock output. (For LVDS levels see Figure 10) output 16 CLK0 HCSL or LVDS Inverted clock output. (For LVDS levels see Figure 10) output 17 CLK1 HCSL or LVDS Noninverted clock output. (For LVDS levels see Figure 10) output 18 CLK1 HCSL or LVDS Inverted clock output. (For LVDS levels see Figure 10) output 19 GND 20 CLK2 HCSL or LVDS Noninverted clock output. (For LVDS levels see Figure 10) output 21 CLK2 HCSL or LVDS Inverted clock output. (For LVDS levels see Figure 10) output 22 CLK3 HCSL or LVDS Noninverted clock output. (For LVDS levels see Figure 10) output 23 CLK3 HCSL or LVDS Inverted clock output. (For LVDS levels see Figure 10) output 24 VDD Power 25 F_SEL Input LVCMOS/ LVTTL level Frequency Selects PCIe (100 MHz) when Low or sRIO (125 MHz) output frequency when High. Pulldown with default of 100 MHz at outputs. 26 IREF Output Output current reference pin. Connect to precision resistor (typical 475 W) to set internal current reference 27 BYPASS Input LVCMOS/ LVTTL level input. Selects PLL operation mode when Low or PLL bypass mode when High. Pulldown with default of PLL mode. 28 VDD Power Ground 25 MHz fundamental mode crystal input connection. Ground this pin when crystal not connected. 25 MHz crystal output. Float this pin when crystal not connected. Asynchronous LVCMOS/ LVTTL level input. When High, this pin acts as Master Reset to disable the output dividers and set outputs to high impedance (Hi−Z) mode. When Low, this pin acts as Output Enable for enabling the output buffers. Pulldown with default Low. Positive supply voltage pin connected to +3.3 V typical supply voltage. Power supply ground 0 V. This pin provides GND return path for the device. Positive supply voltage pin connected to +3.3 V typical supply voltage. Positive supply voltage pin connected to +3.3 V typical supply voltage. www.onsemi.com 3 NB3N51044 Table 2. OUTPUT FREQUENCY SELECT FUNCTION TABLE Input Table 5. INPUT REFERENCE SELECT FUNCTION TABLE Output REF_SEL 0 Crystal, at XIN and XOUT (default) 1 Single−ended reference clock at REF_IN F_SEL N (Output divider) CLK[3:0]/CLK[3:0]# 0 5 100MHz (PCIe, default) 1 4 125MHz (sRIO) Recommended Crystal Parameters Crystal Frequency Load Capacitance Shunt Capacitance, C0 Equivalent Series Resistance Initial Accuracy at 25°C Temperature Stability Aging Table 3. PLL BYPASS FUNCTION TABLE BYPASS PLL Configuration 0 PLL Enabled (default) 1 PLL bypassed, fout = fIN/N Table 4. MASTER RESET AND OE FUNCTION TABLE MR_OE# OEx [x=3:0] 0 (default) 0 (default) CLKx, CLKx# are High impedance 1 CLKx Output Enabled x Device reset, outputs disabled (Hi−Z) 1 Input Reference Fundamental AT−Cut 25 MHz 16−20 pF 7 pF Max 50 W Max ±20 ppm ±30 ppm ±20 ppm Function Table 6. ATTRIBUTES Characteristic Value ESD Protection Human Body Model 2 kV Internal Input Default State Resistor 51 kW Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 132,000 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 7. ABSOLUTE MAXIMUM RATING (Note 2) Symbol VDD Parameter Positive power supply with respect to GND Rating Unit +4.6 V VI Input Voltage with respect to device GND −0.5 V to VDD + 0.5 V V TA Operating Temperature Range −40 to +85 °C TSTG Storage temperature −65 to +150 °C TSOL Max. Soldering Temperature (10 sec) 265 °C qJA Thermal Resistance (Junction−to−ambient) 0 lfpm (Note 3) 500 lfpm 63 55 °C/W qJC Thermal Resistance (Junction−to−case) 50 °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). www.onsemi.com 4 NB3N51044 Table 8. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 5%, GND = 0 V, TA = −40°C to 85°C, Note 4) Symbol Parameter Min Typ Max Unit 3.135 3.3 3.465 V 126 mA 50 mA 2.0 VDD+0.3 V GND−0.3 0.8 V 150 mA VDD Power Supply Voltage IDD Power Supply Current when all outputs are ON, OE[3:0] = 1, FCLKOUT = 125 MHz IOFF Power Supply Current when all outputs are set OFF, OE[3:0] = 0 VIH Input HIGH Voltage (XIN, REF_IN, REF_SEL, BYPASS, F_SEL, MR_OE#) VIL Input LOW Voltage (XIN, REF_IN, REF_SEL, BYPASS, F_SEL, MR_OE#) IIH Input Leackage on logic High current at all input pins IIL Input Leackage on logic Low current at all input pins −5 VOH Output HIGH Voltage for HCSL output (Note 5) 660 VOL Output LOW Voltage for HCSL output (Note 5) −150 45 VMAX Absolute Maximum Voltage, Measured Single ended including overshoot (Notes 5, 6) VMIN Absolute Minimum Voltage, Measured Single ended including undershoot (Notes 5, 7) −300 Crossing Voltage Magnitude (Absolute) for HCSL output (Notes 5, 8, 9) 250 VCROSS Ring Back Voltage measured differentially (Note 11) 850 −100 mV mV 1150 DVCROSS Change in Magnitude of Vcross for HCSL Output (Notes 5, 8, 10) VRB mA mV mV 550 mV 150 mV 100 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor set at RREF = 475 W. See Figure 9. Guaranteed by characterization. 5. Measurement taken from single-ended waveform 6. Defined as the maximum instantaneous voltage value including positive overshoot 7. Defined as the maximum instantaneous voltage value including negative overshoot 8. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx-. 9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 10. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx-. This is maximum allowed variance in the VCROSS for any particular system. 11. Differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100 differential range. www.onsemi.com 5 NB3N51044 Table 9. AC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 5%, GND = 0 V, TA = −40°C to 85°C, Note 12) Symbol fCLKIN fCLKOUT FNOISE−100M FNOISE−125M tJIT(F)−100M tJIT(F)−125M Parameter Conditions Min Clock/ Crystal input frequency Phase Noise Performance at 125 MHz RMS Phase Jitter at 100 MHz Clock RMS Phase Jitter at 125 MHz Clock Max Unit 25 MHz 100 / 125 MHz @ 100 Hz offset from carrier −101 dBc/Hz @ 1 kHz offset from carrier −123 @ 10 kHz offset from carrier −133 @ 100 kHz offset from carrier −136 @ 1 MHz offset from carrier −141 @ 10 MHz offset from carrier −155 @ 100 Hz offset from carrier −98 @ 1 kHz offset from carrier −117 @ 10 kHz offset from carrier −130 @ 100 kHz offset from carrier −133 @ 1 MHz offset from carrier −141 @ 10 MHz offset from carrier −154 Output Frequency Phase Noise Performance at 100 MHz Typ Integration Range 1.875 MHz to 20 MHz 0.2 Integration Range 12 kHz to 20 MHz 0.4 Integration Range 1.875 MHz to 20 MHz 0.2 Integration Range 12 kHz to 20 MHz 0.4 dBc/Hz ps ps tJITTER−100M Peak Cycle−to−Cycle Jitter Measured at 100 MHz over 10000 cycles 20 ps tJITTER−125M Peak Cycle−to−Cycle Jitter Measured at 100 MHz over 10000 cycles 20 ps tR / tF Rise / Fall Time @ 100 MHz and 125 MHz Measured differentially between −150 mV to 150 mV with 2 pF Load, Figure 11 DtR/tF 0.6 4.0 V/ns Output Rise/ Fall time variation 125 ps tSKEW Within device output to output skew 40 ps tOE Output enable/disable time (Note 13) Measured at cross point tDC Output Clock Duty Cycle VDD = 3.3 V tPU Stabilization time from Power−up 10 45 50 3.0 ms 55 % mS NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 12. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W , RL = 49.9 W , with test load capacitance of 2 pF and current biasing resistor set at RREF = 475 W . See Figure 9. Guaranteed by characterization. 13. Output pins are tri−stated when OE is asserted LOW. Output pins are driven differentially when OE is HIGH unless device is in power down mode, PD = Low. www.onsemi.com 6 NB3N51044 Table 10. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS VDD = 3.3 V ± 5%, TA = −40°C to 85°C, fOUT = 100 MHz, 125 MHz Symbol tJ (PCIe Gen 1) tREFCLK_HF_RMS (PCIe Gen 2) tREFCLK_LF_RMS (PCIe Gen 2) tREFCLK_RMS (PCIe Gen 3) tREFCLK_RMS (PCIe Gen 4) Parameter Phase Jitter Peak−toPeak (Notes 15 and 18) Phase Jitter RMS (Notes 16 and 18) Phase Jitter RMS (Notes 16 and 18) Phase Jitter RMS (Notes 17 and 18) Phase Jitter RMS (Notes 17 and 18) Typ Max PCIe Industry Spec fCLKIN = 25 MHz Crystal, fCLKOUT = 100 MHz Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) for 106 clock periods 10 20 86 fCLKIN = 25 MHz Crystal, fCLKOUT = 125 MHz Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) for 106 clock periods 10 20 − fCLKIN = 25 MHz Crystal, fCLKOUT = 100 MHz Input High Band: 1.5 MHz − Nyquist (clock frequency/2) 1.0 1.8 3.1 fCLKIN = 25 MHz Crystal, fCLKOUT = 125 MHz Input High Band: 1.5 MHz − Nyquist (clock frequency/2) 0.8 1.0 − fCLKIN = 25 MHz Crystal, fCLKOUT = 100 MHz Input Low Band: 10 kHz − 1.5 MHz 0.10 0.15 3.0 fCLKIN = 25 MHz Crystal, fCLKOUT = 125 MHz Input Low Band: 10 kHz − 1.5 MHz 0.08 0.15 − fCLKIN = 25 MHz Crystal, fCLKOUT = 100 MHz Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) 0.35 0.70 0.8 fCLKIN = 25 MHz Crystal, fCLKOUT = 125 MHz Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) 0.17 0.22 − 0.35 0.5 0.5 Test Condition Min f = 100 MHz, 25 MHz Crystal Input Evaluation Band: 0 Hz − Nyquist (clock frequency/2) SSOFF Unit ps ps ps ps ps 14. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. 15. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps peak−to−peak for a sample size of 106 clock periods. 16. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). 17. RMS jitter after applying system transfer function for the common clock architecture. 18. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W , RL = 49.9 W , with test load capacitance of 2 pF and current biasing resistor set at RREF = 475 W . See Figure 9. This parameter is guaranteed by characterization. Not tested in production. www.onsemi.com 7 NB3N51044 NOISE POWEER (dBc/Hz) PHASE NOISE OFFSET FREQUENCY (Hz) NOISE POWEER (dBc/Hz) Figure 3. Typical Phase Noise Plot at 100 MHz (fCLKIN = 25 MHz Crystal , fCLKOUT = 100 MHz, RMS Phase Jitter = 172 fs for Integration Range of 1.875 MHz to 20 MHz, Output Termination = HCSL type) OFFSET FREQUENCY (Hz) Figure 4. Typical Phase Noise Plot at 125 MHz (fCLKIN = 25 MHz Crystal , fCLKOUT = 125 MHz, RMS Phase Jitter = 155 fs for Integration Range of 1.875 MHz to 20 MHz, Output Termination = HCSL type) www.onsemi.com 8 NB3N51044 NOISE POWEER (dBc/Hz) PHASE NOISE OFFSET FREQUENCY (Hz) NOISE POWEER (dBc/Hz) Figure 5. Typical Phase Noise Plot at 100 MHz (fCLKIN = 25 MHz Crystal , fCLKOUT = 100 MHz, RMS Phase Jitter = 389 fs for Integration Range of 12 kHz to 20 MHz, Output Termination = HCSL type) OFFSET FREQUENCY (Hz) Figure 6. Typical Phase Noise Plot at 125 MHz (fCLKIN = 25 MHz Crystal , fCLKOUT = 125 MHz, RMS Phase Jitter = 383 fs for Integration Range of 12 kHz to 20 MHz, Output Termination = HCSL type) www.onsemi.com 9 NB3N51044 APPLICATION INFORMATION Crystal Input Interface as nominal values, assuming approximately 2 pF of stray capacitance per trace and approximately 8 pF of internal capacitance. CL = (C1 + Cstray + Cin) / 2; C1 = C2 The frequency accuracy and duty cycle skew can be fine-tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Figure 7 shows the NB3N51044 device crystal oscillator interface using a typical parallel resonant crystal. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors, C1 and C2, need to consider the stray capacitances of the board and are used to match the nominally required crystal load capacitance CL. A parallel crystal with loading capacitance CL = 18 pF would use C1 = 26 pF and C2 = 26 pF C1 = 26 pF X1 Fundamental Mode Parallel Resonant Crystal 18 pF Load X2 C2 = 26 pF Figure 7. Crystal Interface Loading Power Supply Filter capacitors as close as possible to the device to minimize lead inductance. In order to isolate the NB3N51044 from system power supply, noise decoupling is required. The 10 mF and a 0.1 mF cap from supply pins to GND decoupling capacitor has to be connected between VDD (pins 3, 8, 14, 24 and 28) and GND (pins 4, 13 and 19). It is recommended to place decoupling Termination The output buffer structure is shown in the Figure 8. 2.6 mA 14 mA IREF RREF CLKx CLKx HCSL / LVDS termination 475 W Figure 8. Simplified Output Structure www.onsemi.com 10 NB3N51044 interface may not require the 100 W near the LVDS receiver if the receiver has internal 100 W termination. An optional series resistor RL may be connected to reduce the overshoots in case of impedance mismatch. The outputs can be terminated to drive HCSL receiver (see Figure 9) or LVDS receiver (see Figure 10). HCSL output interface requires 49.9 W termination resistors to GND for generating the output levels. LVDS output HCSL INTERFACE CLK0 RL* = 33.2 W Zo = 50 W RL* = 33.2 W Zo = 50 W CLK0 RL = 49.9 W RL = 49.9 W RL = 49.9 W RL = 49.9 W HCSL Receiver NB3N51044 CLK1 RL* = 33.2 W Zo = 50 W RL* = 33.2 W Zo = 50 W CLK1 IREF *Optional RREF = 475 W Figure 9. Typical Termination for HCSL Output Driver and Device Evaluation LVDS COMPATIBLE INTERFACE CLK0 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W 100 W** Zo = 50 W CLK0 RL = 150 W RL = 150 W NB3N51044 CLK1 RL* = 33.2 W Zo = 50 W 100 W RL* = 33.2 W CLK1 IREF RREF = 475 W LVDS Receiver 100 W** Zo = 50 W *Optional **Not required if LVDS receiver has 100 W internal termination RL = 150 W RL = 150 W LVDS Device Load Figure 10. Typical Termination for LVDS Device Load www.onsemi.com 11 NB3N51044 150 mV 0 mV 150 mV tR tF Figure 11. HCSL Differential Measurement of tR/tF ORDERING INFORMATION Temperature Package Shipping† NB3N51044DTG −40°C to 85°C TSSOP−28 (Pb−Free) 96 Units / Rail NB3N51044DTR2G −40°C to 85°C TSSOP−28 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP28 CASE 948AA ISSUE A DATE 26 OCT 2011 SCALE 1:1 e 28 PIN ONE LOCATION 2X 0.20 C B A ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 15 DETAIL A E1 E 1 14 A 0.05 DIM A A1 A2 b b1 c c1 D E E1 e L L1 R R1 S 01 02 03 A A2 A D 0.10 C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. B A SEATING PLANE C 28X A1 b 02 0.10 C B A S H ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ R1 (b) c R GAUGE PLANE c1 0.25 b1 03 SECTION A−A L (L1) GENERIC MARKING DIAGRAM* 01 XXXXX XXXXG ALYW DETAIL A RECOMMENDED SOLDERING FOOTPRINT 28X MILLIMETERS MIN MAX −−− 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 9.60 9.80 6.40 BSC 4.30 4.50 0.65 BSC 0.45 0.75 1.00 REF 0.09 −−− 0.09 −−− 0.20 −−− 0_ 8_ 12 _REF 12 _REF 0.42 XXXXX A L Y W G 28X 1.15 6.70 0.65 PITCH DOCUMENT NUMBER: DESCRIPTION: *This information is generic. Please refer to device data sheet for actual part marking. DIMENSIONS: MILLIMETERS 98AON13023D = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 28 LEAD TSSOP, 9.7X4.4X1.0 MM, 0.65 PITCH PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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