NB3N511DG

NB3N511 PLL Clock Multiplier, 14 MHz - 200 MHz, 3.3 V / 5.0 V Description www.onsemi.com The NB3N511 is a clock multiplier that will generate one of nine selectable output multiples of an input frequency via two 3−level select inputs (S0, S1). It accepts a standard fundamental mode crystal or an external reference clock signal. Phase−Locked−Loop (PLL) design techniques are used to produce a low jitter, TTL level clock output up to 200 MHz with a 50% duty cycle. An Output Enable (OE) pin is provided, and when asserted low, the clock output goes into tri −state (high impedance). The NB3N511 is commonly used in electronic systems as a cost efficient replacement for crystal oscillators MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 3N511 A L Y W G Features • • • • • • • • • • • • • Clock Output Frequencies up to 200 MHz Nine Selectable Multipliers of the Input Frequency Operating Range: VDD = 3.3 V ±10% or 5.0 V ±5% Low Jitter Output of 25 ps One Sigma (rms) Zero ppm Clock Multiplication Error 45% − 55% Output Duty Cycle TTL/CMOS Output with 25 mA TTL Level Drive Crystal Reference Input Range of 5 − 32 MHz Input Clock Frequency Range of 1 − 50 MHz OE, Output Enable with Tri−State Output 8−Pin SOIC Industrial Temperature Range −40°C to +85°C These are Pb−Free Devices 8 1 1 3N511 ALYWG G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. VDD X1/ICLK Crystal Oscillator crystal or clock CLX2 CLX1 X2 ÷P Charge Pump Phase Detector Multiplier Select ÷M S1 S0 January, 2019 − Rev. 5 TTL/ CMOS Output CLKOUT Feedback OE GND © Semiconductor Components Industries, LLC, 2013 VCO Figure 1. NB3N511 Logic Diagram 1 Publication Order Number: NB3N511/D NB3N511 Table 1. CLOCK MULTIPLIER SELECT TABLE S1* S0* CLKOUT Multiplier L L 4X Input L M 5.333X Input L H 5X Input M L 2.5X Input M M 2X Input M H 3.333X Input H L 6X Input H M 3X Input H H 8X Input X1/ICLK 1 8 X2 VDD 2 7 OE GND 3 6 S0 S1 4 5 CLKOUT Figure 2. NB3N511 Package Pinout, 8−Pin (150 mil) SOIC (Top View) *Pins S1 and S0 default to M when open L = GND H = VDD M = OPEN (unconnected; will default to VDD/2) Table 2. PIN DESCRIPTION Pin # Name I/O 1 X1/ICLK Crystal or LVCMOS/LVTTL Input 2 VDD Power supply Positive supply voltage 3 GND Power supply 0 V. Ground. 4 S1 Three level Input Multiplier select pin − connect to VDD, GND or float 5 CLKOUT LVCMOS/LVTTL Output Clock output Multiplier select pin − connect to VDD, GND or float 6 S0 Three level Input 7 OE LVCMOS/LVTTL Input 8 X2 Crystal Description Crystal or external reference clock input Output Enable. CLKOUT is high impedance when OE is low. Internal pullup Crystal input – Leave open when providing an external clock reference Table 3. COMMON OUTPUT FREQUENCY EXAMPLES Table 4. COMMON OUTPUT FREQUENCY EXAMPLES Output Frequency (MHz) Input Frequency (MHz) S1, S0 Output Frequency (MHz) Input Frequency (MHz) S1, S0 20 10 M, M 66.66 20 M, H 24 12 M, M 72 12 H, L 30 10 H, M 75 25 H, M 32 16 M, M 80 10 H, H 25 M, H 33.33 16.66 M, M 83.33 37.5 15 M, L 90 15 H, L 40 10 L, L 100 20 L, H 48 12 L, L 120 15 H, H 50 20 M, L 125 25 L, H 60 10 H, L 133.3 25 L, M L, L 150 25 H, L 64 16 www.onsemi.com 2 NB3N511 Table 4. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model Charged Device Model > 1 kV > 150 V > 1 kV RPU − OE Input Pull−up Resistor 270 kW Moisture Sensitivity (Note 1) SOIC−8 Flammability Rating Oxygen Index: 28 to 34 Level 1 UL 94 V 0 @ 0.125 in Transistor Count 9555 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter Rating Unit 7 V −0.5 V v VIO v VDD + 0.5 V Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) SOIC−8 41 to 44 °C/W Tsol Wave Solder 265 °C VDD Positive Power Supply VIO Input and Output Voltages TA Condition 1 Condition 2 GND = 0 V Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 3 NB3N511 Table 6. DC CHARACTERISTICS VDD = 3.3 V ±10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, TA = −40°C to +85°C Symbol Characteristic Min VDD Operating Voltage VDD = 5 V VDD = 3.3 V IDD Power Supply Current – Inputs and outputs open, CLKOUT operating at 100 MHz (with 20 MHz crystal) VDD = 5 V VDD = 3.3 V VOH Output HIGH Voltage IOH = −4 mA CMOS High VOH Output HIGH Voltage IOH = −25 mA TTL High VOL Output LOW Voltage IOL = 25 mA VIH Input HIGH Voltage, ICLK only (pin 1) VDD = 5 V VDD = 3.3 V VIL Input LOW Voltage, ICLK only (pin 1) VDD = 5 V VDD = 3.3 V VIH Input HIGH Voltage, S0, S1 VIL Input LOW Voltage, S0, S1 VIH Input HIGH Voltage, OE (pin 7) VIL Input LOW Voltage, OE (pin 7) Cin Input Capacitance, S0, S1 and OE ISC Typ 4.75 3.0 Max Unit 5.25 3.6 V mA 9 8 VDD − 0.4 V 2.4 V 0.4 (VDD / 2) + 1 (VDD / 2) + 0.7 V V (VDD / 2) − 1 (VDD / 2) − 0.7 VDD − 0.5 V V 0.5 2.0 V V 0.8 V 4 pF Output Short Circuit Current, CLKOUT ±70 mA Nominal Output Impedance 20 W Table 7. AC CHARACTERISTICS VDD = 3.3 V ±10% or 5.0 V ± 5% unless otherwise noted, GND = 0 V, TA = −40°C to +85°C Symbol Max Unit Crystal Input Frequency (Note 3) 5 32 MHz Clock Input Frequency 1 50 MHz fOUT Output Frequency Range fOUTMIN ≤ fIN x Multiplier ≤ fOUTMAX VDD = 4.25 to 5.25 V (5.0 V ± 5%) VDD = 3.0 to 3.6 V (3.3 V ± 10%) 4 4 200 200 45 fXtal fCLKIN Characteristic Min Typ DC Output Clock Duty Cycle at 1.5 V OEH Output enable time, OE high to output on 50 ns OEL Output disable time, OE low to tri−state 50 ns Period Jitter (rms, 1 s) 25 ps Total Period Jitter, (peak−to−peak) ±70 ps tjitter (rms) tjitter (pk−to−pk) tr/tf Output rise/fall time (0.8 V to 2.0 V) (measured with 15 pF load) 50 1 55 MHz 1.5 % ns 3. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1/CLK to GND and X2 to GND. The value of these capacitors is given by the following equation, where CL is the specified crystal load capacitance: Crystal capacitance (pF) = (CL − 12) X 2. So, for a crystal with 16 pF load capacitance, use two 8 pF capacitors. www.onsemi.com 4 NB3N511 APPLICATIONS INFORMATION High Frequency CMOS/TTL Oscillators small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL − 12 pF) * 2. In this equation, CL = crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16 − 12) x 2 = 8]. The NB3N511, along with a low frequency fundamental mode crystal, can build a high frequency TTL output oscillator. For example, a 20 MHz crystal connected to the NB3N511 with the 5X output selected (S1 = L, S0 = H) produces an 100 MHz CMOS/TTL output clock. Decoupling and External Components The NB3N511 requires a 0.01 mF decoupling capacitor to be connected between VDD and GND on pins 2 and 3. It must be connected close to the NB3N511 to minimize lead inductance. Control input pins can be connected to device pins VDD or GND, or to the VDD and GND planes on the board. Table 8. RECOMMENDED CRYSTAL PARAMETERS Series Termination Resistor A 33 W terminating resistor can be used next to the CLK pin for trace lengths over one inch. Parameter Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant. Crystal load capacitors should be connected from pins X1 to ground and X2 to ground to optimize the frequency accuracy, See Figure 1. The total on chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance Load Capacitance 18 pF Operating Range −40 to +85°C Shunt Capacitance 5 pF Max Equivalent Series Resistance (ESR) Correlation Drive Level 50 W Max 1.0 mW Max ORDERING INFORMATION Package Shipping† NB3N511DG SOIC−8 (Pb−Free) 98 Units / Rail NB3N511DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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