NB3N853501EDTR2G

NB3N853501E 3.3 V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs with Clock Enable and Clock Select http://onsemi.com MARKING DIAGRAM Description The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. Outputs are LVPECL levels and are synchronously enabled by CLK_EN using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output). Features • • • • • • • • • • • • Four differential LVPECL Outputs Two Selectable LVCMOS/LVTTL CLOCK Inputs Up to 266 MHz Clock Operation Output to Output Skew: 30 ps (Max.) Device to Device Skew 250 ps (Max.) Propagation Delay 2.0 ns (Max.) Operating range: VCC = 3.3 ±5% V( 3.135 to 3.465 V) Additive Phase Jitter, RMS: 62 fs (Typ) Synchronous Clock Enable Control Industrial Temp. Range (−40°C to 85°C) Pb−Free TSSOP20 Package These are Pb−Free Devices TSSOP−20 DT SUFFIX CASE 948E A L Y W G NB3N 501E ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2011 November, 2011 − Rev. 2 1 Publication Order Number: NB3N853501E/D NB3N853501E VEE 1 20 Q0 CLK_EN 2 19 Q0 CLK_SEL 3 18 VCC CLK0 4 17 Q1 nc 5 16 Q1 CLK1 6 15 Q2 nc 7 14 Q2 nc 8 13 VCC nc 9 12 Q3 10 11 Q3 VCC Figure 2. Pinout Diagram (Top View) Table 1. PIN DESCRIPTION Open Default Number Name I/O Description 1 VEE 2 CLK_EN LVCMOS / LVTTL Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are disabled (Qx HIGH, Qx LOW) 3 CLK_SEL LVCMOS / LVTTL Pulldown Clock Input Select (HIGH selects CLK1, LOW selects CLK0 input) 4 CLK0 LVCMOS / LVTTL Pulldown Clock 0 Input. Float open when unused. 5, 6, 8, 9 nc 6 CLK1 10, 13, 18 VCC 11, 14, 16, 19 Q[3:0] LVPECL Invert Differential Outputs 12, 15, 16, 20 Q[3:0] LVPECL True Differential Outputs Negative (Ground) Power Supply pin must be externally connected to power supply to guarantee proper operation. No Connect LVCMOS / LVTTL Pulldown Clock 1 Input. Float open when unused. Positive Power Supply pins must be externally connected to power supply to guarantee proper operation. Table 2. FUNCTIONS Inputs Outputs CLK_EN CLK_SEL Input Function Output Function Qx Qx 0 0 CLK0 input selected Disabled LOW HIGH 0 1 CLK1 Input Selected Disabled LOW HIGH 1 0 CLK0 input selected Enabled CLK0 Invert of CLK1 1 1 CLK1 Input Selected Enabled CLK1 Invert of CLK1 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3. http://onsemi.com 2 NB3N853501E Figure 3. CLK_EN TIMING DIAGRAM Table 3. ATTRIBUTES (Note 2) Characteristics Value Internal Input Pullup Resistor 50 kW Internal Input Pulldown Resistor 50 kW ESD Protection Human Body Model Machine Model > 2 kV > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level 1 Flammability Rating Oxygen Index UL 94 V−0 @ 0.125 in 28 to 34 Transistor Count 317 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition 1 Condition 2 Rating Unit 4.6 V −0.5 v VI v VCC + 0.5 V 4 pF 50 100 mA −40 to v +85 °C −65 to +150 °C VCC Supply Voltage Vin Input Voltage Cin Input Capacitance Iout Output Current TA Operating Temperature Range, Industrial Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−20 140 50 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm Single−Layer PCB (700 mm2, 2 oz) 128 °C/W 200 lfpm Multi−Layer PCB (700 mm2, 2 oz) 94 (Note 4) TSSOP−20 23 to 41 °C/W 265 °C Continuous Surge qJC Thermal Resistance (Junction−to−Case) Tsol Wave Solder Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 3 NB3N853501E Table 5. DC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), GND = 0 V, TA = −40°C to +85°C (Note 5) Symbol Characteristic Min IEE Power Supply Current VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input High Current (VCC = Vin = 3.456 V) CLKx, CLK_SEL CLK_EN IIL Input LOW Current (VCC = 3.456 V; Vin = GND) CLKx, CLK_SEL CLK_EN CLK0 CLK1 CLK_EN CLK_SEL Typ Max Unit 50 mA 2 VCC + 0.3 V −0.3 −0.3 1.3 0.8 V 150 5 mA −5 −150 mA VOH Output HIGH Voltage VCC − 1.4 VCC − 0.9 V VOL Output LOW Voltage VCC − 2.0 VCC − 1.7 V 0.6 1.0 V VOUTSWING Output Voltage Swing (peak−to−peak) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Outputs terminated 50 W to VCC − 2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise. http://onsemi.com 4 NB3N853501E Table 6. AC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), GND = 0 V, TA = −40°C to +85°C (Note 6) Symbol Max Unit 0 266 MHz Propagation Delay 0.9 2.0 ns tSKEWDC Duty Cycle Skew same path similar conditions at 50 MHz 48 52 % tSKEWO−O Output to Output Skew Within A Device 30 ps tSKEWD−D Device−to−Device Skew similar path and conditions 250 ps FMAX tPD Characteristic Min Maximum Operating Frequency tJIT Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to 20 MHz) See Figure 6. tr/tf Output rise and fall times @ 266 MHz (20% and 80% points) Typ 50 0.062 240 ps 700 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Outputs terminated 50 W to VCC − 2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise. Measured from Input Midpoint (VDD/2) to differential Output crosspoints, see Figure 5. Figure 4. Typical Test Setup and Termination for Evaluation. The VCC of 2.0 V and VEE of −1.3 ±0.165 V Split supply allows a direct connection to an oscilloscope 50 W impedance input module. Also reference AND8020. http://onsemi.com 5 NB3N853501E Figure 5. AC Measurement Reference http://onsemi.com 6 NB3N853501E Figure 6. For 155.52 MHz carrier, the NB3N853501E Additive Phase Noise (dBc/Hz) verses SSB Offset Frequency (Hz) Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 93.3 fs RMS. The E8663B Source Generator Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where tJIT = /(tJIToutput)2 − (tJITinput)2 = 61.6 fs ORDERING INFORMATION Package Shipping† NB3N853501EDTG TSSOP−20 (Pb−Free) 75 Units / Rail NB3N853501EDTR2G TSSOP−20 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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