NB3V110xC Series
3.3V/2.5V/1.8V LVCMOS
Low Skew Fanout Buffer
Family
Description
The NB3V110xC are a modular, high−performance, low−skew,
general purpose LVCMOS clock buffer family. The family of devices
is designed with a modular approach. Four different fan−out
variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices
are pin compatible to each other for easy handling. All family
members share the same high performing characteristics like low
additive jitter, low skew, and wide operating temperature range. The
NB3V110xC supports an asynchronous output enable control (OE)
which switches the outputs into a low state when OE is low. The
NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment
and are characterized for operation from −40°C to 105°C.
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TSSOP−14
DT SUFFIX
CASE 948G
TSSOP−8
DT SUFFIX
CASE 948S
WDFN8, 2x2
MT SUFFIX
CASE 511AT
Features
•
•
•
•
•
•
•
•
Operating Temperature Range: –40°C to 105°C
High−Performance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer
Available in 8−, 14−, 16−Pin TSSOP and WDFN8 Packages
Very Low Output−to−Output Skew < 50 ps
Very Low Additive Jitter < 200 fs
Supply Voltage: 3.3 V, 2.5 V or 1.8 V
fmax = 250 MHz for 3.3 V; fmax = 180 MHz for 2.5 V;
fmax = 133 MHz for 1.8 V
These Devices are Pb−Free and are RoHS Compliant
TSSOP−16
DT SUFFIX
CASE 948F
MARKING DIAGRAMS
8
16
14
1108
V
ALYWG
G
1106
V
ALYWG
G
10x
YWW
AG
1
1
TSSOP−8
1
TSSOP−14
TSSOP−16
BLOCK DIAGRAM
1
CLKIN
LV
CMOS
LV
CMOS
Q0
LV
CMOS
Q1
LV
CMOS
Q2
LV
CMOS
Q3
0X MG
G
WDFN8
A
= Assembly Location
M
= Date Code
L
= Wafer Lot
Y
= Year
W, WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
S
S
S
LV
CMOS
ORDERING INFORMATION
Qn
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
OE
© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. 3
1
Publication Order Number:
NB3V1102C/D
NB3V110xC Series
CLKIN
1
OE
2
Q0
3
GND
4
NB3V1102C
NB3V1103C
NB3V1104C
8
Q1
7
NC/Q3
6
VDD
5
NC/Q2
TSSOP−8 and WDFN8
CLKIN
1
14
OE
2
13
CLKIN
1
16
Q1
Q1
OE
2
15
Q3
Q3
Q0
3
14
VDD
4
13
Q2
12
GND
Q0
3
12
VDD
GND
GND
4
11
Q2
VDD
5
VDD
5
10
GND
Q4
6
GND
7
NB3V1106C
9
Q5
8
VDD
NB3V1108C
Q4
6
11
Q5
GND
7
10
VDD
Q6
8
9
TSSOP−14
Q7
TSSOP−16
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
LVCMOS Clock
Input
LVCMOS Clock
Output Enable
LVCMOS Clock Output
Device
Supply Voltage
Device
Ground
Devices
CLKIN
OE
Q0, Q1, ... Q7
VDD
GND
NB3V1102C
1
2
3, 8
6
4
NB3V1103C
1
2
3, 8, 5
6
4
NB3V1104C
1
2
3, 8, 5, 7
6
4
NB3V1106C
1
2
3, 14, 11, 13, 6, 9
5, 8, 12
4, 7, 10
NB3V1108C
1
2
3, 16, 13, 15, 6, 11, 8, 9
5, 10, 14
4, 7, 12
NOTE: Pins not mentioned in the table are NC.
Table 2. OUTPUT LOGIC TABLE
INPUTS
OUTPUTS
CLKIN
OE
Qn
X
L
L
L
H
L
H
H
H
Table 3. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model (HBM) per ANSI/ESDA/JEDEC JS−001−2014
Charged Device Model (CDM) per ANSI/ESDA/JEDEC JS−002−2014
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Value
Unit
5000
1500
V
V
Level 1
−
Meets or exceeds JEDEC Spec JESD78D (LU) IC Latchup Test
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm2, 2 oz.)
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2
NB3V110xC Series
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 2)
Over operating free−air temperature range (unless otherwise noted)
Symbol
Condition
Value
Unit
–0.5 to 4.6
V
VDD
Supply Voltage Range
VIN
Input Voltage Range (Note 3)
–0.5 to VDD + 0.5
V
VO
Output Voltage Range (Note 3)
–0.5 to VDD + 0.5
V
IIN
Input Current
±20
mA
IO
Continuous Output Current
qJA
Thermal Resistance (Junction−to−Ambient)
±50
mA
TSSOP−8
151.2*
°C/W
TSSOP−14
104*
32*
TSSOP−16
WDFN8
qJC
TJ
TSTG
Thermal Resistance (Junction−to−Case top)
Maximum Junction Temperature
Storage Temperature Range
110**
190**
TSSOP−8
35
TSSOP−14
8.6
TSSOP−16
10
WDFN8
10
°C/W
125
°C
–65 to 150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm2, 2 oz.)
3. For additional information, see Application Note AND8003/D.
*JEDEC51.7 four layer PCB with 100 sqmm, 2 oz with two 80x80x1oz ground planes.
**JEDEC51.3 two layer PCB with 100 sqmm, 2 oz.
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3
NB3V110xC Series
Table 5. RECOMMENDED OPERATING CONDITIONS
Over operating free−air temperature range (unless otherwise noted)
Condition
Symbol
VDD
VIL
VIH
Vth
tr / tf
tw
fCLK
Supply voltage range
Min
Typ
Max
Unit
3.0
3.3
3.6
V
2.5 V supply
2.3
2.5
2.7
1.8 V supply
1.71
1.8
1.89
3.3 V supply
Low−level input voltage
High−level input voltage
Input threshold voltage
VDD = 3.0 V to 3.6 V
VDD/2 –
600
VDD = 2.3 V to 2.7 V
VDD/2 –
400
VDD = 1.71 V to 1.89 V
0.3xVDD
VDD = 3.0 V to 3.6 V
VDD/2 +
600
VDD = 2.3 V to 2.7 V
VDD/2 +
400
VDD = 1.71 V to 1.89 V
0.7xVDD
V
V
VDD = 1.71 V to 1.89 V
VDD/2
V
4
1.8
VDD = 2.3 V to 2.7 V
2.75
VDD = 1.71 V to 1.89 V
3.75
VDD = 3.0 V to 3.6 V
DC
250
VDD = 2.3 V to 2.7 V
DC
180
DC
133
–40
105
Operating free−air temperature
V/ns
ns
VDD = 3.0 V to 3.6 V
VDD = 1.71 V to 1.89 V
TA
mV
VDD/2
1
LVCMOS clock Input Frequency
V
VDD = 2.3 V to 3.6 V
Input slew rate (Note 4)
Minimum pulse width at CLKIN
mV
MHz
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Guaranteed by Design.
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4
NB3V110xC Series
Table 6. DEVICE CHARACTERISTICS Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V
0.2
mA
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
2.7 V
0.2
OE = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
1.89 V
0.2
OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C)
60
OE = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD =
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C)
75
OVERALL PARAMETERS FOR ALL VERSIONS
IDD
IPD
CPD
II
Static device current
Power down current
Power dissipation capacitance per output (Note 6)
Input leakage current at OE
VDD = 3.3 V; f = 10 MHz
9
VDD = 2.5 V; f = 10 MHz
9
VDD = 1.8 V; f = 10 MHz
9
±8
Input leakage current at OE, CLKIN
VI = 0 V or VDD, VDD = 1.89 V
Output impedance
VDD = 3.3 V
40
VDD = 2.5 V
45
VDD = 1.8 V
fOUT
Output frequency
mA
±8
Input leakage current at CLKIN
ROUT
pF
±8
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
mA
W
60
VDD = 3.0 V to 3.6 V
DC
250
VDD = 2.3 V to 2.7 V
DC
180
VDD = 1.71 V to 1.89 V
DC
133
VDD = 3 V, IOH = –0.1 mA
2.9
VDD = 3 V, IOH = –8 mA
2.5
VDD = 3 V, IOH = –12 mA
2.2
MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V + 0.3 V
VOH
VOL
High−level output voltage
Low−level output voltage
VDD = 3 V, IOL = 0.1 mA
0.1
VDD = 3 V, IOL = 8 mA
0.5
VDD = 3 V, IOL = 12 mA
tPLH, tPHL
tsk(o)
V
Propagation delay (Note 7)
CLKIN to Qn
Output skew (Note 7)
Equal load of each output 85°C
0.8
0.8
Equal load of each output 105°C
tr/tf
Rise and fall time
20%–80% (VOH − VOL)
tDIS
Output disable time (Note 7)
tEN
Output enable time (Note 7)
tsk(p)
Pulse skew; tPLH(Qn) – tPHL(Qn) (Note 8)
To be measured with input duty cycle of 50%
tsk(pp)
Part−to−part skew
Tjit(f)
Additive jitter rms
V
2.0
ns
50
ps
60
0.12
0.8
ns
OE to Qn
6
ns
OE to Qn
6
ns
180
ps
Under equal operating conditions for two parts
0.5
ns
12 kHz...20 MHz fOUT = 100 MHz
100
fs
12 kHz...20 MHz fOUT = 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 W to VDD/2 (see Figure 2).
6. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] Pstat = VDD x IDD [W]
Pdyn = CPD x VDD2 x ƒ x n [W]
PCload = Cload x VDD2 x ƒ x n [W]
n = Number of switching output pins
7. With rail to rail input clock.
8. tsk(p) depends on output rise− and fall−time (tr/tf). The output duty−cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse−width of ideal output waveform and tperiod is 1/fOUT.
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5
NB3V110xC Series
Table 7. DEVICE CHARACTERISTICS (continued)
Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Parameter
Symbol
Condition
Min
VDD = 2.3 V, IOH = –0.1 mA
2.2
VDD = 2.3 V, IOH = –8 mA
1.7
Typ
Max
Unit
OUTPUT PARAMETERS FOR VDD = 2.5 V + 0.2 V
VOH
VOL
tPLH, tPHL
tsk(o)
High−level output voltage
Low−level output voltage
VDD = 2.3 V, IOL = 0.1 mA
0.1
VDD = 2.3 V, IOL = 8 mA
0.5
Propagation delay (Note 10)
CLKIN to Qn
Output skew (Note 10)
Equal load of each output 85°C
1.8
Rise and fall time
20%–80% (VOH − VOL)
tDIS
Output disable time (Note 10)
tEN
Output enable time (Note 10)
– tPHL(Qn)
V
ns
50
Equal load of each output 105°C
tr/tf
tPLH(Qn)
V
ps
60
0.12
1.2
ns
OE to Qn
10
ns
OE to Qn
10
ns
To be measured with input duty cycle of 50%
220
ps
tsk(p)
Pulse skew ;
(Note 9)
tsk(pp)
Part−to−part skew
Under equal operating conditions for two
parts
1.2
ns
tjit(f)
Additive jitter rms
12 kHz...20 MHz fOUT = 100 MHz
150
fs
12 kHz...20 MHz fOUT = 156.25 MHz
100
OUTPUT PARAMETERS FOR VDD = 1.8 V + 5%
VOH
High−level output voltage
VDD = 1.71 V, IOH = –0.1 mA
VDD = 1.71 V, IOH = –4 mA
VOL
Low−level output voltage
0.75xVDD
VDD = 1.71 V, IOL = 0.1 mA
0.1
VDD = 1.71 V, IOL = 4 mA
tPLH, tPHL
Propagation delay (Note 10)
CLKIN to Qn
Output skew (Note 10)
Equal load of each output
tr/tf
Rise and fall time
20%–80% (VOH − VOL)
tDIS
Output disable time (Note 10)
tEN
Output enable time (Note 10)
tsk(o)
tPLH(Qn)
– tPHL(Qn)
V
1.6
V
0.25xVDD
1.8
3.5
ns
75
ps
1.2
ns
OE to Qn
10
ns
OE to Qn
10
ns
To be measured with input duty cycle of 50%
450
ps
0.17
tsk(p)
Pulse skew ;
(Note 9)
tsk(pp)
Part−to−part skew
Under equal operating conditions for two
parts
1.2
ns
tjit(f)
Additive jitter rms
12 kHz...20 MHz, fOUT = 100 MHz
200
fs
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. tsk(p) depends on output rise− and fall−time (tr/tf). The output duty−cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse−width of ideal output waveform and tperiod is 1/fOUT.
10. With rail to rail input clock.
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6
NB3V110xC Series
PARAMETERS MEASUREMENT INFORMATION
VDD = 3.3 V, 2.5 V or 1.8 V
LVCMOS
Output
ZO = 50 Ω
R=50 W
C=2pF
parasitic capacitance
from Measurement Equipment
VDD/2
Figure 2. Test Load Circuit
VDD
VDD = 3.3 V, 2.5V or 1.8 V
R=100 W
LVCMOS
Output
ZO = 50 Ω
parasitic input capacitance
R=100 W
Figure 3. Application Load with 50 W Line Termination
VDD = 3.3 V, 2.5 V or 1.8 V
RS = 10 Ohms (VDD = 3.3 V)
RS = 5 Ohms (VDD = 2.5 V)
RS = 0 Ohms (VDD = 1.8 V)
LVCMOS
Output
ZO = 50 Ω
parasitic input capacitance
Figure 4. Application Load with Series Line Termination
VIN /2
VDD /2
Qn
OE
VIN /2
VDD /2
Qn+1
Qn
tDIS
tsk(o)
tEN
Figure 5. tDIS and tEN for Disable Low
tsk(o)
Figure 6. Output Skew tSk(o)
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7
NB3V110xC Series
V DD / 2
CLKIN
CLKIN
VOH
80% V OH −V OL
Qn
V DD / 2
20% V OH −V OL
Qn
V OL
t PLH
tr
tf
t PHL
Note: tsk(p) = |tPLH − tPHL|
Figure 7. Pulse Skew tsk(p) and Propagation Delay
tPLH/tPHL
Figure 8. Rise/Fall Times tr /tf
r
F_carrier
= 100 MHz
Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 66.92 fs
Input Source Phase Jitter = 36.72 fs
Output (DUT + Source)
Input Source
Output
Input Source 100 MHz
Figure 9. Typical NB3V110xC Phase Noise Plot at fCarrier = 100 MHz, VDD = 3.3 V, 255C
To obtain the most precise additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is greater than the noise floor of the device under test,
the source noise will dominate the additive phase jitter
calculation and lead to an incorrect negative result for the
additive phase noise within the integration range. The
Figure above is a good example of the NB3V110xC source
generator phase noise having a significantly lower floor than
the DUT and results in an additive phase jitter of 55.94 fs.
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 55.94 fs. The additive RMS phase jitter
performance of the fan out buffer is highly dependent on the
phase noise of the input source.
Additive RMS phase jitter + ǸRMS phase jitter of output2 * RMS phase jitter of input2
55.94 fs + Ǹ66.92 fs 2 * 36.72 fs 2
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8
NB3V110xC Series
F_carrier = 156.25 MHz
Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 51.76 fs
Input Source Phase Jitter = 23.5 fs
r
Output (DUT + Source)
Input Source
Output
u
nI Source 156.25 MHz
Input
Figure 10. Typical NB3V110xC Phase Noise Plot at fCarrier = 156.25 MHz, VCC = 3.3 V V, 255C
The additive RMS phase jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 46.11 fs.
Additive RMS phase jitter + ǸRMS phase jitter of output2 * RMS phase jitter of input2
46.11 fs + Ǹ51.76 fs 2 * 23.5 fs 2
phase noise and jitter analysis of timing devices and clock
tree designs. To see the performance of NB3V110xC
beyond conditions outlined in this datasheet, please visit the
ON Semiconductor Green Point Design Tools homepage.
Figures 9 and 10 were created with measured data from
Agilent−E5052A/B Signal Source Analyzer using ON
Semiconductor Phase Noise Explorer web tool. This free
application enables an interactive environment for advanced
Table 8. ORDERING INFORMATION
Device
Marking
Package
Shipping†
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
NB3V1102CDTR2G
102
NB3V1103CDTR2G
103
NB3V1104CDTR2G
104
NB3V1102CMTTBG
02
NB3V1104CMTTBG
04
WDFN8
(Pb−Free)
3000 / Tape & Reel
NB3V1106CDTR2G
1106
V
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NB3V1108CDTR2G
1108
V
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Please contact your ON Semiconductor sales representative for availability of parts in tube.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
DATE 26 FEB 2010
SCALE 4:1
D
PIN ONE
REFERENCE
2X
0.10 C
2X
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
e/2
MOLD CMPD
DETAIL B
A
A1
A3
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ÉÉÉ
ÉÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
DETAIL A
E
0.05 C
8X
L
L1
ÍÍ
ÍÍ
ÍÍ
0.10 C
L
A
B
ALTERNATE
CONSTRUCTIONS
C
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
1
DETAIL A
e
1
7X
4
L
5
8X
BOTTOM VIEW
b
0.10 C A
0.05 C
XXMG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
L2
8
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
B
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 3
7X
PACKAGE
OUTLINE
0.78
2.30
0.88
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON48654E
WDFN8, 2X2, 0.5 P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
0.65
PITCH
16X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
16X
1.26
98ASH70247A
TSSOP−16
DIMENSIONS: MILLIMETERS
XXXX
A
L
Y
W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE C
DATE 20 JUN 2008
SCALE 2:1
K REF
8x
0.20 (0.008) T U
0.10 (0.004)
S
2X
L/2
8
0.20 (0.008) T U
T U
B
−U−
1
J J1
4
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
K1
K
A
−V−
S
S
5
L
PIN 1
IDENT
M
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
DETAIL E
G
PLANE
0.25 (0.010)
N
M
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
N
F
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
XXX
YWW
AG
G
DETAIL E
XXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
STATUS:
98AON00697D
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
TSSOP−8
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON00697D
PAGE 2 OF 2
ISSUE
REVISION
DATE
O
RELEASED FOR PRODUCTION.
18 APR 2000
A
ADDED MARKING DIAGRAM INFORMATION. REQ. BY V. BASS.
13 JAN 2006
B
CORRECTED MARKING DIAGRAM PIN 1 LOCATION AND MARKING. REQ. BY C.
REBELLO.
13 MAR 2006
C
REMOVED EXPOSED PAD VIEW AND DIMENSIONS P AND P1. CORRECTED
MARKING INFORMATION. REQ. BY C. REBELLO.
20 JUN 2008
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2008
June, 2008 − Rev. 01C
Case Outline Number:
948S
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