NB3V8312CMNR4G

NB3V8312C Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra−low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50 W series or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri−stated) via the OE input, or enabled when High. The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate VDD core and VDDO output supplies allow the output buffers to operate at the same supply as the VDD (VDD = VDDO) or from a lower supply voltage. Compared to single−supply operation, dual supply operation enables lower power consumption and output−level compatibility. The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V, while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD ≥ VDDO. This buffer is ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. http://onsemi.com 1 32 QFN32 MN SUFFIX CASE 488AM LQFP−32 FA SUFFIX CASE 873A VDDO VDD Q0 GND Q1 RPU CLK_EN Q2 D Q Q3 Q4 Q5 CLK Q6 RPD Features Q7 • Power Supply Modes: • • • • • • • • • • Q8 VDD (Core) / VDDO (Outputs) 3.3 V / 3.3 V 3.3 V / 2.5 V 3.3 V / 1.8 V 2.5 V / 2.5 V 2.5 V / 1.8 V 1.8 V / 1.8 V 250 MHz Maximum Clock Frequency Accepts LVCMOS, LVTTL Clock Inputs LVCMOS Compatible Control Inputs 12 LVCMOS Clock Outputs Synchronous Clock Enable Output Enable to High Z State Control 150 ps Max. Skew Between Outputs Temp. Range −40°C to +85°C 32−pin LQFP and QFN Packages These are Pb−Free Devices Q9 Q10 Q11 RPU OE Figure 1. Simplified Logic Diagram ORDERING AND MARKING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. Applications • Networking • Telecom • Storage Area Network End Products • Servers • Routers • Switches © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 1 1 Publication Order Number: NB3V8312C/D 4 21 GND GND 5 20 Q6 OE 6 19 VDDO 12 13 14 15 16 Q8 GND 1 24 Q4 VDD 2 23 VDDO CLK_EN 3 22 Q5 CLK 4 GND 5 OE 6 19 VDDO VDD 7 GND 18 Q7 GND 8 17 GND Figure 2. LQFP−32 Pinout Configuration 21 GND NB3V8312C Q11 9 11 Q9 10 VDDO 9 GND Q7 17 Q10 8 GND GND 18 VDDO 7 Q11 VDD NB3V8312C 25 GND CLK 26 Q3 Q5 Exposed Pad (EP) 20 Q6 GND 16 3 27 VDDO CLK_EN Q8 15 VDDO 22 28 Q2 23 VDDO 14 2 Q9 13 Q4 VDD GND 12 24 29 GND 25 30 Q1 26 GND Q3 VDDO 27 Q10 11 28 1 31 VDDO 29 Q2 GND Q1 30 32 Q0 31 GND VDDO 10 32 VDDO Q0 NB3V8312C Figure 3. QFN32 Pinout Configuration (Top View) (Top View) Table 1. PIN DESCRIPTION Open Default Pin Name I/O 1, 5, 8, 12, 16, 17, 21, 25, 29 GND Power Ground, Negative Power Supply 2, 7 VDD Power Positive Supply for Core and Inputs 3 CLK_EN Input High Synchronous Clock Enable Input. When High, outputs are enabled. When Low, outputs are disabled Low. Internal Pullup Resistor. 4 CLK Input Low Single−ended Clock input; LVCMOS/LVTTL. Internal Pull−down Resistor. 6 OE Input High Output Enable. Internal Pullup Resistor. 9, 11, 13, 15, 18, 20, 22, 24, 26, 28, 30, 32 Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 Output Single−ended LVCMOS/LVTTL outputs 10, 14, 19, 23, 27, 31 VDDO Power Positive Supply for Outputs − EP − − Description The Exposed Pad (EP) on the package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is connected to the die and must only be connected electrically to GND on the PC board. 1. All VDD, VDDO and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with 0.01 mF to GND. http://onsemi.com 2 NB3V8312C CLK CLK_EN Q Figure 4. CLK_EN Control Timing Diagram Table 2. OE, CLK_EN FUNCTION TABLES Inputs Outputs OE CLK_EN (Note 2) CLK Q[0:11] 0 X X Hi−Z 1 0 X Low 1 1 0 Low 1 1 1 High 2. The CLK_EN control input synchronously enables or disables the outputs as shown in Figure 4. This control latches on the falling edge of the selected input CLK. When CLK_EN is LOW, the outputs are disabled in a LOW state. When CLK_EN is HIGH, the outputs are enabled as shown. CLK_EN to CLK Set up and Hold times must be satisfied. http://onsemi.com 3 NB3V8312C Table 3. ATTRIBUTES (Note 3) Characteristics Value Internal Input Pullup (RPU) and Pulldown (RPD) Resistor 50 kW Input Capacitance, CIN 4 pF Power Dissipation Capacitance, CPD (per Output) 20 pF 8W ROUT ESD Protection Human Body Model Machine Model > 1.5 kV > 200 V LQFP QFN Level 2 Level 1 Moisture Sensitivity (Note 3) Flammability Rating Oxygen Index UL−94 code V−0 A 1/8” 28 to 34 Transistor Count 464 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS (Note 4) Symbol VDD / VDDO VI Parameter Condition Positive Power Supply GND = 0 V Input Voltage Rating Unit 4.6 V −0.5 v VI v VDD + 0.5 V −65 to +150 °C 0 lfpm 500 lfpm LQFP−32 LQFP−32 80 55 °C/W °C/W Standard Board LQFP−32 LQFP−32 12−17 °C/W Thermal Resistance (Junction−to−Ambient) (Note 5) 0 lfpm 500 lfpm QFN*32 QFN*32 31 27 °C/W Thermal Resistance (Junction−to−Case) (Note 5) Standard Board QFN*32 12 °C/W Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 5) qJC Thermal Resistance (Junction−to−Case) (Note 5) qJA qJC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 5. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 4 NB3V8312C Table 5. LVCMOS/LVTTL DC CHARACTERISTICS (TA = −40°C to +85°C) Symbol Characteristics Conditions Max Unit 2.0 VDD + 0.3 V 1.7 VDD + 0.3 V VDD = 2.0 V 0.65 x VDD VDD + 0.3 V VDD = 3.465 V −0.3 1.3 V VDD = 2.625 V −0.3 0.7 V −0.3 0.35 x VDD V VDD = 3.465 V VIH VIL VDD = 2.625 V Input High Voltage Input Low Voltage VDD = 2.0 V IIH Input High Current IIL Input Low Current VOH VOL Min Typ CLK OE, CLK_EN 150 VDD = VIN = 3.465 V or 2.625 V or 2.0 V CLK OE, CLK_EN −5 VDD = 3.465 V or 2.625 V or 2.0 V, VIN = 0 V 2.6 VDDO = 2.5 V ±5% 1.8 VDDO = 2.5 V ±5%; IOH = −1 mA 2.0 VDDO = 1.8 V ±0.2 V VDD – 0.4 VDDO = 1.8 V ±0.2 V; IOH = −100 mA VDD – 0.2 mA mA −150 VDDO = 3.3 V ±5% Output High Voltage (Note 6) Output Low Voltage (Note 6) 5 V VDDO = 3. 3V ±5% 0.5 VDDO = 2.5 V ±5% 0.45 VDDO = 2.5 V ±5%; IOL = 1 mA 0.4 VDDO = 1.8 V ±0.2 V 0.35 VDDO = 1.8 V ±0.2 V; IOL = 100 mA 0.2 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Outputs terminated 50 W to VDDO/2 unless otherwise specified. See Figure 7. Table 6. POWER SUPPLY DC CHARACTERISTICS, (TA = −40°C to +85°C) VDD (Core) VDDO (Outputs) 3.3 V ±5% Max Unit 3.3 V ±5% 10 mA 3.3 V ±5% 2.5 V ±5% 10 mA 3.3 V ±5% 1.8 V ± 0.2V 10 mA 2.5 V ±5% 2.5 V ±5% 10 mA 2.5 V ±5% 1.8 V ± 0.2V 10 mA 1.8 V ± 0.2 V 1.8 V ± 0.2V 10 mA http://onsemi.com 5 Min Typ NB3V8312C Table 7. AC CHARACTERISTICS (TA = −40°C to +85°C) (Note 7) Symbol fMAX tpLH tjit tsk(o) tsk(pp) tr/tf ODC Characteristic Maximum Operating Frequency Propagation Delay, Low to High; (Note 8) Min VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 250 250 200 250 200 200 VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 0.9 1.0 1.0 1.3 1.3 2.4 Typ Max MHz 2.2 2.3 3.0 3.1 3.5 4.2 Additive Phase Jitter, RMS; fC = 100 MHz Integration Range: 12 kHz − 20 MHz See Figure 5 VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V Output−to−output skew; (Note 9); Figure 6 VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 125 135 145 150 150 140 VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 250 250 250 250 250 250 Part−to−Part Skew; (Note 10) Output rise and fall times Output Duty Cycle (Note 11) Unit 30 40 50 20 100 130 ns fs VDD / VDDO 3.3 V ±5% / 3.3 V ±5% 3.3 V ±5% / 2.5 V ±5% 3.3 V ±5% / 1.8 V ± 0.2 V 2.5 V ±5% / 2.5 V ±5% 2.5 V ±5% / 1.8 V ± 0.2 V 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 200 200 200 200 200 200 700 700 700 700 700 800 VDD / VDDO f ≤ 200 MHz, 3.3 V ±5% / 3.3 V ±5% f ≤ 150 MHz, 3.3 V ±5% / 2.5 V ±5% f ≤ 100 MHz, 3.3 V ±5% / 1.8 V ± 0.2 V f ≤ 150 MHz, 2.5 V ±5% / 2.5 V ±5% f ≤ 100 MHz, 2.5 V ±5% / 1.8 V ± 0.2 V f ≤ 100 MHz, 1.8 V ± 0.2 V / 1.8 V ± 0.2 V 45 45 45 45 45 45 55 55 55 55 55 55 ps ps ps % All parameters measured at fMAX unless noted otherwise. 7. Outputs loaded with 50 W to VDDO/2; see Figure 7. CLOCK input with 50% duty cycle; minimum input amplitude = 1.2 V at VDD = 3.3 V, 1.0 V at VDD = 2.5 V, VDD/2 at VDD = 1.8 V. 8. Measured from the VDD/2 of the input to VDDO/2 of the output. 9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. 10. Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. 11. Clock input with 50% duty cycles, rail−to−rail amplitude and tr/tf = 500 ps. http://onsemi.com 6 NB3V8312C NB3V8312C Additive Phase Jitter @ 100 MHz VDD = VDDO = 3.3 V 12 kHz to 20 MHz = 29.8 fs (typical) Filter = 12 kHz − 20 MHz Source RMS Jitter = 200.53 fs Output RMS Jitter = 202.73 fs RMS addititive jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 29.8 + Ǹ202.73 fs 2 * 200.53 fs 2 Output (DUT + Source) Input Source Figure 5. Typical Phase Noise Plot at fcarrier = 100 MHz at an Operating Voltage of 3.3 V, Room Temperature The above phase noise data was captured using Agilent E5052A/B. The data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. The RMS Phase Jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 29.8 fs. The additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. To obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the DUT. If the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. The Figure above is a good example of the NB3V8312C source generator phase noise having a significantly higher floor such that the DUT output results in an additive phase jitter of 29.8 fs. RMS addititive jitter + ǸRMS phase jitter of output 2 * RMS phase jitter of input 2 29.8 + Ǹ202.73 fs 2 * 200.53 fs 2 http://onsemi.com 7 NB3V8312C VPP = VIH − VIL CLK V DD V DD 2 2 VIHCMR CLK GND LVCMOS_CLK V DD V DD 2 2 V DDO V DDO Qx 2 2 tLH tPHL V DDO tPW V DDO V DDO 2 2 2 Qx tP t SKEWDC % + ǒt PWńt PǓ 100 Figure 6. AC Reference Measurement VDD VDDO ZO = 50 W NB3V8312C Qx IN Scope 50 W GND VDDO ÷ 2 = 0 V = Ground Figure 7. Typical Device Evaluation and Termination Setup − See Table 8 Table 8. TEST SUPPLY SETUP. VDDO SUPPLY MAY BE CENTERED ON 0.0 V (SCOPE GND) TO PERMIT DIRECT CONNECTION INTO “50 W TO GND” SCOPE MODULE. VDD SUPPLY TRACKS DUT GND PIN Spec Condition: VDD Test Setup VDDO Test Setup GND Pin Test Setup VDD = 3.3 V ±5%, VDDO = 3.3 V ±5% +1.65 ±5% +1.65 V ±5% −1.65 V ±5% VDD = 3.3 V ±5%, VDDO = 2.5 V ±5% +2.05 V ±5% +1.25 V ±5% −1.25 V ±5% VDD = 3.3 V ±5%, VDDO = 1.8 V ±5% +2.4 V ±5% +0.9 V ±0.1 V −0.9 V ±0.1 V VDD = 2.5 V ±5%, VDDOO = 2.5 V ±5% +1.25 V ±5% +1.25 V ±5% −1.25 V ±5% +1.6 V ±5% +0.9 V ±0.1 V −0.9 V ±0.1 V +0.9 V ±0.1 V +0.9 V ±0.1 V −0.9 V ±0.1 V VDD = 2.5 V ±5%, VDDO = 1.8 V ±0.2 V VDD = 1.8 V ±0.2 V, VDDO = 1.8 V ±0.2 V http://onsemi.com 8 NB3V8312C MARKING DIAGRAMS* 32 1 NB3V 8312C AWLYYWWG NB3V 8312C AWLYYWWG LQFP−32 QFN32 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (*Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Shipping† NB3V8312CFAG LQFP−32 (Pb−Free) 250 Units / Tray NB3V8312CFAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel NB3V8312CMNG QFN32 (Pb−Free) 74 Units / Rail NB3V8312CMNR4G QFN32 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A 1 32 SCALE 2:1 A D PIN ONE LOCATION ÉÉ ÉÉ NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L B DATE 23 OCT 2013 L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 0.15 C EXPOSED Cu A DETAIL B 0.10 C (A3) A1 0.08 C DETAIL A 9 32X L ALTERNATE CONSTRUCTION GENERIC MARKING DIAGRAM* K D2 1 XXXXXXXX XXXXXXXX AWLYYWWG G 17 8 MOLD CMPD DETAIL B SEATING PLANE C SIDE VIEW NOTE 4 ÉÉ ÉÉ ÇÇ TOP VIEW MILLIMETERS MIN MAX 0.80 1.00 −−− 0.05 0.20 REF 0.18 0.30 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 E2 1 32 25 e e/2 32X b 0.10 M C A B 0.05 M C BOTTOM VIEW XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. NOTE 3 RECOMMENDED SOLDERING FOOTPRINT* 5.30 32X 0.63 3.35 3.35 5.30 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON20032D QFN32 5x5 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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