NB4L858MFAR2G

NB4L858M 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM* Description The NB4L858M is a high−bandwidth low voltage fully differential dual 2 x 2 crosspoint switch with CML outputs that is suitable for applications such as SDH/SONET DWDM and high speed switching applications. Design technique minimizes jitter accumulation, crosstalk, and signal skew which make this device ideal for loop−through and protection channel switching application. Each 2 x 2 crosspoint switch can fan out and/or multiplex up to 3 Gb/s data and 3 GHz clock signals. Differential inputs incorporate a pair of internal 50 W termination resistors in a center−tapped configuration (VTDx Pins) and can accept LVPECL (Positive ECL) or CML input signal without any external component. This feature provides transmission line termination on−chip, at the receiver end, eliminating external components. Differential 16 mA CML output provides matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. The SELECT inputs are single−ended and can be driven with either LVCMOS or LVTTL input levels. The device is housed in a low profile 7 x 7 mm 32−pin LQFP package. LQFP−32 FA SUFFIX CASE 873A A WL, L YY, Y WW, W G NB4L 858M AWLYYWW 32 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. SELA0 0 DA0 VTDA0 DA0 50W 50W A0 QA0 QA0 1 Features • • • • • • • • • Maximum Input Clock Frequency 3 GHz Maximum Input Data Frequency 3 Gb/s 350 ps Typical Propagation Delay 80 ps Typical Rise and Fall Times 12 ps Channel to Channel Skew 0.5 ps RMS Jitter 5 ps Deterministic Jitter @ 2.5 Gb/s Operating Range: VCC = 2.3V to 3.6 V with GND = 0 V CML Output Level (400 mV Peak−to−Peak Output), Differential Output • These are Pb−Free Devices SELA1 0 DA1 VTDA1 50W 50W A1 DA1 QA1 QA1 1 SELB0 0 DB0 VTDB0 DB0 50W 50W B0 QB0 QB0 1 SELB1 0 DB1 VTDB1 50W 50W B1 DB1 QB1 QB1 1 Figure 1. Functional Block Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2005 December, 2005 − Rev. 9 1 Publication Order Number: NB4L858M/D NB4L858M GND VCC QA0 QA0 24 23 22 21 VCC QA1 20 19 QA1 18 VCC 17 DA0 25 16 VCC VTDA0 26 15 QB1 DA0 27 14 QB1 SELA1 28 13 VCC 12 QB0 LQFP−32 DA1 29 VTDA1 30 11 QB0 DA1 31 10 VCC SELA0 32 9 GND 1 2 3 4 5 6 7 8 DB1 VTDB1 DB1 SELB0 DB0 VTDB0 DB0 SELB1 Figure 1. Pin Configuration (Top View) Table 1. TRUTH TABLE SELA0/SELB0 SELA1/SELB1 QA0/QB0 QA1/QB1 L L DA0/DB0 DA0/DB0 1:2 Fanout or Redundant Distribution L H DA0/DB0 DA1/DB1 Quad Repeater or Crosspoint Switch H L DA1/DB1 DA0/DB0 Quad Repeater or Crosspoint Switch H H DA1/DB1 DA1/DB1 1:2 Fanout or Redundant Distribution http://onsemi.com 2 Function NB4L858M Table 2. PIN DESCRIPTION Pin Name I/O 1 DB1 LVPECL, CML Input Description 2 VTDB1 − 3 DB1 LVPECL, CML Input 4 SELB0 LVTTL / LVCMOS 5 DB0 LVPECL, CML Input 6 VTDB0 − 7 DB0 LVPECL, CML Input 8 SELB1 LVTTL / LVCMOS 9,24 GND − Supply ground. All GND pins must be externally connected to power supply to guarantee proper operation. 10, 13, 16, 17, 20, 23 VCC − Positive Supply. All VCC pins must be externally connected to power supply to guarantee proper operation. 11 QB0 CML Output Channel B0 negative signal output. Typically terminated with 50 W resistor to VCC. 12 QB0 CML Output Channel B0 positive signal output. Typically terminated with 50 W resistor to VCC 14 QB1 CML Output Channel B1 negative signal output. Typically terminated with 50 W resistor to VCC. 15 QB1 CML Output Channel B1 positive signal output. Typically terminated with 50 W resistor to VCC. 18 QA1 CML Output Channel A1 negative signal output. Typically terminated with 50 W resistor to VCC. 19 QA1 CML Output Channel A1 positive signal output. Typically terminated with 50 W resistor to VCC. 21 QA0 CML Output Channel A0 negative signal output. Typically terminated with 50 W resistor to VCC. 22 QA0 CML Output Channel A0 positive signal output. Typically terminated with 50 W resistor to VCC. 25 DA0 LVPECL, CML Input 26 VTDA0 − 27 DA0 LVPECL, CML Input 28 SELA1 LVTTL 29 DA1 LVPECL, CML Input 30 VTDA1 − 31 DA1 LVPECL, CML Input 32 SELA0 LVTTL Channel B1 positive signal input. Internal 100 W center−tapped termination pin for channel B1. Channel B1 negative signal input. Channel B0 Output Select. See Table 1. Channel B0 positive signal input. Internal 100 W center−tapped termination pin for channel B0. Channel B0 negative signal input. Channel B1 output select. See Table 1. Channel A0 positive signal input. Internal 100 W center−tapped termination pin for channel A0. Channel A0 negative signal input. Channel A1 output select. See Table 1. Channel A1 positive signal input. Internal 100 W center−tapped termination pin for channel A1. Channel A1 negative signal input. Channel A0 output select. See Table 1. http://onsemi.com 3 NB4L858M Table 3. Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 1) > 2000 V >110 V 32−LQFP Flammability Rating Level 2 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 380 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 3.8 V 3.8 V 3.8 V Static Surge 45 80 mA mA Output Current Continuous Surge 25 80 mA mA TA Operating Temperature Range LQFP−32 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 2) 32 LQFP 12 to 17 °C/W Tsol Wave Solder