NB4N840MMNTWG

NB4N840M 2 x 2 Crosspoint Switch, Dual, 3.3 V, 3.2 Gb/s, with CML Outputs Description http://onsemi.com The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for applications such as SDH/SONET, DWDM, Gigabit Ethernet and high speed switching. Fully differential design techniques are used to minimize jitter accumulation, crosstalk, and signal skew, which make this device ideal for loop−through and protection channel switching applications. Internally terminated differential CML inputs accept AC−coupled LVPECL (Positive ECL) or direct coupled CML signals. By providing internal 50 W input and output termination resistor, the need for external components is eliminated and interface reflections are minimized. Differential 16 mA CML outputs provide matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. Single−ended LVCMOS/LVTTL SEL inputs control the routing of the signals through the crosspoint switch which makes this device configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The device is housed in a low profile 5 x 5 mm 32−pin QFN package. MARKING DIAGRAM 1 32 1 NB4N 840M ALYWG QFN32 MN SUFFIX CASE 488AM A WL YY WW G DA0 DA0 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package CML QA0 0 CML 1 QA0 ENA0 SELA0 Features • • • • • • • • • • • • • 0 Plug−in compatible to the MAX3840 and SY55859L Maximum Input Clock Frequency 2.7 GHz Maximum Input Data Frequency 3.2 Gb/s 225 ps Typical Propagation Delay 80 ps Typical Rise and Fall Times 7 ps Channel to Channel Skew 430 mW Power Consumption < 0.5 ps RMS Jitter 7 ps Peak−to−Peak Data Dependent Jitter Power Saving Feature with Disabled Outputs Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V CML Output Level (400 mV Peak−to−Peak Output), Differential Output These are Pb−Free Devices © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 5 1 DA1 DA1 CML DB0 DB0 CML 1 QA1 CML QA1 ENA1 SELA1 0 QB0 CML 1 QB0 ENB0 SELB0 QB1 0 DB1 DB1 CML 1 CML QB1 ENB1 SELB1 Figure 1. Functional Block Diagram ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Publication Order Number: NB4N840M/D NB4N840M Table 1. TRUTH TABLE L H H H DA0/DB0 DA1/DB1 Quad Repeater H L H H DA1/DB1 DA0/DB0 Crosspoint Switch H H H H DA1/DB1 DA1/DB1 1:2 Fanout X X L L Disable/Power Down Disable/Power Down SELA1 1:2 Fanout DA0 DA0/DB0 DA0 QA1/QB1 DA0/DB0 SELA0 QA0/QB0 H ENA0 ENB0/ENB1 H DA1 ENA0/ENA1 L DA1 SELA1/SELB1 L ENA1 SELA0/SELB0 32 31 30 29 28 27 26 25 ENB1 1 24 GND DB1 2 23 VCC DB1 3 22 QA0 ENB0 4 21 QA0 NB4N840M 6 19 QA1 DB0 7 18 QA1 SELB1 8 17 VCC 11 12 13 14 15 Figure 2. Pin Configuration (Top View) http://onsemi.com 2 16 VCC 10 VCC GND 9 QB1 DB0 QB1 VCC VCC 20 QB0 5 QB0 SELB0 Function No output (@ VCC) NB4N840M Table 2. PIN DESCRIPTION Pin Name I/O 1 ENB1 LVTTL Description 2 DB1 CML Input Channel B1 Positive Signal Input 3 DB1 CML Input Channel B1 Negative Signal Input 4 ENB0 LVTTL Channel B0 Output Enable. LVTTL low input powers down B0 output stage. 5 SELB0 LVTTL Channel B0 Output Select. See Table 1. 6 DB0 CML Input Channel B0 Positive Signal Input 7 DB0 CML Input Channel B0 Negative Signal Input 8 SELB1 LVTTL 9,24 GND − Supply Ground. All GND pins must be externally connected to power supply to guarantee proper operation. 10, 13, 16, 17, 20, 23 VCC − Positive Supply. All VCC pins must be externally connected to power supply to guarantee proper operation. Channel B1 Output Enable. LVTTL low input powers down B1 output stage. Channel B1 Output Select. See Table 1. 11 QB0 CML Output Channel B0 Negative Output. 12 QB0 CML Output Channel B0 Positive Output. 14 QB1 CML Output Channel B1 Negative Output. 15 QB1 CML Output Channel B1 Positive Output. 18 QA1 CML Output Channel A1 Negative Output. 19 QA1 CML Output Channel A1 Positive Output. 21 QA0 CML Output Channel A0 Negative Output. 22 QA0 CML Output Channel A0 Positive Output. 25 SELA1 LVTTL 26 DA0 CML Input Channel A0 Positive Signal Input. 27 DA0 CML Input Channel A0 Negative Signal Input. 28 SELA0 LVTTL Channel A0 Output Select, LVTTL Input. See Table 1. 29 ENA0 LVTTL Channel A0 Output Enable. LVTTL low input powers down A0 output stage. 30 DA1 CML Input Channel A1 Positive Signal Input. 31 DA1 CML Input Channel A1 Negative Signal Input. 32 ENA1 LVTTL − EP GND Channel A1 Output Select, LVTTL Input. See Table 1. Channel A1 Output Enable. LVTTL low input powers down A1 output stage. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. The exposed pad must be soldered to the circuit board GND for proper electrical and thermal operation. http://onsemi.com 3 NB4N840M Table 3. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity (Note 1) > 2000 V > 110 V QFN−32 Flammability Rating Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 380 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Rating Unit 3.8 V 3.8 V 3.8 V Static Surge 45 80 mA mA Output Current Continuous Surge 25 80 mA mA TA Operating Temperature Range QFN−32 −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 2) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) QFN−32 12 °C/W Tsol Wave Solder