NB4N855SMR4

NB4N855S 3.3 V, 1.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer/ Translator Description http://onsemi.com MARKING DIAGRAM* 10 1 Micro 10 M SUFFIX CASE 846B A Y W 855S AYW 1 = Assembly Location = Year = Work Week NB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in compatible to the SY55855V in a 3.3 V applications. The NB4N855S has a wide input common mode range of GND + 50 mV to VCC − 50 mV. This feature is ideal for translating differential or single−ended data or clock signals to 350 mV typical LVDS output levels. The device is offered in a small 10 lead MSOP package. NB4N855S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. Application notes, models, and support documentation are available at www.onsemi.com. Features *For additional marking information, refer to Application Note AND8002/D. D0 D0 Q0 Q0 • • • • • • • • Guaranteed Input Clock Frequency up to 1.0 GHz Guaranteed Input Data Rate up to 1.5 Gb/s 490 ps Maximum Propagation Delay 1.0 ps Maximum RMS Jitter 180 ps Maximum Rise/Fall Times Single Power Supply; VCC = 3.3 V ±10% Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs GND + 50 mV to VCC − 50 mV VCMR Range D1 D1 Q1 Q1 Functional Block Diagram ORDERING INFORMATION VOLTAGE (50 mV/div) See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Device DDJ = 7 ps TIME (133 ps/div) Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5 (VINPP = 100 mV, Input Signal DDJ = 24 ps) © Semiconductor Components Industries, LLC, 2005 1 June, 2005 − Rev. 0 Publication Order Number: NB4N855S/D NB4N855S D0 D0 D1 D1 GND 1 2 3 4 5 10 9 8 7 6 VCC Q0 Q0 Q1 Q1 Figure 2. Pin Configuration and Block Diagram (Top View) Table 1. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 Name D0 D0 D1 D1 GND Q1 Q1 Q0 Q0 VCC I/O LVPECL, CML, LVCMOS, LVTTL, LVDS LVPECL, CML, LVCMOS, LVTTL, LVDS LVPEL, CML, LVDS LVCMOS, LVTTL LVPECL, CML, LVDS LVCMOS LVTTL − LVDS Output LVDS Output LVDS Output LVDS Output − Description Noninverted Differential Clock/Data D0 Input. Inverted Differential Clock/Data D0 Input. Noninverted Differential Clock/Data D1 Input. Inverted Differential Clock/Data D1 Input. Ground. 0 V. Inverted Q1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted Q1 output. Typically loaded with 100 W receiver termination resistor across differential pair. Inverted Q0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Noninverted Q0 output. Typically loaded with 100 W receiver termination resistor across differential pair. Positive Supply Voltage. http://onsemi.com 2 NB4N855S Table 2. ATTRIBUTES Characteristics Moisture Sensitivity (Note 1) Flammability Rating ESD Protection Oxygen Index: 28 to 34 Human Body Model Machine Model Charged Device Model Value Level 1 UL 94 V−0 @ 0.125 in > 2 kV > 200 V > 1 kV 281 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol VCC VI IIN IOSC Parameter Positive Power Supply Positive Input Input Current Through RT (50 W Resistor) Output Short Circuit Current Line−to−Line (Q to Q) Line−to−End (Q or Q to GND) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 2) Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm 1S2P (Note 4)