NB6HQ14M 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer w/ Selectable
Input Equalizer Multi−Level Inputs w/ Internal Termination
Description
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16 1
The NB6HQ14M is a high performance differential 1:4 CML fanout buffer with a selectable Equalizer receiver. When placed in series with a Clock /Data path operating up to 5 GHz or 6.5 Gb/s, respectively, the NB6HQ14M inputs will compensate the degraded signal transmitted across a FR4 PCB backplane or cable interconnect and output four identical CML copies of the input signal. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When EQEN is set High, the IN/IN inputs flow through the Equalizer. The default state at start−up is LOW. As such, NB6HQ14M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB6HQ14M to accept various logic level standards, such as LVPECL, CML or LVDS. The outputs have the flexibility of being powered by either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized for low output skew applications. The NB6HQ14M is a member of the ECLinPS MAX™ family of high performance clock products.
Features
1 QFN−16 MN SUFFIX CASE 485G
NB6H Q14M ALYWG G
A L Y W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
EQ
• • • • • • • • • • • • •
Input Data Rate > 6.5 Gb/s Input Clock Frequency > 5 GHz 170 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times < 15 ps Output Skew < 0.8 ps RMS Clock Jitter < 10 ps pp of Data Dependent Jitter Differential CML Outputs, 400 mV Peak−to−Peak, Typical Selectable Input Equalization Operating Range: VCC = 2.375 V to 2.625 V, VCCO = 1.71 V to 2.625 V Internal Input Termination Resistors, 50 W −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 0
1
Publication Order Number: NB6HQ14M/D
NB6HQ14M
Multi−Level Inputs LVPECL, LVDS, CML IN VT IN 50 W CML Outputs VCC0 Q0 50 W 0 2:1 MUX EQ 1 Q0 Q1 Q1 Q2 Q2 Q3 Q3 56 kW
VREFAC VCC GND EQEN (Equalizer Enable)
Figure 1. Detailed Block Diagram of NB6HQ14M
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NB6HQ14M
GND Q0 16 IN VT 1 2 NB6HQ14M VREFAC 3 IN 4 5 6 7 8 15 Q0 14 VCC Exposed Pad (EP) 13 12 Q1 11 Q1 10 Q2 9 Q2
Table 1. EQUALIZER ENABLE FUNCTION
EQEN 0 1 Function IN / IN Inputs By−pass the Equalizer section Inputs flow through the Equalizer
EQEN Q3
Q3 VCCO
Figure 2. QFN−16 Pinout (Top View) Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name IN VT VREFAC IN EQEN Q3 Q3 VCCO Q2 Q2 Q1 Q1 VCC Q0 Q0 GND EP LVPECL, CML, LVDS Input LVCMOS Input CML Output CML Output − CML Output CML Output CML Output CML Output − CML Output CML Output − − I/O LVPECL, CML, LVDS Input Non−inverted Differential Input. Note 1. Internal 100 W Center−tapped Termination Pin for IN / IN Output Voltage Reference for Capacitor−Coupled Inputs, only Inverted Differential Input. Note 1. Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor) Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 2.5 V Positive Supply Voltage for the core Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. Negative Supply Voltage The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Description
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN / IN input, then, the device will be susceptible to self−oscillation. 2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation.
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NB6HQ14M
Table 3. ATTRIBUTES
Characteristics ESD Protection RPD − EQEN Input Pulldown Resistor Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. 16−QFN Oxygen Index: 28 to 34 Human Body Model Machine Model Value > 2 kV > 200V 56 kW Level 1 UL 94 V−0 @ 0.125 in 277
Table 4. MAXIMUM RATINGS
Symbol VCC VCCO VIO VINPP IIN IOUT IVFREFAC TA Tstg θJA θJC Tsol Parameter Positive Power Supply − Core Positive Power Supply − Outputs Positive Input/Output Voltage Differential Input Voltage |IN − IN| Input Current Through RT (50 W Resistor) Output Current Through RT (50 W Resistor) VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) (Note 4) Wave Solder Pb−Free 0 lfpm 500 lfpm 16 QFN 16 QFN 16 QFN 16 QFN Condition 1 GND = 0 V GND = 0 V GND = 0 V Condition 2 Rating 3.0 3.0 −0.5 to VCC + 0.5 1.89 $40 $40 $1.5 −40 to +85 −65 to +150 42 35 4 265 Unit V V V V mA mA mA °C °C °C/W °C/W °C/W °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6HQ14M
Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V;
Symbol POWER SUPPLY / CURRENT VCC VCCO ICC ICCO Power Supply Voltage VCC = 2.5 V VCCO = 2.5 V VCCO = 1.8 V 2.375 2.375 1.71 2.5 2.5 1.8 75 65 2.625 2.625 1.89 110 90 V Characteristic Min Typ Max Unit
TA = −40°C to 85°C (Note 5)
Power Supply Current for VCC (Inputs and Outputs Open) Power Supply Current for VCCO (Inputs and Outputs Open)
mA
CML OUTPUTS (Note 6) VOH Output HIGH Voltage VCCO = 2.5 V VCCO = 1.8 V VCCO = 2.5 V VCCO = 1.8 V VCCO – 30 2470 1770 VCCO – 550 1950 1250 VCCO – 10 2490 1790 VCCO – 450 2050 1350 VCCO 2500 1800 VCCO – 300 2200 1500 mV
VOL
Output LOW Voltage
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7) VIH VIL Vth VISE VREFAC VREFAC VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Output Reference Voltage @100 mA for capacitor− coupled inputs, only VCC – 1325 1200 0 100 1050 −150 −150 VCC – 1125 VCC – 925 VCC VIHD − 100 1200 VCC − 50 150 150 mV Single−ended Input HIGH Voltage Single−ended Input LOW Voltage Input Threshold Reference Voltage Range (Note 8) Single−ended Input Voltage Amplitude (VIH − VIL) Vth + 100 GND 1100 200 VCC Vth −100 VCC − 100 2800 mV mV mV mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input Common Mode Range (Differential Configuration) (Note 10) (Figure 9) Input HIGH Current IN / IN, (VT Open) Input LOW Current IN / IN, (VT Open) mV mV mV mV uA uA
CONTROL INPUTS (EQEN) Input HIGH Voltage for Control Pins Input LOW Voltage for Control Pins Input HIGH Current Input LOW Current VCC x 0.65 GND −150 −150 VCC VCC x 0.35 150 150 V V mA mA
TERMINATION RESISTORS Internal Input Termination Resistor Internal Output Termination Resistor 45 45 50 50 55 55 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Output parameters vary 1:1 with VCCO. 6. CML outputs loaded with 50 W to VCCO for proper operation. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the crosspoint side of the differential input signal.
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NB6HQ14M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V; VCCO = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11)
Symbol fMAX fDATAMAX VOUTPP tPLH, tPHL tSKEW Characteristic Maximum Input Clock Frequency; Maximum Operating Data Rate (PRBS23) Output Voltage Amplitude, EQEN = 0 or 1 (Note 15) (See Figures 3 and 10) Propagation Delay, EQEN = 0 or 1 Duty Cycle Skew (Note 12) Output – Output Within Device Skew Device to Device Skew Output Clock Duty Cycle (Reference Duty Cycle = 50%) Phase Noise, fin = 1 GHz fin = 1 GHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz 45 fin ≤ 5 GHz IN to Q VOUT w 200 mV Min 5 6.5 200 150 Typ 7 10 400 220 275 15 15 50 55 Max Unit GHz Gbps mV ps ps
3 10 50 −132 −135 −145 −146 −147 −148 50 fin v 5 GHz fin v 3.0 Gb/s EQEN = 0 (v 3” FR4) EQEN = 1 (12” FR4) 100 Qx, Qx 15 30 0.2
tDC FN
% dBc
t FN tJITTER
Integrated Phase Jitter fin = 1 GHz, 12 kHz − 20 MHz Offset (RMS) RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14)
fs 0.8 15 10 1200 60 ps rms ps pk−pk ps pk−pk mV ps
VINPP tr tf
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) Output Rise/Fall Times @ 1.0 GHz (20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured by forcing VINPP min from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCCO. Input edge rates 40 ps (20% − 80%). 12. Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. For applications requiring equalization, the vertical eye height is also a critical figure of merit. See Figure 4 for equalized eye height versus data rate. 15. Input and output voltage swings are single−ended measurements operating in a differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 fin, CLOCK INPUT FREQUENCY (GHz) 8 400 350 Q AMP (mV) EYE HEIGHT (mV) 300 250 200 150 100 50 0 0 1 2 3 4 4 6 DATE RATE (Gbps) 5 8 7
Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical)
Figure 4. NB6HQ14M Eye Height vs. Data Rate
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NB6HQ14M
VCC
IN 50 W VT 50 W IN
Figure 5. Input Structure
VIH Vth VIL
IN IN
IN Vth
IN
Figure 6. Differential Input Driven Single−Ended
VCC Vthmax VIHmax VILmax Vth Vthmin GND IN VIH Vth VIL VIHmin VILmin IN IN
Figure 7. Differential Inputs Driven Differentially
VID = |VIHD(IN) − VILD(IN)| VIHD VILD
Figure 8. Vth Diagram
Figure 9. Differential Inputs Driven Differentially
VCC VCMRmax
VIHD(MAX) VILD(MAX)
INx INx VINPP = VIH(IN) − VIL(IN)
VCMR
VIHD VID = VIHD − VILD VILD
Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL
VCMRmin GND
VIHD(MIN) VILD(MIN)
Figure 10. VCMR Diagram
Figure 11. AC Reference Measurement
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NB6HQ14M
VCC
VT FR4 − 12 Inch Backplane
NB6HQ14M EQualizer EQEN = 1
Driver
Q
IN IN
Q
DJ1
DJ2
DJ3
Figure 12. Typical NB6HQ14M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1
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NB6HQ14M
VCC VCC VCC VCC
ZO = 50 W LVPECL Driver VT = VCC − 2 V ZO = 50 W
NB6HQ14M IN 50 W 50 W IN LVDS Driver
ZO = 50 W VT = Open ZO = 50 W
NB6HQ14M IN 50 W 50 W IN
GND/VEE
GND
GND
GND
Figure 13. LVPECL Interface
Figure 14. LVDS Interface
VCC
VCC
VCC
VCC
ZO = 50 W CML Driver VT = VCC ZO = 50 W
NB6HQ14M IN 50 W 50 W IN Differential Driver ZO = 50 W VT = VREFAC* ZO = 50 W
NB6HQ14M IN 50 W 50 W IN
GND
GND
GND
GND
Figure 15. Standard 50 W Load CML Interface
Figure 16. Capacitor−Coupled Differential Interface (VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor
VCC
VCC
ZO = 50 W Differential Driver VT = VREFAC*
NB6HQ14M IN 50 W 50 W IN
GND
Figure 17. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC)
GND
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NB6HQ14M
NB6HQ14M VCCO VCCO = VCC (Receiver) 50 W 50 W Receiver VCC (Receiver)
50 W
50 W
16 mA GND
Figure 18. Typical CML Output Structure and Termination
ORDERING INFORMATION
Device NB6HQ14MMNG NB6HQ14MMNHTBG NB6HQ14MMNTXG Package QFN−16 (Pb−Free) QFN−16 (Pb−Free) QFN−16 (Pb−Free) Shipping† 123 Units / Rail 100 / Tape & Reel 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB6HQ14M
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G−01 ISSUE D
L L1 DETAIL A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG
D
A B
PIN 1 LOCATION
0.15 C 0.15 C
TOP VIEW
A1
0.10 C
DETAIL B
(A3) A
DETAIL B
ALTERNATE CONSTRUCTIONS
16 X
0.08 C SIDE VIEW A1 C
SEATING PLANE
16X
L
DETAIL A 5 4
D2
8
e
EXPOSED PAD 9
NOTE 5
0.575 0.022
16X
K
1 16 16X 13
E2
12
e 3.25 0.128 1.50 0.059
b BOTTOM VIEW 0.50 0.02 0.30 0.012
SCALE 10:1 mm inches
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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ÇÇ ÉÉ ÉÉ
ÉÉ ÉÉ ÉÉ
ÇÇÇ ÇÇÇ
E
EXPOSED Cu
ALTERNATE TERMINAL CONSTRUCTIONS
MOLD CMPD
A3
DIM A A1 A3 b D D2 E E2 e K L L1
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
EXPOSED PAD
NB6HQ14M/D
