NB6L11MMNGEVB

NB6L11M 2.5V / 3.3V 1:2 Differential CML Fanout Buffer Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB6L11M is a differential 1:2 CML fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pins and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single−ended PECL or NECL inputs. For all single−ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor−coupled inputs. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L11M is a member of the ECLinPS MAXt family of high performance clock products. Features • • • • • • • • • • • • Maximum Input Clock Frequency > 4 GHz, Typical 225 ps Typical Propagation Delay 70 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter Differential CML Outputs, 380 mV peak−to−peak, typical LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V NECL Operating Range: VCC = 0 V with VEE = −2.375 V to −3.63 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP, EP, and SG Devices −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices MARKING DIAGRAM* 1 QFN−16 MN SUFFIX CASE 485G 16 NB6L 11M ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 VTD Q0 D D Q1 VTD Q1 VREFAC Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 4 1 Publication Order Number: NB6L11M/D NB6L11M VCC 16 VTD 1 D 2 VEE VEE VCC 15 13 14 Exposed Pad (EP) 12 Q0 11 Q0 NB6L11M D 3 10 Q1 VTD 4 9 Q1 5 6 7 VCC VREFAC VEE 8 VCC Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O 1 VTD − Description 2 D ECL, CML, LVCMOS, LVDS, LVTTL Input Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. 3 D ECL, CML, LVCMOS, LVDS, LVTTL Input Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. 4 VTD − Internal 50 W Termination Pin for D input. 5 VCC − Positive Supply Voltage 6 VREFAC Internal 50 W Termination Pin for D input. Output Reference Voltage for direct or capacitor coupled inputs 7 VEE − Negative Supply Voltage 8 VCC − Positive Supply Voltage 9 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 10 Q1 CML Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 11 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 12 Q0 CML Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC. 13 VCC − Positive Supply Voltage 14 VEE − Negative Supply Voltage 15 VEE − Negative Supply Voltage 16 VCC − Positive Supply Voltage − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation. 2. All VCC and VEE pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB6L11M Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model Moisture Sensitivity 16−QFN Flammability Rating Oxygen Index: 28 to 34 > 2 kV > 200V Level 1 UL 94 V−0 @ 0.125 in Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol Positive Power Supply Parameter VEE = 0 V Condition 1 Condition 2 4.0 V VEE Negative Power Supply VCC = 0 V −4.0 V VIO Positive Input/Output Voltage Negative Input/Output Voltage VEE = 0 V VCC = 0 V 4.0 −4.0 V V VINPP Differential Input Voltage |D − D| VCC − VEE V IIN Input Current Through RT (50 W Resistor) Static Surge 45 80 mA mA IOUT Output Current (CML Output) Continuous Surge 25 50 mA mA IVREFAC VREFAC Sink/Source Current $0.5 mA TA Operating Temperature Range −40 to +85 _C Tstg Storage Temperature Range −65 to +150 _C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfmp 500 lfmp QFN−16 QFN−16 42 35 _C/W _C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4 _C/W Tsol Wave Solder Pb−Free 265 _C −0.5 v VIo v VCC + 0.5 +0.5 v VIo v VEE − 0.5 16 QFN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L11M Table 4. DC CHARACTERISTICS, Multi−Level Inputs VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C Characteristic Symbol Min Typ Max Unit 45 60 75 mA VCC = 3.3 V VCC = 2.5 V VCC − 40 3260 2460 VCC − 10 3290 2490 VCC 3300 2500 mV VCC = 3.3V VCC = 2.5V VCC − 500 2800 2000 VCC − 400 2900 2100 VCC − 300 3000 2200 mV 1125 VCC − 75 mV POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) CML OUTPUTS (Notes 4 and 5) VOH Output HIGH Voltage VOL Output LOW Voltage DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 4 and 5) (Note 6) Vth Input Threshold Reference Voltage Range (Note 7) VIH Single−ended Input HIGH Voltage Vth + 75 VCC mV VIL Single−ended Input LOW Voltage VEE Vth − 75 mV VISE Single−ended Input Voltage Amplitude (VIH − VIL) 150 2800 mV VCC – 1325 mV VREFAC VREFAC Output Reference Voltage (VCC w 2.5 V) VCC – 1525 VCC – 1425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8) VIHD Differential Input HIGH Voltage VEE + 1200 VCC mV VILD Differential Input LOW Voltage VEE VCC − 100 mV VID Differential Input Voltage (VIHD − VILD) VEE + 100 VCC − VEE mV VCMR Input Common Mode Range (Differential Configuration) (Note 9) VEE + 950 VCC − 50 mV IIH Input HIGH Current D / D, (VTD/VTD Open) −150 150 uA IIL Input LOW Current D / D, (VTD/VTD Open) −150 150 uA TERMINATION RESISTORS RTIN Internal Input Termination Resistor 40 50 60 W RTOUT Internal Output Termination Resistor 40 50 60 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. CML outputs loaded with 50 W to VCC for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR min varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L11M Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = −2.375 V to −3.63 V, TA = −40°C to +85°C; (Note 10) Characteristic Symbol VOUTPP Output Voltage Amplitude (@ VINPP(MIN) (Note 15) (See Figure 9) tPD Propagation Delay tSKEW Duty Cycle Skew (Note 11) Within Device Skew Device to Device Skew (Note 12) tDC tJITTER Output Clock Duty Cycle (Reference Duty Cycle = 50%) Peak−to−Peak Data Dependent Jitter (Note 14) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) tr tf Output Rise/Fall Times @ 0.5 GHz (20% − 80%) Typ fin ≤ 3.0GHz fin ≤ 3.5 GHz fin ≤ 4.0 GHz 230 190 150 380 320 270 D to Q 175 225 325 ps 5.0 3.0 15 15 80 ps 50 60 % fin ≤ 4GHz 0.2 0.5 fin ≤ 4Gb/s 40 fin ≤ 4.0GHz RMS Random Clock Jitter (Note 13) VINPP Min 40 150 Q, Q 70 Max Unit mV ps 2800 mV 120 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. http://onsemi.com 5 NB6L11M VTD VCC 50 W RC RC D I D 50 W VTD Figure 3. Input Structure VCC Vthmax D VIH VIHmax VILmax Vth VIH Vth VIL Vth VIL Vthmin D Vth Figure 5. Vth Diagram D D D D Figure 6. Differential Inputs Driven Differentially VIHD(MAX) VIHD VILD D VINPP = VIH(D) − VIL(D) D VIHD VID = VIHD − VILD Q VILD VOUTPP = VOH(Q) − VOL(Q) Q VIHD(MIN) GND VID = |VIHD(D) − VILD(D)| Figure 7. Differential Inputs Driven Differentially VILD(MAX) VCMR VILmin VEE Figure 4. Differential Input Driven Single−Ended VCC VIHmin tPD tPD VIL(MIN) Figure 8. VCMR Diagram Figure 9. AC Reference Measurement http://onsemi.com 6 NB6L11M VCC VCC VCC ZO = 50 W LVPECL Driver Vth ZO = 50 W D VCC ZO = 50 W NB6L11M 50 W VTD VTD ZO = 50 W D NB6L11M 50 W* VTD LVDS Driver 50 W VTD 50 W* IN Vth = VCC − 2 V VEE IN GND VEE GND Figure 10. LVPECL Interface Figure 11. LVDS Interface VCC VCC ZO = 50 W CML Driver IN NB6L11M 50 W* VTD VCC ZO = 50 W VT = VT = VCC VTD 50 W* IN GND GND Figure 12. Standard 50 W Load CML Interface VCC ZO = 50 W Differential Driver VCC VCC Vth ZO = 50 W IN VTD VTD ZO = 50 W NB6L11M 50 W* Single−Ended Driver 50 W* IN Vth IN VTD VTD NB6L11M 50 W* 50 W* IN Vth = External VREFAC GND VCC Vth = External VREFAC GND GND GND Figure 14. Capacitor−Coupled Single−Ended Interface (VT/VT Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) Figure 13. Capacitor−Coupled Differential Interface (VTD/VTD Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) http://onsemi.com 7 VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NB6L11M VCC 800 700 600 500 50 W 50 W 400 Q 300 Q 200 100 0 0 1 2 4 3 fout, CLOCK OUTPUT FREQUENCY (GHz) 16 mA Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) VEE Figure 16. CML Output Structure VCC 50 W Z = 50 W DUT Driver Device 50 W Q D Receiver Device Z = 50 W Q D Figure 17. Typical CML Termination for Output Driver and Device Evaluation ORDERING INFORMATION Device NB6L11MMNG Package Shipping† QFN−16 (Pb−Free) 123 Units / Rail (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. The products described herein (NB4L16M), may be covered by U.S. patents including 6,362,644. There may be other patents pending. ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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