NB6L14SMNG

NB6L14S 2.5 V 1:4 AnyLevel] Differential Input to LVDS Fanout Buffer/Translator The NB6L14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML, LVDS, or HSCL. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6L14S is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The NB6L14S has a wide input common mode range from GND + 50 mV to VCC − 50 mV. Combined with the 50 W internal termination resistors at the inputs, the NB6L14S is ideal for translating a variety of differential or single−ended Clock or Data signals to 350 mV typical LVDS output levels. The NB6L14S is the 2.5 V version of the NB6N14S and is offered in a small 3 mm x 3 mm 16−QFN package. Application notes, models, and support documentation are available at www.onsemi.com. The NB6L14S is a member of the ECLinPS MAX™ family of high performance products. MARKING DIAGRAM* 16 1 NB6L 14S ALYW G G 1 QFN−16 MN SUFFIX CASE 485G A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Features • • • • • • • • • http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. Maximum Input Clock Frequency > 2.0 GHz Maximum Input Data Rate > 2.5 Gb/s 1 ps Maximum of RMS Clock Jitter Typically 10 ps of Data Dependent Jitter 380 ps Typical Propagation Delay 120 ps Typical Rise and Fall Times Single Power Supply; VCC = 2.5 $ 5% VREF_AC Reference Output These are Pb−Free Devices Q0 Q0 Q1 Q1 IN W VT 50 W IN 50 Q2 Q2 VOLTAGE (130 mV/div) EN (LVTTL/CMOS) D Q Q3 VREFAC Q3 Device DDJ = 10 ps Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. TIME (58 ps/div) Figure 2. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps) © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 2 1 Publication Order Number: NB6L14S/D NB6L14S Q0 Q0 VCC GND 16 15 14 Exposed Pad (EP) 13 Q1 1 12 IN Q1 2 11 VT Q2 3 NB6L14S Q2 Table 1. TRUTH TABLE 10 VREFAC 4 9 IN IN IN EN Q Q 0 1 1 0 1 1 0 1 1 0 x x 0 0 (Note 1) 1 (Note 1) 1. On next transition of the input signal (IN). 5 6 7 Q3 Q3 VCC 8 EN Figure 3. NB6L14S Pinout, 16−pin QFN (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 2 Q1 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 3 Q2 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 4 Q2 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 Q3 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 Q3 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 7 VCC − 8 EN LVTTL / LVCMOS Input 9 IN LVPECL, CML, LVDS 10 VREFAC LVPECL Output The VREFAC reference output can only be used to rebias capacitor−coupled differential or single−ended input signals. For the capacitor−coupled IN and/or INb inputs, VREFAC should be connected to the VT pin and bypassed to ground with a 0.01 mF capacitor. Internal 100 W Center−tapped Termination Pin for IN and IN Positive Supply Voltage. Synchronous Output Enable. When LOW, Q outputs will go LOW and Qb outputs will go HIGH on the next negative transition of IN input. The internal DFF register is clocked on the falling edge of IN input; see Figure 26. The EN pin has an internal pullup resistor and defaults HIGH when left open. Inverted Differential Input 11 VT LVPECL Output 12 IN LVPECL, CML, LVDS 13 GND − Negative Supply Voltage. 14 VCC − Positive Supply Voltage. 15 Q0 LVDS Output Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. 16 Q0 LVDS Output Inverted IN output. Typically loaded with 100 W receiver termination resistor across differential pair. − EP − Non−inverted Differential Input. (Note 2) The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 2. In the differential configuration, when the input termination pin (VT) is connected to a termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self−oscillation. http://onsemi.com 2 NB6L14S Table 3. ATTRIBUTES Characteristics Value Moisture Sensitivity (Note 3) Flammability Rating ESD Protection Level 1 Oxygen Index: 28 to 34 Human Body Model Machine Model UL 94 V−0 @ 0.125 in > 2 kV > 200 V Transistor Count 745 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Power Supply GND = 0 V VIN Positive Input GND = 0 V IIN Input Current Through RT (50 W Resistor) Static Surge IOSC Output Short Circuit Current Line−to−Line (Q to Q) Line−to−End (Q or Q to GND) IREF_AC VREF_AC Sink/Source Current TA Operating Temperature Range Tstg Storage Temperature Range qJA Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) 1S2P (Note 4) Tsol Wave Solder Q or Q Q to Q to GND Condition 2 VIN ≤ VCC Continuous Continuous QFN−16 Pb−Free Rating Unit 3.8 V 3.8 V 35 70 mA mA 12 24 mA "0.5 mA −40 to +85 °C −65 to +150 °C QFN−16 QFN−16 41.6 35.2 °C/W °C/W QFN−16 4.0 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L14S Table 5. DC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V, TA = −40°C to +85°C Symbol ICC Characteristic Min Power Supply Current (Note 9) Typ Max Unit 65 100 mA DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 17, 18, 22, and 24) Vth Input Threshold Reference Voltage Range (Note 8) GND +100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV VREFAC Reference Output Voltage (Note 11) VCC − 1.300 V VCC − 1.600 VCC − 1.425 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 10, 12, NO TAG, NO TAG, 23, and 25) VIHD Differential Input HIGH Voltage 100 VCC mV VILD Differential Input LOW Voltage GND VIHD − 100 mV VCMR Input Common Mode Range (Differential Configuration) GND + 50 VCC − 50 mV VID Differential Input Voltage (VIHD − VILD) 100 VCC mV RTIN Internal Input Termination Resistor 40 60 W 450 mV 25 mV 1375 mV 1 25 mV 1425 1600 mV 50 LVDS OUTPUTS (Note 5) VOD Differential Output Voltage 250 DVOD Change in Magnitude of VOD for Complementary Output States (Note 10) VOS Offset Voltage (Figure 21) DVOS Change in Magnitude of VOS for Complementary Output States (Note 10) VOH Output HIGH Voltage (Note 6) VOL Output LOW Voltage (Note 7) 0 1 1125 0 900 1075 mV LVTTL/LVCMOS INPUT, EN VIH Input HIGH Voltage 2.0 VCC V VIL Input LOW Voltage GND 0.8 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 20. 6. VOHmax = VOSmax + ½ VODmax. 7. VOLmax = VOSmin − ½ VODmax. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. Input termination pins open at the DC level within VCMR and output pins loaded with RL = 100 W across differential. 10. Parameter guaranteed by design verification not tested in production. 11. VREFAC used to rebias capacitor−coupled inputs only (see Figures 17 and 18). http://onsemi.com 4 NB6L14S Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 12) −40°C to +85°C Min Characteristic Symbol Typ finMax Maximum Input Clock Frequency VOUTPP Output Voltage Amplitude (@ VINPPmin) (Figure 4) fDATA Maximum Operating Data Rate 2.5 tPLH, tPHL Differential Input to Differential Output, IN to Q Propagation Delay @ 100 MHz 300 450 ts th Setup Time Hold Time 300 500 20 20 tSKEW Within Device Skew (Note 17) Device−to−Device Skew (Note 16) tJITTER RMS Random Clock Jitter (Note 14) Deterministic Jitter (Note 15) VINPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 13) tr tf Output Rise/Fall Times @ 250 MHz (20% − 80%) Max 2.0 fin ≤ 1.0 GHz fin= 1.5 GHz fin= 2.0 GHz 220 200 170 EN to IN/IN 350 300 270 mV Gb/s fin = 2.0 GHz fDATA v 2.488 Gb/s 600 ps 5 30 20 200 ps 0.5 5.0 0.8 20 ps VCC−GND mV 225 ps 100 Q, Q Unit GHz 70 150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W. Input edge rates 150 ps (20%−80%). See Figure 20. 13. Input voltage swing is a single−ended measurement operating in differential mode. 14. RMS jitter with 50% Duty Cycle clock signal at 750 MHz. 15. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5. 16. Skew is measured between outputs under identical transition @ 250 MHz. 17. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition. OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 INPUT CLOCK FREQUENCY (GHz) Figure 4. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V) http://onsemi.com 5 3 NB6L14S Figure 5. Typical Phase Noise Plot at fcarrier = 311.04 MHz Figure 6. Typical Phase Noise Plot at fcarrier = 622.08 MHz Figure 7. Typical Phase Noise Plot at fcarrier = 1 GHz Figure 8. Typical Phase Noise Plot at fcarrier = 1.5 GHz device (integrated between 12 kHz and 20 MHz; as shown in the shaded region of the plot) at each of the frequencies is 65 fs, 29 fs, 24 fs and 20 fs respectively. The input source used for the phase noise measurements is Agilent E8663B. The above phase noise plots captured using Agilent E5052A show additive phase noise of the NB6L14S device at frequencies 311.04 MHz, 622.08 MHz, 1 GHz and 1.5 GHz respectively at an operating voltage of 2.5 V in room temperature. The RMS Phase Jitter contributed by the http://onsemi.com 6 VOLTAGE (63.23 mV/div) NB6L14S Device DDJ = 10 ps TIME (58 ps/div) Figure 9. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask (VINPP = 100 mV; Input Signal DDJ = 14 ps) VCC = 3.3 V or 2.5 V VCC = 2.5 V VCC = 3.3 V or 2.5 V VCC VCC = 2.5 V 0.1 mF Zo = 50 W LVPECL Driver NB6L14S IN 50 W VT = VCC − 2.0 V Zo = 50 W 19 W GND VEE / GND Figure 10. LVPECL Interface GND VCC = 2.5 V NB6L14S IN Zo = 50 W 50 W VT = VCC 50 W Zo = 50 W IN GND NB6L14S IN 50 W CML Driver VT = OPEN Zo = 50 W GND VCC = 2.5 V 50 W LVDS Driver IN Figure 11. LVPECL Y−Termination Interface VCC = 2.5 V Zo = 50 W 50 W 50 W IN VEE / GND VCC = 3.3 V or 2.5 V VT LVPECL Driver 50 W Zo = 50 W NB6L14S IN Zo = 50 W GND IN GND Figure 12. LVDS Interface GND Figure 13. CML Interface http://onsemi.com 7 NB6L14S VCC = 3.3 V or 2.5 V VCC = 2.5 V Zo = 50 W VCC = 2.5 V VCC = 2.5 V NB6L14S IN Zo = 50 W 50 W HSTL Driver VT = GND 50 W Zo = 50 W VT = OPEN LVCMOS Driver NB6L14S IN 50 W* 50 W* IN IN 2.5 kW GND GND GND Figure 14. HSTL Interface VCC = 2.5 V LVTTL Driver VT = OPEN VCC VCC = 2.5 V NB6L14S IN Zo = 50 W 50 W* 50 W* VT = VREFAC* 50 W Zo = 50 W IN GND NB6L14S IN 50 W Differential Driver 1.5 kW GND GND Figure 15. LVCMOS Interface VCC = 2.5 V Zo = 50 W GND GND GND IN GND Figure 17. Capacitor−Coupled Differential Interface (VT Connected to VREF_AC) Figure 16. LVTTL Interface *VREFAC bypassed to ground with a 0.1 mF capacitor. VCC VCC = 2.5 V Zo = 50 W NB6L14S IN 50 W Single−Ended Driver VT = VREFAC* 50 W IN GND GND Figure 18. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) *VREFAC bypassed to ground with a 0.1 mF capacitor. http://onsemi.com 8 NB6L14S IN VINPP = VIH(D) − VIL(D) IN Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 19. AC Reference Measurement Q LVDS Driver Device Zo = 50 W HI Z Probe D 100 W Q Zo = 50 W Oscilloscope D HI Z Probe Figure 20. Typical LVDS Termination for Output Driver and Device Evaluation QN VOH VOS VOD VOL QN Figure 21. LVDS Output IN VIH IN Vth VIL Vth IN IN Figure 22. Differential Input Driven Single−Ended Figure 23. Differential Inputs Driven Differentially VCC VCC VCMRmax VIHmax Vthmax IN VILD(MAX) VILmax VCMR Vth Vthmin GND VIHD(MAX) VIHD VID = VIHD − VILD VILD VIHmin IN VILmin VCMRmin GND Figure 24. Vth Diagram VIHD(MIN) VILD(MIN) Figure 25. VCMR Diagram http://onsemi.com 9 NB6L14S EN VCC/2 VCC/2 tS IN IN tH tpd Q Q Figure 26. EN Timing Diagram Figure 27. Tape and Reel Pin 1 Quadrant Orientation ORDERING INFORMATION Package Shipping† NB6L14SMNG QFN−16, 3 X 3 mm (Pb−Free) 123 Units / Rail NB6L14SMNTXG QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel (Pin 1 Orientation in Quadrant B, Figure 27) NB6L14SMNTWG QFN−16, 3 X 3 mm (Pb−Free) 3000 / Tape & Reel (Pin 1 Orientation in Quadrant A, Figure 27) Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. AnyLevel and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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