NB6L239

NB6L239 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider Features http://onsemi.com The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7). • Maximum Clock Input Frequency, 3.0 GHz • Input Compatibility with LVDS/LVPECL/CML/HSTL • Rise/Fall Time 70 ps Typical • < 10 ps Typical Output−to−Output Skew • Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs • Internal 50 W Termination Provided • Random Clock Jitter < 1 ps RMS • Divide−by−1 Edge of QA Aligned to QB Divided Output • Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • Master Reset for Synchronization of Multiple Chips • VBBAC Reference Output • Synchronous Output Enable/Disable MARKING DIAGRAM* Bottom View QFN−16 MN SUFFIX CASE 485G XXXX A L Y W XXXX XXXX ALYW = Device Code = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. SELA0 SELA1 QA QA CLK VT CLK QB QB EN SELB0 SELB1 MR + Figure 1. Simplified Logic Diagram © Semiconductor Components Industries, LLC, 2004 1 April, 2004 − Rev. 0 Publication Order Number: NB6L239/D NB6L239 MR 16 1 2 NB6L239 CLK VBBAC 3 4 5 EN 6 7 8 10 9 QB QB SELA0 SELA1 VCC 15 14 13 12 11 VT CLK QA QA SELB0 SELB1 VEE Exposed Pad (EP) Figure 2. Pinout: QFN−16 (Top View) Table 1. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VT CLK CLK VBBAC EN* SELB0* SELB1* VEE QB QB QA QA VCC SELA1* SELA0* MR** EP LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply LVPECL Output LVPECL Output LVPECL Output LVPECL Output Power Supply LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply (OPT) LVPECL, CML, LVDS, HSTL Input LVPECL, CML, LVDS, HSTL Input I/O Description Internal 100 W Center−Tapped Termination Pin for CLK and CLK. Noninverted Differential CLOCK Input. Inverted Differential CLOCK Input. Output Voltage Reference for Capacitor Coupled Inputs, Only. Synchronous Output Enable Clock Divide Select Pin Clock Divide Select Pin Negative Supply Voltage Inverted Differential Output. Typically terminated with 50 W resistor to VTT. Noninverted Differential Output. Typically terminated with 50 W resistor to VTT. Inverted Differential Output. Typically terminated with 50 W resistor to VTT. Noninverted Differential Output. Typically terminated with 50 W resistor to VTT. Positive Supply Voltage. Clock Divide Select Pin Clock Divide Select Pin Master Reset Asynchronous, Default Open High, Asserted LOW The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 2 NB6L239 + SELA0 VCC SELA1 B1 B2 B4 R B8 QA QA A CLK VT CLK 50 W 50 W R B2 B4 B EN SELB0 B8 B16 QB QB SELB1 MR VBBAC + VEE Figure 3. Logic Diagram Table 2. FUNCTION TABLES CLK EN* L H X MR** H H L FUNCTION Divide Hold Q Reset Q X Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS SELA1* L L H H SELA0* L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS SELB1* L L H H SELB0* L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16 = Low−to−High Transition = High−to−Low Transition X = Don’t Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 3 NB6L239 Table 5. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 75 kW > 1500 V > 150 V > 1000 V Level 1 UL 94 V−0 @ 0.125 in 367 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. MAXIMUM RATINGS Symbol VCC VI Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Mode Power Supply Input Voltage Output Current VBBAC Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Wave Solder 0 lfpm 500 lfpm Standard Board < 3 sec @ 248°C Condition 1 VEE = 0 V VEE = 0 V Continuous Surge VEE v VI v VCC Condition 2 Rating 3.6 3.6 50 100 ± 0.5 −40 to +85 −65 to +150 41.6 35.2 4.0 265 Units V V mA mA mA °C °C °C/W °C/W °C/W °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 4 NB6L239 Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V) −405C Symbol IEE VOH Characteristic Power Supply Current Output HIGH Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V Output LOW Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V Min 30 VCC−1150 2150 1350 VCC−1870 1430 630 Typ 40 VCC−1060 2240 1440 VCC−1760 1540 740 Max 50 VCC−950 2350 1550 VCC−1630 1670 870 Min 30 VCC−1100 2200 1400 VCC−1820 1480 680 255C Typ 40 VCC−1015 2285 1485 VCC−1700 1600 800 Max 50 VCC − 900 2400 1600 VCC−1580 1720 920 Min 30 VCC−1050 2250 1450 VCC−1770 1530 730 85°C Typ 40 VCC −980 2320 1520 VCC−1660 1640 840 Max 50 VCC − 850 2450 1650 VCC−1530 1770 970 mV Unit mA mV VOL DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10) Vth Input Threshold Reference Voltage (Note 4) Single−ended Input HIGH Voltage Single−ended Input LOW Voltage Output Voltage Reference @ 100 mA (Note 7) VCC = 3.3 V VCC = 2.5 V 100 VCC − 100 100 VCC − 100 100 VCC − 100 mV VIH VIL VBBAC Vth + 100 VEE VCC−1460 1840 1040 VCC−1330 1970 1170 VCC Vth − 100 VCC−1200 2100 1300 Vth + 100 VEE VCC−1460 1840 1040 VCC−1340 1960 1160 VCC Vth − 100 VCC−1200 2100 1300 Vth + 100 VEE VCC−1460 1840 1040 VCC−1350 1950 1150 VCC Vth − 100 VCC−1200 2100 1300 mV mV mV DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 6) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross−point Voltage) (Note 5) Differential Input Voltage (VIHD(CLK) − VILD(CLK)) and (VIHD(CLK)−VILD(CLK)) Internal Input Termination Resistor 100 VEE 50 VCC VCC – 100 VCC – 50 100 VEE 50 VCC VCC – 100 VCC – 50 100 VEE 50 VCC VCC – 100 VCC – 50 mV mV mV VID 100 VCC − VEE 100 VCC − VEE 100 VCC − VEE mV RTIN 45 50 55 45 50 55 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. Outputs loaded with 50 W to VCC – 2.0 V for proper operation. 4. Vth is applied to the complementary input when operating in single−ended mode. 5. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. 6. Input and output voltage swing is a single−ended measurement operating in differential mode. 7. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17). http://onsemi.com 5 NB6L239 Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C) Symbol VIH VIL IIH IIL Characteristic Input HIGH Voltage (LVCMOS/LVTTL) Input LOW Voltage (LVCMOS/LVTTL) Input HIGH Current Input LOW Current Min 2.0 VEE −150 −150 Typ Max VCC 0.8 150 150 Unit V V mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 8) −40°C Symbol fin VOUTPP Characteristic Maximum Input CLOCK Frequency Output Voltage Amplitude (Notes 10, 11) QA(B2, 4, 8), QB(Bn) fin v 3.0 GHz QA(B1), QB(Bn) fin v 2.5 GHz QA(B1), QB(Bn) 2.5 GHz < fin v 3.0 GHz Propagation Delay to Output Differential @ 50 MHz Reset Recovery Setup Time @ 50 MHz Hold Time @ 50 MHz Within−Device Skew @ 50 MHz Device−to−Device Skew Duty Cycle Skew Minimum Pulse Width RMS Random Clock Jitter (See Figure 20. Fmax/JITTER) Input Voltage Swing (Differential Configuration) (Note 10) Output Rise/Fall Times @ 50 MHz (20% − 80%) Qn, Qn 100 30 60 EN, CLK SELA/B, CLK CLK, EN CLK, SELA/B (Note 9) (Note 9) (Note 9) MR 550