NB6L295

NB6L295 2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs Multi−Level Inputs w/ Internal Termination http://onsemi.com The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de−skewing and timing MARKING adjustment. The NB6L295 is versatile in that two individual variable DIAGRAM* delay channels, PD0 and PD1, can be configured in one of two 24 operating modes, a Dual Delay or an Extended Delay. 1 QFN−24 In the Dual Delay Mode, each channel has a programmable delay NB6L MN SUFFIX 295 section which is designed using a matrix of gates and a chain of CASE 485L 24 1 ALYWG multiplexers. There is a fixed minimum delay of 3.2 ns per channel. G The Extended Delay Mode amounts to the additive delay of PD0 A = Assembly Location L = Wafer Lot plus PD1 and is accomplished with the Serial Data Interface MSEL bit Y = Year set High. This will internally cascade the output of PD0 into the input W = Work Week of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 G = Pb−Free Package inputs, flows through PD0, cascades to the PD1 and outputs through (Note: Microdot may be in either location) Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended *For additional marking information, refer to Delay Mode. Application Note AND8002/D. The required delay is accomplished by programming each delay ORDERING INFORMATION channel via a 3−pin Serial Data Interface, described in the application See detailed ordering and shipping information in the package section. The digitally selectable delay has an increment resolution of dimensions section on page 13 of this data sheet. typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode. The Multi−Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24−pin QFN Pb−free package. The NB6L295 is a member of the ECLinPS MAX™ family of high performance products. • Input Clock Frequency > 1.5 GHz with 550 mV • 3 ps Typical Clock Jitter, RMS VOUTPP • 20 ps Pk−Pk Typical Data Dependent Jitter • Input Data Rate > 2.5 Gb/s • LVPECL, CML or LVDS Differential Input Compatible • Programmable Delay Range: 0 ns to 6 ns per Delay • LVPECL, LVCMOS, LVTTL Single−Ended Input Channel Compatible • Programmable Delay Range: 0 ns to 11.2 ns for • 3−Wire Serial Interface Extended Delay Mode • Operating Range: VCC = 2.375 V to 3.6 V • Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel • LVPECL Output Level; 780 mV Peak−to−Peak, Typical • Total Delay Range: 6 ns to 17 ns in Extended Delay • Internal 50 W Input Termination Provided Mode • −40°C to 85°C Ambient Operating Temperature • Monotonic Delay: 11 ps Increments in 511 Steps • 24−Pin QFN, 4 mm x 4 mm • Linearity $20 ps, Maximum • These are Pb−Free Devices* • 100 ps Typical Rise and Fall Times *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 January, 2010 − Rev. 3 1 Publication Order Number: NB6L295/D EN PD0 VT0 50 W 0 256 1 GD* 1 32 GD* 1 1 1 1 1 1 1 128 GD* 1 64 GD* 16 GD* 8 GD* 4 GD* 2 GD* 1 GD* 0 0 0 0 0 0 0 0 0 Q0 Q0 IN0 IN0 50 W VT0 9 Bit Latch *GD = Gate Delay PD1 NB6L295 Figure 1. Simplified Functional Block Diagram http://onsemi.com 1 0 256 1 GD* 1 32 GD* 1 128 GD* 1 64 GD* 16 GD* 1 0 0 0 0 8 GD* 0 0 1 9 Bit Latch *GD = Gate Delay 11 Bit Shift Register D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL 2 VT1 0 4 GD* 1 2 GD* 0 1 1 GD* 0 1 Q1 Q1 50 W IN1 IN1 50 W VT1 SDATA D8 SCLK SLOAD NB6L295 VT0 IN0 24 VCC EN SLOAD SDIN SCLK VCC 1 2 3 4 5 6 7 VT1 8 9 10 VT1 11 12 NB6L295 23 IN0 VT0 GND VCC0 22 21 20 19 18 17 16 15 14 13 Exposed Pad (EP) Q0 Q0 VCC0 VCC1 Q1 Q1 Figure 2. Pinout: QFN−24 (Top View) Table 1. PIN DESCRIPTION Pin 1 2 3 IN1 IN1 GND VCC1 Name VCC EN SLOAD I/O Power Supply LVCMOS/LVTTL Input LVCMOS/LVTTL Input Description Positive Supply Voltage for the Inputs and Core Logic Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default state LOW (37 kW pulldown resistor). Serial Load; This pin loads the configuration latches with the contents of the shift register. The latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH− to−LOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown resistor). Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin Default state LOW (37 kW pulldown resistor). Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor). Positive Supply Voltage for the Inputs and Core Logic Internal 50 W Termination Pin for IN1 Non−inverted differential input. Note 1. Inverted differential input. Note 1. Internal 50 W Termination Pin for IN1 Negative Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1 Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to VCC1 − 2.0 V. Non−inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to VCC1 − 2.0 V. Positive Supply Voltage for the Q1/Q1 outputs, channel PD1 Positive Supply Voltage for the Q0/Q0 outputs, channel PD0 Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to VCC0 − 2.0 V. Non−inverted Differential Output . Channel 0. Typically terminated with 50 W resistor to VCC0 − 2.0 V. Positive Supply Voltage for the Q0/Q0 outputs, channel PD0 Negative Power Supply Internal 50 W Termination Pin for IN0 Inverted differential input. Note 1. Noninverted differential input. Note 1. Internal 50 W Termination Pin for IN0 The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND and must be connected to GND on the PC board. 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 − SDIN SCLK VCC VT1 IN1 IN1 VT1 GND VCC1 Q1 Q1 VCC1 VCC0 Q0 Q0 VCC0 GND VT0 IN0 IN0 VT0 EP LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input Power Supply Power Supply LVPECL Output LVPECL Output Power Supply Power Supply LVPECL Output LVPECL Output Power Supply Power Supply LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input Ground 1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and if no signal is applied on INx/INx input then the device will be susceptible to self−oscillation. 2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate. http://onsemi.com 3 NB6L295 Table 2. ATTRIBUTES Characteristics Input Default State Resistors ESD Protection Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Human Body Model Machine Model QFN−24 Oxygen Index: 28 to 34 Value 37 kW > 2 kV > 100V Level 1 UL 94 V−0 @ 0.125 in 3094 Table 3. MAXIMUM RATINGS Symbol VCC, VCC0, VCC1 VIO VINPP IIN IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input/Output Voltage Differential Input Voltage |INx − INx| Condition 1 GND = 0 V GND = 0 V −0.5 v VIO v VCC + 0.5 Condition 2 Rating 4.0 4.5 VCC − GND $50 Continuous Surge 50 100 −40 to +85 −65 to +150 0 lfpm 500 lfpm (Note 4) QFN−24 QFN−24 QFN−24 37 32 11 265 Unit V V V mA mA mA °C °C °C/W °C/W °C/W °C Input Current Through RT (50 W Resistor) Output Current (LVPECL Output) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 4) Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 4 NB6L295 Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs, VTx and Outputs Open) (Sum of ICC, ICC0, and ICC1) 110 140 170 mA Characteristic Min Typ Max Unit LVPECL OUTPUTS (Notes 5 and 6, Figure 21) VOH Output HIGH Voltage VCC = VCC0 = VCC1 = 3.3 V VCC = VCC0 = VCC1 = 2.5 V VCC = VCC0 = VCC1 = 3.3 V VCC = VCC0 = VCC1 = 2.5 V VCC − 1075 2225 1425 VCC − 1825 1475 VCC − 1825 675 VCC − 950 2350 1550 VCC − 1725 1575 VCC − 1725 775 VCC − 825 2475 1675 VCC − 1625 1675 VCC − 1600 900 mV VOL Output LOW Voltage mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 10 and 11) (Note 7) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN Input Threshold Reference Voltage Range Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage Amplitude (VIH − VIL) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage Swing (INx, INx) (VIHD − VILD) Input Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current INx/INx, (VTn/VTn Open) Input LOW Current IN/INX, (VTn/VTn Open) 1050 Vth + 150 GND 300 VCC − 150 VCC Vth − 150 VCC − GND VCC VCC − 150 VCC − GND VCC – 75 150 150 mV mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 12 and 13) (Note 8) 1200 GND 150 950 −150 −150 mV mV mV mV mA mA SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Input HIGH Current Input LOW Current 2000 GND −150 −150 VCC 800 150 150 mV mV mA mA TERMINATION RESISTORS Internal Input Termination Resistor 40 50 60 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVPECL outputs loaded with 50 W to VCC − 2.0 V for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR(min) varies 1:1 with voltage on GND Pin, VCMR(max) varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB6L295 Table 5. AC CHARACTERISTICS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 10) Symbol fSCLK VOUTPP fDATA tRange Characteristic Serial Clock Input Frequency, 50% Duty Cycle Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.5 GHz (Note 15) (See Figure 22) Maximum Data Rate (Note 14) Programmable Delay Range (@ 50 MHz) Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 Extended Mode IN0/IN0 to Q1/Q1 Duty Cycle Skew (Note 11) Within Device Skew − Dual Mode Linearity (Note 12) Setup Time (@ 20 MHz) SDIN to SCLK SLOAD to SCLK EN to SDIN SDIN to SCLK SLOAD to SCLK EN to SLOAD 0.5 1.5 0.5 1.0 1.0 0.5 1 3 6 20 150 85 120 10 20 30 VCC − GND 170 mV ps D[8:0] = 0 D[8:0] = 1 530 2.5 0 0 0 5.7 11.2 2 60 60 $15 0.3 1.0 0.6 6.9 13.7 5 100 175 $20 780 Min Typ Max 20 Unit MHz mV Gb/s ns tSKEW ps Lin ts ps ns th Hold Time ns tpwmin tJITTER Minimum Pulse Width SLOAD Random Clock Jitter RMS; SETMIN to SETMAX (Note 13) fin ≤ 1.5 GHz Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 Extended Mode IN0/IN0 to Q1/Q1 Deterministic Jitter; SETMIN to SETMAX (Note 14) fDATA ≤ 2.5 Gbps Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15) Output Rise/Fall Times (@ 50 MHz), (20% − 80%) Qx, Qx ns ps VINPP tr, tf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPPmin and VINPPmax from a 50% duty cycle clock source, VCMR (min+max). All loading with an external RL = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz. 12. Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps. 13. Additive random CLOCK jitter with 50% duty cycle input clock signal. 14. NRZ data at PRBS23 and K28.5. 15. Input and output voltage swing is a single−ended measurement operating in differential mode. http://onsemi.com 6 NB6L295 Table 6. AC CHARACTERISTICS VCC = VCC0 = VCC1 = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 16) −405C Symbol tPLH, tPHL Characteristic Propagation Delay (@ 50 MHz) Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 D[8:0] = 0 D[8:0] = 1 Extended Mode IIN0/IN0 to Q1/Q1 D[8:0] = 0 D[8:0] = 1 Min Typ Max Min +255C Typ Max Min +855C Typ Max Unit ns 2.7 7.2 5.0 14.2 2.9 8.0 5.5 15.2 3.2 8.8 6.0 17.1 2.8 7.5 5.2 14.8 3.1 8.4 5.8 16.5 3.4 9.3 6.3 18.2 2.9 7.9 5.5 15.6 3.2 9.2 6.2 16.4 3.6 9.9 6.8 19.6 ns D0 HIGH D1 HIGH D2 HIGH D3 HIGH D4 HIGH D5 HIGH D6 HIGH D7 HIGH D8 HIGH 9.6 19.4 40 81 167 338 678 1358 2715 8.7 19 42 85 175 355 714 1432 2861 11 24.4 52 99 196 389 774 1544 3074 Dt Step Delay (Selected D Bit HIGH All Others LOW) NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 16. Measured by forcing VINPPmin and VINPPmax from a 50% duty cycle clock source, VCMR (min+max). All loading with an external RL = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% − 80%). http://onsemi.com 7 NB6L295 Serial Data Interface Programming The NB6L295 is programmed by loading the 11−Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11−bit load cycle is required to program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5 and 6. DUAL MODE OPERATIONS PD0 Programmable Delay 0/1 D8 0/1 D7 0/1 D6 0/1 D5 0/1 D4 0/1 D3 0/1 D2 0/1 D1 0/1 D0 Control Bits 0 MSEL 0 PSEL (LSB) Value Bit Name 0/1 D8 0/1 D7 PD1 Programmable Delay 0/1 D6 0/1 D5 0/1 D4 0/1 D3 0/1 D2 0/1 D1 0/1 D0 Control Bits 0 MSEL 1 PSEL (LSB) Value Bit Name (MSB) (MSB) Figure 3. PDO Shift Register EXTENDED MODE OPERATIONS PD0 Programmable Delay 0/1 D8 0/1 D7 0/1 D6 0/1 D5 0/1 D4 0/1 D3 0/1 D2 0/1 D1 0/1 D0 Control Bits 1 MSEL 0 PSEL (LSB) Value Bit Name 0/1 D8 0/1 D7 Figure 4. PD1 Shift Register PD1 Programmable Delay 0/1 D6 0/1 D5 0/1 D4 0/1 D3 0/1 D2 0/1 D1 0/1 D0 Control Bits 1 MSEL 1 PSEL (LSB) Value Bit Name (MSB) (MSB) Figure 5. PDO Shift Register Figure 6. PD1 Shift Register Refer to Table 7, Channel and Mode Select BIT Functions. In a load cycle, the 11−Bit Shift Register least significant bit (clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and the device uses both channels independently. A pulse edge entering IN0/IN0 is delayed according to the values in PD0 and exits from Q0/Q0. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1. When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 and flows through PD0 and is extended through PD1 to exit at Q1 and Q1. The most significant 9−bits, D[8:0] are delay value data for both channels. See Figure 7. Table 7. CHANNEL AND MODE SELECT BIT FUNCTIONS BIT Name PSEL 0 Loads Data to PD0 1 Loads Data to PD1 MSEL 0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path 1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs, Q0−LOW, Q0−HIGH. D[8:0] Select one of 512 Delay Values Function http://onsemi.com 8 NB6L295 Q0/Q0 Q1/Q1 PD0 Delay MSEL PD1 Delay D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 PD0 Latch 0 1 PD1 Latch D8 D7 D6 D5 D4 D3 SCLK 11−Bit Shift Register Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels Serial Data Interface Loading Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by using the SCLK input pin and latching the data with the SLOAD input pin. The 11−bit SHIFT REGISTER shifts once per rising edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOW−to−HIGH edge transition (transparent state) into a data Latch register and latches the data with a subsequent HIGH−to−LOW edge transition. Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence. Input EN should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After programming, the EN should be returned LOW (enabled) for functional delay operation. EN LSB PSEL SDIN MSEL D0 D1 D2 D3 D4 D5 D6 D7 MSB D8 SCLK SLOAD ts SDIN to SCLK C0 C1 C2 C3 C4 C5 D2 D1 D0 SDATA C6 MSEL PSEL C7 C8 D2 D1 D0 C9 SLOAD C10 ts SCLK to SLOAD th SDIN to SCLK tpwmin Figure 8. SDI Timing Diagram http://onsemi.com 9 NB6L295 Table 8 shows theoretical values of delay capabilities in both the Dual Delay Mode and in the Extended Delay Modes of operation. Table 8. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN DUAL MODE INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1 Dual Mode PD1 D[8:0] 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 (Decimal) (0) (0) (0) (0) (0) (0) (0) (0) (0) PD0 D[8:0] 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001000 • • • 000000000 000000000 000000000 000000000 000000000 000000000 (0) (0) (0) (0) (0) (0) 000010000 000100000 001000000 111111101 111111110 111111111 (16) (32) (64) (509) (510) (511) 0 0 0 0 0 0 (Decimal) (0) (1) (2) (3) (4) (5) (6) (7) (8) MSEL 0 0 0 0 0 0 0 0 0 PD0 Delay* (ps) 0 11 22 33 44 55 66 77 88 • • • 176 352 704 5599 5610 5621 PD1 Delay* (ps) 0 0 0 0 0 0 0 0 0 • • • 0 0 0 0 0 0 *Fixed minimum delay not included Table 9. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN EXTENDED MODE INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1 Extended Delay Mode PD1 D[8:0] 000000000 000000000 000000000 000000000 (Decimal) (0) (0) (0) (0) PD0 D[8:0] 000000000 000000001 000000010 000000011 • • • 000000000 000000000 000000000 000000001 000000010 (0) (0) (0) (1) (2) 111111101 111111110 111111111 111111111 111111111 • • • 111111100 111111101 111111110 111111111 (508) (509) (510) (511) 111111111 111111111 111111111 111111111 (511) (511) (511) (511) 1 1 1 1 (509) (510) (511) (511) (511) 1 1 1 1 1 (Decimal) (0) (1) (2) (3) MSEL 1 1 1 1 PD0* (ps) 0 0 0 0 • • • 0 0 0 11 22 • • • 5588 5599 5610 5621 PD1* (ps) 0 11 22 33 • • • 5599 5610 5621 5621 5621 • • • 5621 5621 5621 5621 Total Delay* (ps) 0 11 22 33 • • • 5599 5610 5621 5632 5643 • • • 11209 11220 11231 11242 *Fixed minimum delay not included http://onsemi.com 10 NB6L295 VTx 50 W INx VCC I INx 50 W VTx Figure 9. Input Structure VIH Vth VIL INx VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin Vth INx Vth Vthmin GND Figure 10. Differential Input Driven Single−Ended Figure 11. Vth Diagram INx INx INx INx VID = |VIHD(INx) − VILD(INx)| VIHD VILD Figure 12. Differential Inputs Driven Differentially Figure 13. Differential Inputs Driven Differentially VCC VIHD(MAX) VILD(MAX) INx INx VINPP = VIH(INx) − VIL(INx) VCMR VIHD VID = VIHD − VILD VILD VIHD(MIN) Qx Qx tPD VOUTPP = VOH(Qx) − VOL(Qx) tPD GND VILD(MIN) Figure 14. VCMR Diagram Figure 15. AC Reference Measurement http://onsemi.com 11 NB6L295 VCC VCC VCC VCC INx Zo = 50 W LVPECL Driver VTx VTx Zo = 50 W INx GND VTx = VTx = VCC − 2.0 V NB6L295 50 W 50 W LVDS Driver INx Zo = 50 W VTx VTx Zo = 50 W VTx = VTx INx NB6L295 50 W* 50 W* GND GND GND Figure 16. LVPECL Interface Figure 17. LVDS Interface VCC VCC INx Zo = 50 W CML Driver VTx VCC VTx Zo = 50 W INx VTx = VTx = VCC GND NB6L295 50 W* 50 W* GND Figure 18. CML Interface, Standard 50 W Load VCC VCC VCC VCC INx Zo = 50 W Differential Driver VTx VREFAC VTx Zo = 50 W INx NB6L295 Zo = 50 W 50 W* 50 W* Single−Ended Driver VREFAC VTx VTx INx NB6L295 50 W* 50 W* INx VTx = VTx = External VREFAC GND GND GND VTx = VTx = External VREFAC GND Figure 19. Capacitor−Coupled Differential Interface (VTx/VTx Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) Figure 20. Capacitor−Coupled Single−Ended Interface (VTx/VTx Connected to External VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) http://onsemi.com 12 NB6L295 Z = 50 W Q Driver Device Q 50 W 50 W Z = 50 W D D Receiver Device VTT VTT = VCC − 2.0 V Figure 21. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) 800 VOUTPP, TYPICAL OUTPUT VOLTAGE AMPLITUDE (mV) 700 600 500 400 300 200 100 0 0 0.5 1.0 1.5 2.0 fOUT, CLOCK OUTPUT FREQUENCY (GHz) Figure 22. Output Voltage Amplitude (VOUTPP) vs. Output Frequency at Ambient Temperature (Typical) ORDERING INFORMATION Device NB6L295MNG NB6L295MNTXG Package QFN−24 (Pb−free) QFN−24 (Pb−free) Shipping† 92 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 13 NB6L295 PACKAGE DIMENSIONS QFN24, 4x4, 0.5P MN SUFFIX CASE 485L−01 ISSUE A D PIN 1 IDENTIFICATION A B E 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.20 0.30 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.30 0.50 0.15 C 2X 0.15 C A2 0.10 C A 0.08 C SEATING PLANE A1 D2 L 7 6 A3 REF C DIM A A1 A2 A3 b D D2 E E2 e L e 12 13 E2 24X b 1 24 19 18 0.10 C A B 0.05 C e ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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