NB7L111MMN

NB7L111M 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output Description The NB7L111M is a low skew 1–to–10 differential clock/data driver, designed with clock/data distribution in mind. It accepts two clock/data sources into multiplexer input and reproduces ten identical CML differential outputs. This device is ideal for clock/data distribution across the backplane or a board, and redundant clock switchover applications. The input signals can be either differential or single–ended (if the external reference voltage is provided). Differential inputs incorporate internal 50 W termination resistors and accept Negative ECL (NECL), Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using appropriate power supplies). The differential 16 mA CML output provides matching internal 50 W termination, and 400 mV output swing when externally terminated 50 W to VCC. The NB7L111M operates from a 2.5 V $5% supply or a 3.3 V $5% supply and is guaranteed over the full industrial temperature range of −40°C to +85°C. This device is packaged in a low profile 8x8 mm, QFN−52 package with 0.5 mm pitch (see package dimension on the back of the datasheet). Application notes, models, and support documentation are available at www.onsemi.com. Features http://onsemi.com 1 52 QFN−52 MN SUFFIX CASE 485M MARKING DIAGRAM* 52 1 NB7L 111M AWLYYWWG • • • • • • • • • • • • • Maximum Input Clock Frequency > 5.5 GHz Typical Maximum Input Data Rate > 6.125 Gb/s Typical < 0.5 ps Maximum Clock RMS Jitter < 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s 50 ps Typical Rise and Fall Times 240 ps Typical Propagation Delay 2 ps Typical Duty Cycle Skew 10 ps Typical Within Device Skew 15 ps Typical Device−to−Device Skew Operating Range: VCC = 2.5 V $5 and 3.3 V $5 400 mV Differential CML Output Swing 50 W Internal Input and Output Termination Resistors Pb−Free Packages are Available* A WL YY WW G = Assembly Site = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 1 1 Publication Order Number: NB7L111M/D NB7L111M VCC VCC VEE VEE VEE 40 39 38 37 36 35 34 NC NC 41 Q0 Q0 Q1 Q1 Q2 44 Q2 43 Exposed Pad (EP) 52 51 50 49 48 47 46 45 VEE VTCLK0 CLK0 CLK0 VTCLK0 VTSEL SEL SEL VTSEL VTCLK1 CLK1 CLK1 VTCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 42 VCC Q3 Q3 VEE Q4 Q4 VEE Q5 Q5 VEE Q6 Q6 VCC QFN52 33 32 31 30 29 28 27 NC VCC VCC VEE VEE NC Figure 1. Pinout (Top View) Q0 VCC VEE Q0 Q1 Q1 Q2 VTCLK0 50 W CLK0 CLK0 50 W VTCLK0 VTCLK1 50 W CLK1 CLK1 50 W VTCLK1 VTSEL 50 W SEL SEL VTSEL 50 W R2 R3 1 0 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 R1 Q8 Q8 Q9 Q9 Figure 2. Logic Diagram Table 1. FUNCTION TABLE SEL LOW HIGH SEL HIGH LOW CLK0/CLK0 ON OFF CLK1/CLK1 OFF ON http://onsemi.com 2 VEE Q9 Q9 Q8 Q8 Q7 Q7 NB7L111M Table 2. PIN DESCRIPTION Pin 15, 24, 27, 39, 42, 51 1, 18, 21, 26, 30, 33, 36, 40, 45, 48 2 3 Name VCC VEE VTCLK0 CLK0 I/O − − − LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input − Description Positive supply voltage. All VCC pins must be externally connected to power supply to guarantee proper operation. Negative supply voltage. All VEE pins must be externally connected to power supply to guarantee proper operation. Internal 50 W termination pin for CLK0. (Note 2) Non−inverted differential clock/data input 0 (Note 2). 4 CLK0 Inverted differential clock/data input 0 (Note 2). 5 6 7 VTCLK0 VTSEL SEL Internal 50 W termination pin for CLK0. (Note 2) Internal 50 W termination pin for SEL. (Note 2) LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input − LVPECL, CML, LVCMOS, LVTTL, LVDS Input LVPECL, CML, LVCMOS, LVTTL, LVDS Input − − CML Outputs CML Outputs − Non−inverted differential clock/data select input. Internal 75 kW to VEE. 8 SEL Inverted differential clock/data select input. Internal 56 KW to VCC and 56 kW to VEE bias this pin to (VCC−VEE)/2. Internal 50 W termination pin for SEL. (Note 2) 9 VTSEL 10 11 VTCLK1 CLK1 Internal 50 W termination pin for CLK1. (Note 2) Non−inverted differential clock/data input 1 (Note 2). 12 CLK1 Inverted differential clock/data input 1 (Note 2). 13 14, 25, 41, 52 17, 20, 23, 29, 32, 35, 38, 44, 47, 50 16, 19, 22, 28, 31, 34, 37, 43, 46, 49 EP VTCLK1 NC Q[0−9] Q[0−9] − Internal 50 W termination pin for CLK1. (Note 2) Non−inverted CML outputs [0−9] with internal 50 W source termination resistor (Note 1). Inverted CML outputs [0−9] with internal 50 W source termination resistor (Note 1). Exposed Pad (EP). The thermally exposed pad on package bottom (see case drawing) must be attached to a heat−sinking conduit on the printed circuit board. 1. CML output requires 50 W receiver termination resistor to VCC for proper operation. 2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation. http://onsemi.com 3 NB7L111M Table 3. ATTRIBUTES Characteristics Input Default State Resistors ESD Protection Moisture Sensitivity (Note 3) QFN−52 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 R1, R3 R2 Human Body Model Machine Model Pb Pkg Level 2 Value 56 kW 75 kW > 1400 V > 80 V Pb−Free Pkg Level 1 UL 94 V−0 @ 0.125 in 339 Table 4. MAXIMUM RATINGS (Note 4) Symbol VCC VI VINPP Iin Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Input Voltage Differential Input Voltage |CLK − CLK| Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 5) Thermal Resistance (Junction−to−Case) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm 1S2P (Note 8) QFN52 QFN52 Condition 1 VEE = 0 V VEE = 0 V VCC − VEE ≥ 2.8 V VCC − VEE < 2.8 V Continuous Surge Continuous Surge QFN52 VEE v VI v VCC Condition 2 Rating 3.6 3.6 2.8 |VCC − VEE| 25 50 25 50 −40 to +85 −65 to +150 25 19.6 21 265 265 Unit V V V V mA mA mA mA °C °C °C/W °C/W °C/W °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 4. Maximum Ratings are those values beyond which device damage may occur. 5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power). http://onsemi.com 4 NB7L111M Table 5. DC CHARACTERISTICS VCC = 2.375 V 2.625 V and 3.135 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C (Notes 6 and 7) Symbol ICC Characteristic Power Supply Current (Inputs and Outputs Open) VCC = 2.375 V to 2.625 V VCC = 3.135 V to 3.465 V Output HIGH Voltage (Notes 6 and 7) Output LOW Voltage (Notes 6 and 7) VCC = 2.375 V to 2.625 V VCC = 3.135 V to 3.465 V Min 255 270 VCC − 40 VCC − 440 VCC − 490 Typ 290 305 VCC − 20 VCC − 350 VCC − 400 Max 325 340 VCC VCC – 290 VCC − 340 Unit mA VOH VOL mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (See Figures 13 and 15) Vth VIH VIL VIHD VILD VCMR VID IIH IIL RTIN RTOUT RTemp Coef Input Threshold Reference Voltage Range (Note 8) Single−ended Input HIGH Voltage (Note 7) Single−ended Input LOW Voltage (Note 7) 1125 Vth + 75 VEE 1200 VEE 1163 75 CLK[0−1]/CLK[0−1] SEL/SEL CLK[0−1]/CLK[0−1] SEL/SEL −100 −150 −100 −150 45 45 5 5 50 50 −3.75 VCC – 75 VCC VCC – 150 VCC VCC – 75 VCC – 37 2500 100 150 100 150 55 55 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 14 and 16) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) (Note 9) Differential Input Voltage (VIHD − VILD) Input HIGH Current (Termination Pins Open) Input LOW Current (Termination Pins Open) Internal Input Termination Resistor Internal Output Termination Resistor Internal I/O Termination Resistor Temperature Coefficient mV mV mV mV mA mA W W mW/C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. CML outputs require 50 W receiver termination resistors to VCC for proper operation. 7. Input and output parameters vary 1:1 with VCC. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VCMR(MIN) varies 1:1 with VEE, VCMR(MAX) varies 1:1 with VCC. http://onsemi.com 5 NB7L111M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V and 3.135 V to 3.465 V, VEE = 0 V; (Note 10) −40°C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ Vinppmin) (See Figures 3, 4, 5, and 6) VCC = 2.375 V to 2.625 V fin ≤ 3 GHz fin ≤ 5.5 GHz VCC = 3.135 V to 3.465 V fin ≤ 3 GHz fin ≤ 5.5 GHz Maximum Operating Data Rate Differential Input−to−Output Propagation Delay @ 1 GHz (See Figures 7 and 11) CLK−Q SEL−Q Duty Cycle Skew (Note 11) Within Device Skew Device−to−Device Skew (Note 15) RMS Random Clock Jitter (Note 13) fin = 3 GHz fin = 5.5 GHz Peak−to−Peak Data Dependent Jitter (Note 14) fDATA = 3.125 Gb/s fDATA = 5 Gb/s fDATA = 6.125 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 12 and Figures 3, 4, 5, and 6) Output Rise/Fall Times @ 1 GHz (20% − 80%) 75 Min Typ Max Min 25°C Typ Max Min 85°C Typ Max Unit mV 240 115 250 130 5 200 290 330 220 350 250 6 240 340 2 10 15 0.2 0.2 6 15 15 400 280 390 15 20 80 0.5 0.5 15 25 25 2500 75 240 115 250 130 5 200 290 330 220 350 250 6 240 340 2 10 15 0.2 0.2 6 15 15 400 280 390 15 20 80 0.5 0.5 15 25 25 2500 75 240 115 250 130 5 200 290 330 220 350 250 6 240 340 2 10 15 0.2 0.2 6 15 15 400 280 390 15 20 80 0.5 0.5 15 25 25 2500 mV Gb/s ps fDATA tPLH, tPHL tSKEW ps tJITTER ps VINPP tr tf 50 75 50 75 50 75 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% − 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. 12. VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1. 15. Device−to−device skew is measured between outputs under identical transition and conditions @ 1 GHz. http://onsemi.com 6 NB7L111M OUTPUT VOLTAGE AMPLITUDE (mV) OUTPUT VOLTAGE AMPLITUDE (mV) 400 350 300 250 200 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 6.5 25 85 −40 400 350 300 250 200 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 6.5 85 25 −40 INPUT CLOCK FREQUENCY (GHz) INPUT CLOCK FREQUENCY (GHz) Figure 3. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 400 mV; VCC = 3.3 V) Figure 4. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 75 mV; VCC = 3.3 V) OUTPUT VOLTAGE AMPLITUDE (mV) 350 300 250 200 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 6.5 INPUT CLOCK FREQUENCY (GHz) 85 25 −40 OUTPUT VOLTAGE AMPLITUDE (mV) 400 400 350 300 250 200 150 100 50 0 1 2 3 3.5 4 4.5 5 5.5 6 6.5 25 85 −40 INPUT CLOCK FREQUENCY (GHz) Figure 5. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 400 mV; VCC = 2.5 V) Figure 6. Output Voltage Amplitude vs. Input Clock Frequency and Temperature (Vinpp = 75 mV; VCC = 2.5 V) 280 PROPAGATION DELAY (ps) 270 260 250 240 230 220 210 200 −40 25 Temperature (°C) 85 Typical Tpd Figure 7. Propagation Delay versus Temperature http://onsemi.com 7 NB7L111M VOLTAGE (50 mV/div) VOLTAGE (50 mV/div) Device DDJ = 6 ps Device DDJ = 7 ps TIME (22.1 ps/div) TIME (22.1 ps/div) Figure 8. Typical Output Waveform at 3.125 Gb/s with PRBS 223−1 (Vinpp = 75 mV−left and 400 mV−right) VOLTAGE (40 mv/ div) Device DDJ=16ps VOLTAGE (40 mv/ div) Device DDJ=17ps TIME (22.1 ps/div) TIME (22.1 ps/div) Figure 9. Typical Output Waveform at 5 Gb/s with PRBS 223−1 (Vinpp=75 mV−left and 400 mV−right) VOLTAGE (35 mv/div) Device DDJ=12ps VOLTAGE (35 mv/div) Device DDJ=15ps TIME (22.1 ps/div) TIME (22.1 ps/div) Figure 10. Typical Output Waveform at 6.125 Gb/s with PRBS 223−1 (Vinpp = 75 mV−left and 400 mV−right) http://onsemi.com 8 NB7L111M CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 11. AC Reference Measurement NB7L111M VCC VCC Receiver Device 50 W Q 50 W 50 W 50 W CLK Q CLK Figure 12. Typical Termination for 16 mA Output Drive and Device Evaluation CLK Vth CLK CLK Vth CLK Figure 13. Differential Input Driven Single−Ended Figure 14. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VCC VCMmax VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp Vth Vthmin GND VCMR VCMmax GND VIHDmin VILDmin Figure 15. Vth Diagram Figure 16. VCMR Diagram http://onsemi.com 9 NB7L111M VCC 50 W 50 W Q Q 16 mA VEE Figure 17. CML Output Structure Table 7. Interfacing Options INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, LVPECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL, VTSEL to VCC Connect VTCLK0, VTCLK0 together for CLK0 input; Connect VTCLK1, VTCLK1 together for CLK1 input; Connect VTSEL, VTSEL together for SEL control input. Bias VTCLK0, VTCLK0, VTSEL, VTSEL and VTCLK1, VTCLK1 inputs within (VCMR) Common Mode Range. Standard ECL termination techniques. See AND8020. An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. http://onsemi.com 10 NB7L111M Application Information All NB7L111M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are VCC minimum input swing of 100 mV and the maximum input swing of 450 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). VCC 50 W 50 W Q CML or NB7L111M Z CLK VCC VTCLK VCC VTCLK CLK VEE 50 W CML or NB7L111M Z Q VEE 50 W Figure 18. CML to CML Interface VCC VCC 50 W PECL Driver Recommended RT Values VCC RT VEE 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W RT VEE 50 W RT Z VBIAS* VBIAS* Z CLK VTCLK VTCLK CLK VEE 50 W NB7L111M 50 W Figure 19. PECL to CML Receiver Interface *VBIAS is within VCMR Range. VCC VCC LVDS Driver Z CLK VTCLK VTCLK 50 W 50 W NB7L111M Z CLK VEE VEE Figure 20. LVDS to CML Receiver Interface http://onsemi.com 11 NB7L111M VCC VCC Z LVTTL/ LVCMOS Driver No Connect No Connect VREF CLK 50 W VTCLK VTCLK NB7L111M 50 W CLK VCC Recommended VREF Values VREF LVCMOS VCC * VEE 2 LVTTL 1.5 V VEE Figure 21. LVCMOS/LVTTL to CML Receiver Interface ORDERING INFORMATION Device NB7L111MMN NB7L111MMNG NB7L1MMNR2 NB7L1MMNR2G Package QFN−52 QFN−52 (Pb−Free) QFN−52 QFN−52 (Pb−Free) Shipping † 46 Units / Rail 46 Units / Rail 2000 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NB7L111M PACKAGE DIMENSIONS 52 PIN QFN 8x8 CASE 485M−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A2 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 −−− 0.30 0.50 E 2X 0.15 C 2X 0.15 C 0.10 C 0.08 C SEATING PLANE A2 A A1 D2 14 26 27 13 A3 REF C 52 X L E2 1 52 X 39 52 40 K e 52 X b NOTE 3 0.10 C A B 0.05 C GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 13 NB7L111M/D