NB7N017MMNR2G

NB7N017M 3.3V SiGe 8−Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs The NB7N017M is a high speed 8–bit dual modulus programmable divider/prescaler with 16 mA CML outputs capable of switching at input frequencies greater than 3.5 GHz. The CML output structure contains internal 50 W source termination resistor to VCC. The device generates 400 mV output amplitude with 50 W receiver resistor to VCC. This I/O structure enables easy implementation of the NB7N017M in 50 W systems. The differential inputs contain 50 W termination resistors to VT pads and all differential inputs accept RSECL, ECL, LVDS, LVCMOS, LVTTL, and CML. Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmable down counter. A select pin, SEL, is used to select between two words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb respectively. Two parallel load pins, PLa and PLb, are used to load the level triggered programming registers, REGa and REGb, respectively. A differential clock enable, CE, pin is available. The NB7N017M offers a differential output, TC. Terminal count output, TC, goes high for one clock cycle when the counter has reached the all zeros state. To reduce output phase noise, TC is retimed with the rising edge triggered latches. • Maximum Input Clock Frequency > 3.5 GHz Typical • Differential CLK Clock Input • Differential CE Clock Enable Input • Differential SEL Word Select Input • 50 W Internal Input and Output Termination Resistors • Differential TC Terminal Count Output • All Outputs 16 mA CML with 50 W Internal Source Termination to VCC • All Single–Ended Control Pins CMOS and PECL/NECL Compatible • Counter Programmed Using One of Two Single−Ended Words, Pa[0:7] and Pb[0:7], Stored in REGa and REGb • REGa and REGb Implemented with Level Triggered Latch • Compatible with Existing 3.3 V LVEP, EP, and SG Devices • Ability to Program the Divider without Disturbing Current Settings • Positive CML Output Operating Range: VCC = 3.0 V to 3.465 V with VEE = 0 V • Negative CML Output Operating Range: VCC = 0 V with VEE = –3.0 V to –3.465 V • VBB Reference Voltage Output • CML Output Level: 400 mV Peak−Peak Output with 50 W Receiver Resistor to VCC • Pb−Free Packages are Available* http://onsemi.com 1 52 QFN−52 MN SUFFIX CASE 485M MARKING DIAGRAM* 52 1 NB7N 017M AWLYYWW NB7N017M A WL YY WW = Device Code = Assembly Site = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.  Semiconductor Components Industries, LLC, 2004 November, 2004 − Rev. 0 1 Publication Order Number: NB7N017M/D NB7N017M VTCLK VTCLK VTSEL VTSEL VTCE VTCE CLK CLK SEL SEL VBB CE CE Exposed Pad (EP) 52 51 50 49 48 47 46 45 44 43 42 41 40 VCC PLa Pa0 Pa1 Pa2 VCC Pa3 VEE Pa4 Pa5 Pa6 Pa7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 VEE PLb Pb0 Pb1 Pb2 VCC Pb3 VEE Pb4 Pb5 Pb6 Pb7 NC NB7N017M 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 VEE TC NC NC TC VCC VCC VCC VEE VEE NC Figure 1. Pinout (Top View) http://onsemi.com 2 VEE MR 26 NB7N017M Table 1. PIN DESCRIPTION Pin Name CLK CE MR I/O ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input CMOS, ECL Input Default State − − Low Single/Differential (Notes 1 and 2) Differential Differential Single Clock Clock Enable Asynchronous Master Reset: Counter set to 0000 0000 to reload at next CLK pulse, REGa and REGb = 1111 1111 and TC = 1. Divide Select Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level Triggered) Terminal Count, 16 mA CML output with 50 W Source Termination to VCC (Note 5) Counter Program Pins. CMOS and PECL/NECL compatible Pa7 = MSB, Pb7 = MSB Positive Supply Negative Supply 50 W Internal Input Termination Resistor (Note 6) Description SEL PLa, PLb TC Pa[0:7], Pb[0:7] VCC VEE VTCLK, VTCLK, VTSEL, VTSEL VTCE, VTCE VBB NC EP ECL, CML, LVCMOS, LVDS, LVTTL Input CMOS, ECL Input CML Output CMOS, ECL Input Power Power Termination − Low − High − Differential Single Differential Single − − Differential − − Output N/A − − − − − CMOS/ECL Reference Voltage Output No Connect (Note 4) Exposed Pad (Note 3) − − ÑÑÑÑÑÑÑÑÑÑÑÑ Ñ Ñ ÑÑÑÑÑÑÑÑÑÑÑÑ 1. All high speed inputs and outputs are differential to improve performance. 2. All single−ended inputs are CMOS and NECL/ECL compatible. 3. All VCC and VEE pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Exposed pad is bonded to the lowest voltage potential, VEE. 4. The NC pins are electrically connected to the die and must be left open. 5. CML outputs require 50 W receiver termination resistor to VCC for proper operation. 6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation. http://onsemi.com 3 NB7N017M Table 2. CE Truth Table CE LOW HIGH Clock Status Clock Disabled Clock Enabled LOW HIGH Table 3. SEL Truth Table SEL Active Register REGa REGb Table 4. Register Programming Values for Various Divide Ratios Pa7/Pb7 0 0 0 0 − − 1 1 1 Pa6/Pb6 0 0 0 0 − − 1 1 1 Pa5/Pb5 0 0 0 0 − − 1 1 1 Pa4/Pb4 0 0 0 0 − − 1 1 1 Pa3/Pb3 0 0 0 0 − − 1 1 1 Pa2/Pb2 0 0 0 0 − − 1 1 1 Pa1/Pb1 0 0 1 1 − − 0 1 1 Pa0/Pb0 0 1 0 1 − − 1 0 1 Divide By undefined 2 3 4 − − 254 255 256 Table 5. Function Table MR H L L L L L Pla X H L L L X PLb X L H L L X SEL X X X L H X CE X X X H H L CLK X X X Z Z X Function Master Reset (Counter programmed to 0000 0000, REGa and REGb programmed to 1111 1111 and TC to 1) REGa is transparent to Pa[0:7] REGb is transparent Pb[0:7] Count; At TC pulse, load counter from REGa Count; At TC pulse, load counter from REGb Hold X − Don’t Care H − HIGH L − LOW Z − Rising Edge http://onsemi.com 4 NB7N017M VCC R1 R2 QINTERNAL QINTERNAL CLK CLK RT = 50 W RT = 50 W VTCLK VTCLK VEE Figure 2. Input Structure VCC RT = 50 W RT = 50 W Q Q DINTERNAL DINTERNAL 16 mA VEE Figure 3. Output Structure http://onsemi.com 5 NB7N017M CLK CLK CE CE MR MUX_OUT[7:0] SEL SEL Pa_INT[7:0] TCLD MUX Pb_INT[7:0] MR CLK_INT GENERATOR CLK_INT 8−BIT COUNTER Counter_State [7:0] TC GENERATOR TC_INT DFF TC TC CLK_INT MR PLa 8−BIT REGa 8−BIT REGb PLb Pa[7:0] Pb[7:0] Figure 4. Block Diagram Table 6. Interface Options CLK INPUT interfacing options CML LVDS AC−COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CLK INPUT INTERFACING OPTIONS Connect VTCLK and VTCLK to VCC Connect VTCLK and VTCLK together Bias VTCLK and VTCLK Inputs within (VIHCMR) Common Mode Range Standard ECL Termination Techniques or connect VTCLK and VTCLK to VTT An Entered Voltage Should be Applied to the unused Complementary Differential Input. Nominal Voltage is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. Table 7. ATTRIBUTES Characteristic Internal Input Pulldown Resistor (MR, PLa, PLb) Internal Input Pullup Resistor (Pa[0:7], Pb[0:7]) ESD Protection Human Body Model Machine Model Charged Device Model Value 75 k to VEE 75 k to VCC >500 V >10 V >2 kV Level 2 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in 1914 Moisture Sensitivity (Note 7) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 7. For additional information, see Application Note AND8003/D. http://onsemi.com 6 NB7N017M Table 8. MAXIMUM RATINGS Symbol VCC VEE VI VINPP Iin Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |CLK − CLK| Input Current through RT (50 W Resistor) Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 8) Thermal Resistance (Junction−to−Case) Wave Solder 0 lfpm 500 lfpm 2S2P (Note 8) < 2 to 3 seconds 52 QFN 52 QFN 52 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC − VEE w 2.8 V Continuous Surge Continuous Surge VI ≤ VCC VI ≥ VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 V 25 50 25 50 $0.5 −40 to +85 −65 to +150 25 − 32 20 − 27 4 − 15 265 Units V V V V V mA mA mA mA °C °C °C/W °C/W °C/W °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 7 NB7N017M Table 9. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 3.0 V to 3.465 V; VEE = 0 V (Note 11) −40°C Symbol ICC VOH VOL Characteristic Positive Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Min 170 VCC −40 Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Min 170 VCC −40 25°C Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Min 170 VCC −40 85°C Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Unit mA mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21) Vth VIH VIL Input Threshold Reference Voltage Range (Note 9) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross−Point Voltage) (Note 10) Differential Input Voltage Output Voltage Reference @ −100 mA Internal Input Termination Resistor Internal Output Resistor Input HIGH Current CLK, CE, SEL MR, PLa, PLb Pa[0:7], Pb[0:7] CLK, CE, SEL MR, PLa, PLb Pa[0:7], Pb[0:7] VEE +1200 VEE VEE +1200 VEE +100 1840 45 45 0 0 −50 −0.5 0 −50 1970 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC 2100 55 55 15 60 0 0.5 60 0 VEE +1200 VEE VEE +1200 VEE +100 1840 45 45 0 0 −50 −0.5 0 −50 1960 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC 2100 55 55 15 60 0 0.5 60 0 VEE +1200 VEE VEE +1200 VEE +100 1820 45 45 0 0 −50 −0.5 0 −50 1970 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC 2100 55 55 15 60 0 0.5 60 0 mV mV mV VID VBB RTIN RTOUT IIH mV mV W W mA IIL Input LOW Current mA 20 −20 20 −20 20 −20 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Vth is applied to the complementary input when operating in single−ended mode. 10. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V. 12. All loading with 50 W to VCC. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 8 NB7N017M Table 10. DC CHARACTERISTICS, NEGATIVE CML OUTPUT VCC = 0 V; VEE = −3.465 V to −3.0 V (Note 16) −40°C Symbol ICC VOH VOL Characteristic Positive Power Supply Current Output HIGH Voltage (Note 17) Output LOW Voltage (Note 17) Min 170 VCC −40 Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Min 170 VCC −40 25°C Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Min 170 VCC −40 85°C Typ 200 VCC −10 VCC −400 Max 230 VCC VCC −330 Unit mA mV mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21) Vth VIH VIL Input Threshold Reference Voltage Range (Note 14) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 VEE +1125 Vth +75 VEE VCC −75 VCC Vth −75 mV mV mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross−Point Voltage) (Note 15) Differential Input Voltage Output Voltage Reference @ −100 mA Internal Input Termination Resistor Internal Output Resistor Input HIGH Current CLK, CE, SEL MR, PLa, PLb Pa[0:7], Pb[0:7] CLK, CE, SEL MR, PLa, PLb Pa[0:7], Pb[0:7] VEE +1200 VEE VEE +1200 VEE +100 −1460 45 45 0 0 −50 −0.5 0 −50 −1330 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC −1200 55 55 15 60 0 0.5 60 0 VEE +1200 VEE VEE +1200 VEE +100 −1460 45 45 0 0 −50 −0.5 0 −50 −1330 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC −1200 55 55 15 60 0 0.5 60 0 VEE +1200 VEE VEE +1200 VEE +100 −1460 45 45 0 0 −50 −0.5 0 −50 −1330 50 50 7 30 −10 VCC VCC −75 VCC −50 VCC −1200 55 55 15 60 0 0.5 60 0 mV mV mV VID VBB RTIN RTOUT IIH mV mV W W mA IIL Input LOW Current mA 20 −20 20 −20 20 −20 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Vth is applied to the complementary input when operating in single−ended mode. 15. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. 16. Input and output parameters vary 1:1 with VCC. 17. All loading with 50 W to VCC. 18. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 9 NB7N017M Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −3.0 V or VCC = 3.0 V to 3.465 V; VEE = 0 V (Note 19) −40°C Symbol VOUTPP Characteristic Output Voltage Amplitude @ B 2 Mode fin = 3.5 GHz (See Figure 5) Propagation Delay to Output Differential CLK to TC MR to TC RMS Random Clock Jitter fin = 3.5 GHz (See Figure 5) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 20) Output Rise/Fall Times (20% − 80%) Setup Time (Figure 23) Pa[7:0] to PLa Pb[7:0] to PLb CE to CLK SEL to CLK PLa to CLK PLb to CLK Pa[7:0] to CLK Pb[7:0] to CLK PLa to Pa[7:0] PLb to Pb[7:0] CLK to CE CLK to SEL CLK to PLa CLK to PLb CLK to PLb[7:0] CLK to PLb[7:0] Device−to−Device (Note 21) Minimum Pulse Width Reset Recovery MR MR to TC 250 3000 100 25 3750 4500 400 300 2500 3250 4750 3000 −1500 −1250 450 0 −1750 −2250 −2250 −2000 45 2500 2000 30 120 2000 2750 3500 2500 −2700 −1900 40 −110 −1900 −2700 −3200 −2500 40 85 2500 75 250 3000 Min 300 Typ 400 Max Min 300 25°C Typ 400 Max Min 300 85°C Typ 400 Max Unit mV tPLH, tPHL tJITTER VINPP tr tf ts 435 100 555 500 2.5 2500 65 455 100 575 500 3.0 475 100 595 500 3.0 ps ps mV ps ps 100 25 3750 4500 400 300 2500 3250 4750 3000 −1500 −1250 450 0 −1750 −2250 −2250 −2000 45 2500 2000 30 120 2000 2750 3500 2500 −2700 −1900 40 −110 −1900 −2700 −3200 −2500 40 85 2500 2500 65 100 25 3750 4500 400 300 2500 3250 4750 3000 −1500 −1250 450 0 −1750 −2250 −2250 −2000 45 2500 2000 30 120 2000 2750 3500 2500 −2700 −1900 40 −110 −1900 −2700 −3200 −2500 40 250 3000 85 2500 2500 65 tH Hold Time (Figure 23) ps tSKEW tPW tRR 75 75 ps ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 19. Measured using a 400 mV source, 50% duty cycle clock source at fin = 1 GHz unless stated otherwise. All loading with 50 W to VCC. Input edge rates 40 ps (20% − 80%). 20. VINPP (MAX) cannot exceed VCC − VEE. 21. Device−to−Device skew for identical transitions at identical VCC levels. OUTPUT VOLTAGE AMPLITUDE (mV) 400 VOUTPP 300 4 3 200 2 100 RMS Jitter 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 INPUT FREQUENCY (MHz) Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) @ Ambient Temperature (Typical) http://onsemi.com 10 JITTEROUT ps (RMS) NB7N017M Application Information All NB7N017M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are VCC minimum input swing of 100 mV and the maximum input swing of 450 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). VCC 50 W 50 W 7N017M Q Z CLK VCC VTCLK VCC VTCLK CLK VEE 50 W 7N017M Z Q VEE 50 W Figure 6. CML to CML Interface VCC VCC 50 W PECL Driver Recommended RT Values VCC RT VEE 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W RT VEE 50 W RT Z VBIAS* VBIAS* Z CLK VTCLK VTCLK CLK VEE 50 W 7N017M 50 W Figure 7. PECL to CML Receiver Interface *VBIAS is within VCMR Range. VCC VCC LVDS Driver Z CLK VTCLK VTCLK 50 W 50 W 7N017M Z CLK VEE VEE Figure 8. LVDS to CML Receiver Interface http://onsemi.com 11 NB7N017M VCC VCC Z LVTTL/ LVCMOS Driver No Connect No Connect VREF CLK 50 W VTCLK VTCLK 50 W CLK VCC Recommended VREF Values VREF LVCMOS VCC * VEE 2 LVTTL 1.5 V 7N017M VEE Figure 9. LVCMOS/LVTTL to CML Receiver Interface Table 12. OPERATION TABLE MR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pa XXXXXXXX 00000101 00000101 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PLa x H H L L L L L L L L L L L L L L L L L L L L L L L L Pb XXXXXXXX 00000100 00000100 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PLb X H H L L L L L L L L L L L L L L L L L L L L L L L L SEL X X X L X X X X X X X X X X X L X X X X X X X X X X X CE X H H H H H H H H H H H H H H H H H H H H H H H H H H CLK X L L H L H L H L H L H L H L H L H L H L H L H L H L CLK_INT X H H H L H L H L H L H L H L H L H L H L H L H L H L TC_INT X H X X X X X X X X X X X X X X X X X X X X X X X X X TC X H X X X X X X X X X X X X X X X X X X X X X X X X X X − Don’t Care H − HIGH L − LOW http://onsemi.com 12 NB7N017M Table 12. OPERATION TABLE MR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pa XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000010 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PLa L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L Pb XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000001 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PLb L L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L SEL H X X X X X X X X X H X X X X X X X X X X X X X H X X X L X X X X L L X X X X L L X X CE H H H H H H H H H H H H H H L L H H L H H L H H H H H H H H H H H H H H H H H H H H H CLK H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H CLK_INT H L H L H L H L H L H L H L H H H L H H H L H L H L H L H L H L H L H L H L H L H L H TC_INT X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X TC X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X − Don’t Care H − HIGH L − LOW http://onsemi.com 13 NB7N017M MR Pa[7:0] PLa Pa_INT[7:0] Pb[7:0] PLb Pb_INT[7:0] SEL CE CLK CLK_INT TC_INT TC 04 01 05 02 05 XX 02 XX 04 XX 01 XX Figure 10. Device Timing Diagram for Table 12 MR CLK CE CLK_INT Figure 11. Timing Diagram for CE Input http://onsemi.com 14 NB7N017M MR delay CLK PLa Pa[7:0] d=12 0B d=12 d=12 TC[7:0] Figure 12. Timing Diagram for PLa / PLb Inputs (SEL is Low) MR delay CLK PLa Pa[7:0] TC[7:0] d=256 d=256 (hex) 0B d=12 d=12 Figure 13. Timing Diagram for PLa / PLb Inputs (Before Critical Rising Edge of CLK) (SEL is Low) MR delay CLK PLa (hex) Pa[7:0] d=256 d=256 0B d=256 d=256 d=12 TC[7:0] Figure 14. Timing Diagram for PLa / PLb Inputs (After Critical Rising Edge of CLK) (SEL is Low) http://onsemi.com 15 NB7N017M MR CLK SEL Pa[7:0] Pb[7:0] PLa PLb d=4 d=4 delay 03 02 d=4 TC[7:0] d=3 d=3 Figure 15. Timing Diagram for SEL Input (Before Critical Rising Edge of CLK) MR CLK SEL Pa[7:0] Pb[7:0] PLa PLb d=4 d=4 delay 03 02 d=4 d=4 d=3 TC[7:0] Figure 16. Timing Diagram for SEL Input (After Critical Rising Edge of CLK) MR CLK Pa[7:0] PLa Pa_INT[7:0] Pb[7:0] PLb Pb_INT[7:0] SEL MUX_INT[7:0] 01 255 103 255 201 02 03 2 255 201 10 04 05 5 151 151 06 6 27 27 43 43 07 7 176 08 Pb/PLb have the same functionality as Pa/PLa MUX_OUT is the output of the internal MUX 255 2 5 27 43 151 Figure 17. Timing Diagram Relating PLa, PLb, Pa(0:7), Pb(0:7) http://onsemi.com 16 NB7N017M CLK VINPP = VIH(CLK) − VIL(CLK) CLK TC VOUTPP = VOH(TC) − VOL(TC) TC tPHL tPLH Figure 18. AC Reference Measurement Vth D D D Vth D Figure 19. Differential Input Driven Single−Ended Figure 20. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VCC VCMmax Vth Vthmin GND VCMR VIHDmax VILDmax VID = VIHD − VILD VIHDtyp VILDtyp VIHDmin VILDmin VCMmax GND Figure 21. Vth Diagram Figure 22. VCMR Diagram http://onsemi.com 17 NB7N017M CLK Setup Time + ts − Hold Time − th + Figure 23. Setup and Hold Time NB7N017M VCC VCC Receiver Device 50 W Q 50 W 50 W 50 W D Q D Figure 24. Typical Termination for 16 mA Output Drive and Device Evaluation ORDERING INFORMATION Device NB7N017MMN NB7N017MMNG* NB7N017MMNR2 NB7N017MMNR2G* Package QFN−52 QFN−52 (Pb−Free) QFN−52 QFN−52 (Pb−Free) Shipping† 260 Units / Tray 260 Units / Tray 2000 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Future Product − Contact factory for availability. http://onsemi.com 18 NB7N017M PACKAGE DIMENSIONS QFN−52, 8 x 8 mm, 0.5 mm Pitch Quad Flat No Lead Package CASE 485M−01 ISSUE O D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 −−− 0.35 0.45 E 2X 0.15 C 2X 0.15 C 0.10 C 0.08 C SEATING PLANE A2 A A1 D2 14 26 27 13 DIM A A1 A2 A3 b D D2 E E2 e K L A3 REF C 52 X L E2 1 52 X 39 52 40 K e 52 X b NOTE 3 0.10 C A B 0.05 C http://onsemi.com 19 NB7N017M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 20 NB7N017M/D