NB7NPQ1104MMTTWG

3.3 V USB 3.1 Gen-2 10Gbps Quad Channel / Dual Port Linear Redriver NB7NPQ1104M Description The NB7NPQ1104M is a high performance 2−Port linear redriver designed for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications that supports both 5 Gbps and 10 Gbps data rates. Signal integrity degrades from PCB traces, transmission cables, and inter−symbol interference (ISI). The NB7NPQ1104M compensates for these losses by engaging varying levels of equalization at the input receiver, and flat gain amplification on the output transmitter. The NB7NPQ1104M offers programmable equalization and flat gain for each independent channel to optimize performance over various physical mediums. The NB7NPQ1104M contains an automatic receiver detect function which will determine whether the output is active. The receiver detection loop will be active if the corresponding channel’s signal detector is idle for a period of time. The channel will then move to Unplug Mode if a load is not detected, or it will return to Low Power Mode (Slumber mode) due to inactivity. The NB7NPQ1104M comes in a 3.5 x 9 mm WQFN42 package and is specified to operate across the entire industrial temperature range, –40°C to 85°C. Features • • • • • • • • • • • • • www.onsemi.com MARKING DIAGRAM 1 NB7N 1104 AWLYYWWG WQFN42 CASE 510AP NB7N1104 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION Device Package Shipping† NB7NPQ1104MMTTWG WQFN42 5000 / Tape 3.3 V ± 0.3 V Power Supply (Pb−Free) & Reel 5 Gbps & 10 Gbps Serial Link with Linear Amplifier †For information on tape and reel specifications, including part orientation and tape sizes, please Device Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates refer to our Tape and Reel Packaging Specifications Automatic Receiver Detection Brochure, BRD8011/D. Integrated Input and Output Termination Pin Adjustable Receiver Equalization and Flat Gain 100−W Differential CML I/O’s Typical Applications Auto Slumber Mode for Adaptive Power Management • USB3.1 Type−A and Type−C Signal Routing Hot−Plug Capable • Mobile Phone and Tablet ESD Protection ±4 kV HBM • Computer, Laptop and Notebook Operating Temperature Range Industrial: • External Storage Device −40°C to +85°C • Docking Station and Dongle Package: WQFN42, 3.5 x 9 mm • Active Cable, Back Planes This is a Pb−Free Device • Gaming Console, Smart T.V. © Semiconductor Components Industries, LLC, 2019 June, 2020 − Rev. 2 1 Publication Order Number: NB7NPQ1104M/D NB7NPQ1104M A_RX+ Receiver/ Equalizer FGA Driver B_TX+ B_TX− Detect A_RX− Driver Receiver/ Equalizer NC NC NC 42 41 40 39 FGA 1 38 NC EN_AB 2 37 NC VDD 3 36 VDD A_RX+ 4 35 A_TX+ A_RX- 5 34 A_TX- TEST1# 6 33 NC B_RX+ VDD 7 32 VDD B_RX− B_TX+ 8 31 B_RX+ B_TX- 9 30 B_RX- FGC 10 29 EQB EN_AB Detect EQA EQA A_TX+ A_TX− EQB FGB Exposed Pad GND 12 27 C_TX- EQC C_RX+ 13 26 C_TX+ VDD 14 25 VDD NC 15 24 TEST2# D_TX- 16 23 D_RX- D_TX+ 17 22 D_RX+ C_RX− Receiver/ Equalizer Driver D_TX− D_TX+ Detect C_RX+ C_TX− C_TX+ D_RX− Driver FGD Receiver/ Equalizer EQD D_RX+ EN_CD Figure 1. Logic Diagram of NB7NPQ1104M 18 19 20 21 VDD C_RX- EN_CD FGB FGD 28 EQD 11 Detect EQC FGC Figure 2. WQFN−42 Package Pinout (Top View) www.onsemi.com 2 NB7NPQ1104M Table 1. PIN DESCRIPTION Pin Number Pin Name Type Description 1 FGA INPUT DC flat gain for channel A. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down. 2 EN_AB INPUT Channel AB Enable. Internal 300 k−W pull−up. High−Channel is in normal operation. Low− Channel is in power down mode. 3 VDD POWER 4 A_RX+ INPUT 5 A_RX− Channel A Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC− coupled in system. UFP/DFP transmitter should provide this capacitor. 6 Test1# INPUT Connect to VDD is recommended. 3.3 V power supply. VDD pins must be externally connected to power supply. 7 VDD POWER 3.3 V power supply. VDD pins must be externally connected to power supply. 8 B_TX+ OUTPUT 9 B_TX− Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system. 10 FGC INPUT DC flat gain for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down. 11 EQC INPUT EQ select for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down. 12 C_RX− INPUT 13 C_RX+ Channel C Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC− coupled in system. UFP/DFP transmitter should provide this capacitor. 14 VDD POWER 3.3 V power supply. VDD pins must be externally connected to power supply. 15 NC NC 16 D_TX− OUTPUT No Connect pin: connect to VDD is recommended 17 D_TX+ Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system. 18 EQD INPUT EQ select for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down. 19 FGD INPUT DC flat gain for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down. 20 EN_CD INPUT Channel CD Enable. Internal 300k−W pull−up. High−Channel is in normal operation. Low− Channel is in power down mode. 21 VDD POWER 22 D_ RX+ INPUT 23 D_ RX− Channel D Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC− coupled in system. UFP/DFP transmitter should provide this capacitor. 24 Test2# INPUT Connect to VDD is recommended. 25 VDD POWER 3.3 V power supply. VDD pins must be externally connected to power supply. 26 C_TX+ OUTPUT 27 C_TX− Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system. 3.3 V power supply. VDD pins must be externally connected to power supply. 28 FGB INPUT DC flat gain for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down. 29 EQB INPUT EQ select for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down. 30 B_ RX− INPUT 31 B_ RX+ Channel B Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC− coupled in system. UFP/DFP transmitter should provide this capacitor. 32 VDD POWER 3.3 V power supply. VDD pins must be externally connected to power supply. 33 NC NC 34 A_TX− OUTPUT 35 A_TX+ Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system. 3.3 V power supply. VDD pins must be externally connected to power supply. 36 VDD POWER 37, 38, 39, 40, 41 NC NC 42 EQA INPUT EP GND GND No Connect pin: connect to VDD is recommended No Connect EQ select for channel A. 4−level input pin. Internal 100k−W pull−up and 200k−W pull−down. Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat transfer out of the package. The exposed pad is electrically connected to the die and must be soldered to GND on the PC Board. www.onsemi.com 3 NB7NPQ1104M Power Management Table 3. EQUALIZATION SETTING The NB7NPQ1104M has an adaptive power management feature in order to minimize power consumption. When the receiver signal detector is idle, the corresponding channel will change to low power slumber mode. Accordingly, both channels will move to low power slumber mode individually. While in the low power slumber mode, the receiver signal detector will continue to monitor the input channel. If a channel is in low power slumber mode, the receiver detection loop will be active again. If a load is not detected, then the channel will move to Device Unplug Mode and continuously monitor for the load. When a load is detected, the channel will return to Low Power Slumber Mode and receiver detection will be active again per 6 ms. EQ A/B/C/D are the selection pins for the equalization. EQA/B/C/D RIN ROUT 67 k−W to GND High−Z Unplug Mode High−Z 40 k−W to VDD Low Power Slumber Mode 50−W to VDD 40 k−W to VDD Active 50−W to VDD 50−W to VDD PD @5 GHz L (Tie 0−W to GND) 5.0 11.5 R (Tie Rext to GND) 2.7 7.4 F (Leave Open) 4.0 9.9 (Default) H (Tie 0−W to VDD) 6.5 13.1 Table 4. FLAT GAIN SETTING FGA/B/C/D are the selection pins for the DC gain. Table 2. OPERATING MODES Mode Equalizer Setting (dB) @2.5 GHz FGA/B/C/D Flat Gain Settings (dB) L (Tie 0−W to GND) −1.2 R (Tie Rext to GND) 0 F (Leave Open) +1.0 (Default) H (Tie 0−W to VDD) +2.0 Table 5. CHANNEL ENABLE SETTING EN_AB / EN_CD are the channel enable pins for channels A&B and C&D respectively. EN Channel Enable Setting 0 Disabled 1 Enabled (Default) Table 6. ATTRIBUTES Parameter ESD Protection Human Body Model Charged Device Model ± 4 kV > 1.5 kV Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−O @ 0.125 in Transistor Count 81034 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test 1. For additional information, see Application Note AND8003/D. Table 7. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted) Parameter Description Min Max Unit VDD −0.5 4.6 V Differential I/O −0.5 VDD + 0.5 V LVCMOS inputs −0.5 VDD + 0.5 V −25 +25 mA 1.2 W Supply Voltage (Note 2) Voltage range at any input or output terminal Output Current Power Dissipation, Continuous Storage Temperature Range, TSG 150 °C Maximum Junction Temperature, TJ −65 125 °C Junction−to−Ambient Thermal Resistance @ 500 lfm, ØJA (Note 3) 34 °C/W Wave Solder, Pb−Free, TSOL 265 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. All voltage values are with respect to the GND terminals. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). www.onsemi.com 4 NB7NPQ1104M Table 8. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted) Description Parameter VDD TA CAC Main power supply Operating free−air temperature Industrial Temperature Range AC coupling capacitor Min Typ Max Unit 3.0 3.3 3.6 V +85 °C 265 nF −40 75 100 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 9. POWER SUPPLY CHARACTERISTICS and LATENCY Symbol Parameter VDD Supply Voltage IDDActive Active mode current IDDLPSlumber Low Power Slumber mode current IDDUnplug Test Conditions Min 3.0 Typ (Note 4) Max Unit 3.3 3.6 V EN_AB & EN_CD = 1, 10 Gbps, compliance test pattern 225 334 mA EN_AB & EN_CD = 1, no input signal longer than TLPSlumber 0.8 1.2 mA 0.5 0.75 mA 20 100 mA 2 ns Unplug mode current EN_AB & EN_CD = 1, no output load is detected IDDpd Power−down mode current EN_AB & EN_CD = 0 tpd Latency From Input to Output 4. TYP values use VDD = 3.3 V, TA = 25°C Table 10. LVCMOS CONTROL PIN CHARACTERISTICS VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted) Min Typ Max Unit DC Input Logic High 0.65 x VDD VDD VDD V VIL DC Input Logic Low GND GND 0.35 x VDD V IIH High−level input current 25 mA IIL Low−level input current Symbol Parameter Test Conditions 2−Level Control Pins LVCMOS Inputs (EN_AB, EN_CD) VIH −25 mA 4−Level Control Pins LVCMOS Inputs (EQA/B/C/D, FGA/B/C/D) VIH DC Input Logic High; Setting “H” Input pin connected to VDD VIF DC Input Logic 2/3 VDD; Setting “F” Input pin is left floating (Open) (Note 5) VIR VDD V 0.59 x VDD 0.67*VDD 0.75 x VDD V DC Input Logic 1/3 VDD; Setting “R” Rext 68 kW must be between pin and GND 0.25 x VDD 0.33*VDD 0.41 x VDD V VIL DC Input Logic Low; Setting “L” IIH High−level input current IIL Low−level input current Rext External Resistor for input setting “R” 0.92 x VDD Input pin connected to GND GND 0.08 x VDD V 50 mA −50 Rext connect to GND (±5%) 5. Floating refers to a pin left in an open state, with no external connections. www.onsemi.com 5 64.6 mA 68 71.4 kW NB7NPQ1104M Table 11. CML RECEIVER AC/DC CHARACTERISTICS VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted) Symbol RRX−DIFF−DC RRX−SINGLE−DC Parameter Test Conditions Differential Input Impedance (DC) Single−ended Input Impedance (DC) Measured with respect to GND over a voltage of 500 mV max. ZRX−HIZ−DC−PD Common−mode input impedance for VCM = 0 to 500 mV V>0 during reset or power−down (DC) Cac_coupling AC coupling capacitance VRX−CM−AC−P Common mode peak voltage VRX−CM−DC−Acti Common mode peak voltage ve−Idle−Delta−P |AvgU0(|V RX−D++VRX−D−|)/2 –AvgU1(|VRX−D++VRX−D−|)/2| Min Typ Max Unit 72 100 120 W 30 W 18 25 kW 75 265 nF AC up to 5 GHz 150 mVpeak Between U0 and U1. AC up to 5 GHz 200 mVpeak Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 12. TRANSMITTER AC/DC CHARACTERISTICS VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted) Parameter VTX−DIFF−PP Output differential p−p voltage swing at 100 MHz RTX−DIFF−DC Differential TX impedance (DC) VTX−RCV−DET Voltage change allowed during receiver detect Cac_coupling AC coupling capacitance Test Conditions Min Typ Differential Swing |VTX−D+−VTX−D−| 72 75 100 Max Unit 1.2 VPPd 120 W 600 mV 265 nF TTX−EYE(10Gbps) Transmitter eye, Include all jitter At the silicon pad. 10Gbps 0.646 UI TTX−EYE(5Gbps) At the silicon pad. 5Gbps 0.625 UI Transmitter eye, Include all jitter TTX−DJ−DD(10Gbps) Transmitter deterministic jitter At the silicon pad. 10Gbps 0.17 UI TTX−DJ−DD(5Gbps) Transmitter deterministic jitter At the silicon pad. 5Gbps 0.205 UI 1.1 pF Ctxparasitic Parasitic capacitor for TX RTX−DC−CM Common−mode output imped− ance (DC) 18 30 W VTX−DC−CM Instantaneous allowed DC com|VTX−D++VTX−D−|/2 mon mode voltage at the connector side of the AC coupling capacitors 0 2.2 V VDD – 1.5 VDD V VTX−CM−AC−PP− TX AC common−mode peak−to− VTX−D++VTX−D− for both time and amActive peak voltage swing in active mode plitude 100 mVPP VTX−CM−DC−Active_ Common mode delta voltage Idle−Delta |AvgU0(|VTX−D++VTX−D−|)/2 –AvgU1(|VTX−D++VTX−D−|)/2| 200 mVpeak 10 mVppd 10 mV VTX−C Common−mode voltage |VTX−D++VTX−D−|/2 Between U0 to U1 VTX−Idle−DIFF−AC−pp Idle mode AC common mode delta Between TX+ and TX− in idle mode. voltage |VTX−D+−VTX−D−| Use the HPF to remove DC components. 1/LPF. No AC and DC signals are applied to RX terminals. VTX−Idle−DIFF−DC Idle mode DC common mode delta voltage |VTX−D+−VTX−D−| Between TX+ and TX− in idle mode. Use the LPF to remove DC components. 1/HPF. No AC and DC signals are applied to RX terminals. www.onsemi.com 6 NB7NPQ1104M Table 12. TRANSMITTER AC/DC CHARACTERISTICS VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted) Parameter Test Conditions Min Typ Max Unit CHANNEL PERFORMANCE Gp Peaking gain (Compensation at 5 GHz, relative to 100 MHz, 100 mVp−p sine wave input) EQx = L EQx = R EQx = F EQx = H 11.5 7.4 9.9 13.1 Variation around typical GF Flat Gain (