NB7V32M

NB7V32M 1.8V / 2.5V, 10GHz ÷2 Clock Divider with CML Outputs Multi−Level Inputs w/ Internal Termination http://onsemi.com Description The NB7V32M is a differential B 2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a B2 output copy of an input Clock operating up to 10 GHz with minimal jitter. The RESET Pin is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M’s in a system. The 16 mA differential CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated with 50 W to VCC . The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M (2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16−pin QFN package. The NB7V32M is a member of the GigaComm™ family of high performance clock products. Application notes, models, and support documentation are available at www.onsemi.com. Features MARKING DIAGRAM* 1 1 QFN−16 MN SUFFIX CASE 485G 16 NB7V 32M ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. • • • • • • • • • • Maximum Input Clock Frequency > 10 GHz, typical Random Clock Jitter < 0.8 ps RMS 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3 mm x 3 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices R RESET VTCLK 50W CLK Q Q B2 CLK 50W VTCLK VREFAC Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2009 November, 2009 − Rev. 4 1 Publication Order Number: NB7V32M/D NB7V32M VCC 16 VTCLK 1 CLK CLK 2 NB7V32M 3 10 9 5 6 7 8 Q VCC R 15 VCC VCC 14 13 12 11 VCC Q Exposed Pad (EP) Table 1. TRUTH TABLE CLK x Z CLK x W R H L Q L CLK B 2 Q H CLK B 2 Z = LOW to HIGH Transition W = HIGH to LOW Transition x = Don’t Care VTCLK 4 VREFAC GND GND GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name VTCLK CLK CLK VTCLK VREFAC GND GND GND VCC Q Q VCC VCC VCC R VCC EP I/O − LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − − − − − CML Output CML Output − − − LVCMOS Input − − Internal 50 W Termination Pin for CLK Non−inverted Differential CLK Input. (Note 1) Inverted Differential CLK Input. (Note 1) Internal 50 W Termination Pin for CLK Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, only Negative Supply Voltage Negative Supply Voltage Negative Supply Voltage Positive Supply Voltage. (Note 2) Inverted Differential Output Non−Inverted Differential Output Positive Supply Voltage. (Note 2) Positive Supply Voltage. (Note 2) Positive Supply Voltage. (Note 2) Asynchronous Reset Input. Internal 75 kW pulldown to GND. Positive Supply Voltage. (Note 2) The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Description 1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source termination resistors. 2. VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7V32M Table 3. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Human Body Model Machine Model 16−QFN Oxygen Index: 28 to 34 Value > 4 kV > 200 V Level 1 UL 94 V−0 @ 0.125 in 164 Table 4. MAXIMUM RATINGS Symbol VCC VIN VINPP IIN IOUT IVREFAC TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Voltage Differential Input Voltage |D − D| Input Current Through RT (50 W Resistor) Output Current Through RT (50 W Resistor) VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 3) Thermal Resistance (Junction−to−Case) (Note 3) Wave Solder Pb−Free 0 lfpm 500 lfpm QFN−16 QFN−16 QFN−16 Condition 1 GND = 0 V GND = 0 V Condition 2 Rating 3.0 1.89 1.89 $40 $40 $1.5 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA mA mA °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7V32M Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 4) Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.5 V $ 5% VCC = 1.8 V $ 5% 90 80 100 90 mA Characteristic Min Typ Max Unit CML OUTPUTS VOH Output HIGH Voltage (Note 5) VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC = 2.5 V VCC = 1.8 V VCC = 1.8 V DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7) Vth VIH VIL VISE VREFAC VREFAC Output Reference Voltage @ 100 mA for capacitor− coupled inputs, only VCC = 2.5 V (Note 8) VCC = 1.8 V VCC – 850 VCC – 750 VCC – 500 VCC – 450 mV Input Threshold Reference Voltage Range (Note 7) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage (VIH − VIL) 1050 Vth + 100 GND 200 VCC − 100 VCC Vth − 100 1200 mV mV mV mV VCC – 30 2470 1770 VCC – 600 1900 VCC – 550 1250 VCC – 1 2490 1790 VCC – 500 2000 VCC – 450 1350 VCC 2500 1800 VCC – 400 2100 VCC – 350 1450 mV VOL Output LOW Voltage (Note 5) mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 9) (Note 9) VIHD VILD VID VCMR IIH IIL VIH VIL IIH IIL RTIN RTOUT Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) Input HIGH Current (VTCLK/VTCLK Open) Input LOW Current (VTCLK/VTCLK Open) 1100 GND 100 1050 −150 −150 VCC VCC − 100 1200 VCC − 50 150 150 mV mV mV mV uA uA CONTROL INPUT (Reset Pin) Input HIGH Voltage for Control Pin Input LOW Voltage for Control Pin Input HIGH Current Input LOW Current VCC − 200 GND −150 −150 VCC 200 150 150 mV mV uA uA TERMINATION RESISTORS Internal Input Termination Resistor (@ 10 mA) Internal Output Termination Resistor (@ 10 mA) 45 45 50 50 55 55 W W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VREFAC will not be less than GND + 1050 mV. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 4 NB7V32M 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11) Symbol fMAX VOUTPP tPLH, tPHL tPLH TC tskew tRR tPW tDC tJITTER VINPP tr, tf Characteristic Maximum Input Clock Frequency Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 3) Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential cross−point Propagation Delay Temperature Coefficient Duty Cycle Skew (Note 13) Device − Device skew (tpdmax – tpdmin) Reset Recovery (See Figure 11) Minimum Pulse Width R Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 10 GHz RJ – Output Random Jitter (Note 14) fin v 10 GHz Input Voltage Swing (Differential Configuration) (Figure 10) (Note 15) Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q 100 35 300 500 45 135 200 50 0.2 55 0.8 1200 60 % ps RMS mV ps fin ≤ 10GHz CLK/CLK to Q, Q R to Q, Q Min 10 280 150 400 200 200 50 20 50 275 Typ Max Unit GHz mV ps Dfs/°C ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a 1 GHz, VINPPmin, 50% duty−cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. Skew is measured between outputs under identical transitions and conditions. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Input voltage swing is a single−ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 Q AMP (mV) 400 350 300 250 200 0 2 4 6 8 10 VTCLK fin, Clock Input Frequency (GHz) CLK 50 W CLK I VTCLK 50 W RC RC VCC Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure http://onsemi.com 5 NB7V32M VIH Vth VIL CLK Vth CLK CLK CLK Figure 5. Differential Input Driven Single−Ended Figure 6. Differential Inputs Driven Differentially VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin VID = |VIHD(CLK) − VILD(CLK)| VIHD VILD Vth Vthmin GND CLK CLK Figure 7. Vth Diagram VCC VCMmax CLK VCMR CLK VCMmin GND VIHDmax VILDmax VIHDtyp VID = VIHD − VILD VILDtyp VIHDmin VILDmin CLK CLK Q Q Figure 8. Differential Inputs Driven Differentially VINPP = VIH(CLK) − VIL(CLK) VOUTPP = VOH(Q) − VOL(Q) tPHL tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement 50% 50% VOUTPP = VOH(Q) − VOL(Q) Q tPLH tPHL VINPP = VIH(CLK) − VIL(CLK) 50% 50% CLK R tRR(MIN) 50% Figure 11. AC Reference Measurement (Timing Diagram) http://onsemi.com 6 NB7V32M VCC VCC VCC VCC ZO = 50 W LVPECL Driver VTCLK VTCLK NB7V32M CLK 50 W LVDS Driver ZO = 50 W CLK VTCLK VTCLK ZO = 50 W NB7V32M 50 W 50 W Vth ZO = 50 W 50 W CLK Vth = VCC − 2 V VEE VEE GND CLK GND Figure 12. LVPECL Interface Figure 13. LVDS Interface VCC VCC ZO = 50 W CLK NB7V32M 50 W 50 W CML Driver VTCLK ZO = 50 W VT = VT = VCC VCC VTCLK CLK GND GND Figure 14. Standard 50 W Load CML Interface VCC VCC VCC VCC ZO = 50 W CLK VTCLK NB7V32M 50 W 50 W ZO = 50 W CLK NB7V32M 50 W 50 W Differential Driver VTCLK ZO = 50 W CLK Vth = VREFAC Vth Single−Ended Driver Vth VTCLK VTCLK CLK Vth = VREFAC GND GND GND GND Figure 15. Capacitor−Coupled Differential Interface (VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) Figure 16. Capacitor−Coupled Single−Ended Interface (VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) http://onsemi.com 7 NB7V32M NB7V32M VCC Receiver VCC (Receiver) 50 W 50 W Q 50 W Q 50 W 16 mA GND Figure 17. Typical CML Output Structure and Termination VCC 50 W Z = 50 W DUT Driver Device Q Z = 50 W Q 50 W D Receiver Device D Figure 18. Typical Termination for CML Output Driver and Device Evaluation ORDERING INFORMATION Device NB7V32MMNG NB7V32MMNTXG Package QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping† 123 Units / Rail 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB7V32M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D A B L L1 DETAIL A L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG PIN 1 LOCATION TOP VIEW 0.15 C DETAIL B A1 0.10 C (A3) A DETAIL B ALTERNATE CONSTRUCTIONS 16 X 0.08 C SIDE VIEW A1 C SEATING PLANE 16X L DETAIL A 5 4 D2 8 e EXPOSED PAD 9 NOTE 5 0.575 0.022 16X K 1 16 16X 13 E2 12 e 3.25 0.128 b BOTTOM VIEW 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches 0.10 C A B 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NB7V32M), may be covered by U.S. patents including 6,362,644. There may be other patents pending. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 9 ÇÇ ÇÇ ÉÉ ÉÉ ÉÉ ÉÉ 0.15 C ÇÇÇ ÇÇÇ ÇÇÇ E EXPOSED Cu ALTERNATE TERMINAL CONSTRUCTIONS MOLD CMPD A3 DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 SOLDERING FOOTPRINT* 3.25 0.128 0.30 0.012 EXPOSED PAD 1.50 0.059 NB7V32M/D