NB7V32MMNTXG

1.8 V/2.5 V, 10 GHz ÷2 Clock Divider with CML Outputs Multi−Level Inputs w/ Internal Termination NB7V32M www.onsemi.com Description The NB7V32M is a differential B2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML and LVDS logic levels. The NB7V32M produces a B2 output copy of an input Clock operating up to 10 GHz with minimal jitter. The RESET Pin is asserted on the rising edge. Upon power−up, the internal flip−flops will attain a random state; the Reset allows for the synchronization of multiple NB7V32M’s in a system. The 16 mA differential CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated with 50 W to VCC . The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M (2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16−pin QFN package. The NB7V32M is a member of the GigaComm™ family of high performance clock products. Application notes, models, and support documentation are available at www.onsemi.com. Features • • • • • • • • • • Maximum Input Clock Frequency > 10 GHz, typical Random Clock Jitter < 0.8 ps RMS 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3 mm x 3 mm −40°C to +85°C Ambient Operating Temperature These Devices are Pb−Free and RoHS Compliant 1 QFN−16 MN SUFFIX CASE 485G MARKING DIAGRAM* 1 16 NB7V 32M ALYWG G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. R RESET VTCLK 50 W CLK B2 CLK Q Q 50 W VTCLK VREFAC Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2010 May, 2021 − Rev. 6 1 Publication Order Number: NB7V32M/D NB7V32M VCC 16 R 15 VCC VCC 14 Exposed Pad (EP) VTCLK 1 12 VCC 11 Q 3 10 Q VTCLK 4 9 VCC CLK Table 1. TRUTH TABLE 13 2 5 6 7 CLK R Q Q x x H L H Z W L CLK B 2 CLK B 2 Z = LOW to HIGH Transition W = HIGH to LOW Transition x = Don’t Care NB7V32M CLK CLK 8 VREFAC GND GND GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O 1 VTCLK − Description 2 CLK LVPECL, CML, LVDS Input Non−inverted Differential CLK Input. (Note 1) 3 CLK LVPECL, CML, LVDS Input Inverted Differential CLK Input. (Note 1) 4 VTCLK − Internal 50 W Termination Pin for CLK 5 VREFAC − Internally Generated Output Voltage Reference for Capacitor−Coupled Inputs, only 6 GND − Negative Supply Voltage 7 GND − Negative Supply Voltage 8 GND − Negative Supply Voltage 9 VCC − Positive Supply Voltage. (Note 2) 10 Q CML Output Inverted Differential Output Internal 50 W Termination Pin for CLK 11 Q CML Output Non−Inverted Differential Output 12 VCC − Positive Supply Voltage. (Note 2) 13 VCC − Positive Supply Voltage. (Note 2) 14 VCC − Positive Supply Voltage. (Note 2) 15 R LVCMOS Input 16 VCC − Positive Supply Voltage. (Note 2) − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Asynchronous Reset Input. Internal 75 kW pulldown to GND. 1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source termination resistors. 2. VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2 NB7V32M Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model > 4 kV > 200 V Moisture Sensitivity 16−QFN Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 164 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Power Supply GND = 0 V 3.0 V VIN Positive Input Voltage GND = 0 V −0.5 to VCC + 0.5 V V Differential Input Voltage |D − D| 1.89 V Input Current Through RT (50 W Resistor) ±40 mA Output Current Through RT (50 W Resistor) ±40 mA VINPP IIN IOUT IVREFAC Parameter Condition 1 Condition 2 VREFAC Sink/Source Current ±1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 3) QFN−16 QFN−16 42 35 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4 °C/W Tsol Wave Solder Pb−Free 265 °C 0 lfpm 500 lfpm Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. www.onsemi.com 3 NB7V32M Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 4) Symbol Characteristic Min Typ Max 90 80 100 90 Unit POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.5 V ±5% VCC = 1.8 V ±5% mA CML OUTPUTS VOH Output HIGH Voltage (Note 5) VOL Output LOW Voltage (Note 5) VCC = 2.5 V VCC = 1.8 V VCC – 30 2470 1770 VCC – 1 2490 1790 VCC 2500 1800 VCC = 2.5 V VCC = 2.5 V VCC – 600 1900 VCC – 500 2000 VCC – 400 2100 VCC = 1.8 V VCC = 1.8 V VCC – 550 1250 VCC – 450 1350 VCC – 350 1450 mV mV DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7) Vth Input Threshold Reference Voltage Range (Note 7) VIH VIL VISE 1050 VCC − 100 mV Single−Ended Input HIGH Voltage Vth + 100 VCC mV Single−Ended Input LOW Voltage GND Vth − 100 mV Single−Ended Input Voltage (VIH − VIL) 200 1200 mV VCC – 850 VCC – 750 VCC – 500 VCC – 450 VREFAC VREFAC Output Reference Voltage @ 100 mA for capacitor− coupled inputs, only VCC = 2.5 V (Note 8) VCC = 1.8 V mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 9) (Note 9) VIHD Differential Input HIGH Voltage 1100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VID Differential Input Voltage (VIHD − VILD) 100 1200 mV Input Common Mode Range (Differential Configuration, Note 10) (Figure 9) 1050 VCC − 50 mV IIH Input HIGH Current (VTCLK/VTCLK Open) −150 150 uA IIL Input LOW Current (VTCLK/VTCLK Open) −150 150 uA VCMR CONTROL INPUT (Reset Pin) VIH Input HIGH Voltage for Control Pin VCC − 200 VCC mV VIL Input LOW Voltage for Control Pin GND 200 mV IIH Input HIGH Current −150 150 uA IIL Input LOW Current −150 150 uA TERMINATION RESISTORS RTIN RTOUT Internal Input Termination Resistor (@ 10 mA) 45 50 55 W Internal Output Termination Resistor (@ 10 mA) 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Input and output parameters vary 1:1 with VCC. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VREFAC will not be less than GND + 1050 mV. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 NB7V32M Table 6. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; GND = 0 V; TA = −40°C to 85°C (Note 11) Symbol fMAX VOUTPP tPLH, tPHL tPLH TC tskew Characteristic Min Maximum Input Clock Frequency Typ Max 10 Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 3) Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential cross−point fin ≤ 10GHz 280 400 CLK/CLK to Q, Q R to Q, Q 150 200 200 Propagation Delay Temperature Coefficient Unit GHz mV 275 50 ps Dfs/°C Duty Cycle Skew (Note 13) Device − Device skew (tpdmax – tpdmin) 20 50 ps tRR Reset Recovery (See Figure 11) 300 135 tPW Minimum Pulse Width R 500 200 tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin 3 ≤ 10 GHz 45 50 55 % 0.2 0.8 ps RMS 1200 mV 60 ps tJITTER RJ – Output Random Jitter (Note 14) fin ≤ 10 GHz VINPP Input Voltage Swing (Differential Configuration) (Figure 10) (Note 15) tr, tf 100 Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q 35 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 11. Measured using a 1 GHz, VINPPmin, 50% duty−cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Output voltage swing is a single−ended measurement operating in differential mode. 13. Duty cycle skew is defined only for differential operation when the delays are measured from cross−point of the inputs to the cross−point of the outputs. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz. Skew is measured between outputs under identical transitions and conditions. 14. Additive RMS jitter with 50% duty cycle clock signal. 15. Input voltage swing is a single−ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mV) 500 VCC 450 VTCLK Q AMP (mV) 400 50 W RC RC CLK 350 I 300 CLK 250 50 W 200 0 2 4 6 8 10 VTCLK fin, Clock Input Frequency (GHz) Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ) Figure 4. Input Structure www.onsemi.com 5 NB7V32M CLK VIH Vth CLK VIL CLK CLK Vth Figure 5. Differential Input Driven Single−Ended VCC Vthmax Figure 6. Differential Inputs Driven Differentially VIHmax VILmax VIH Vth VIL Vth VILD VILmin GND Figure 7. Vth Diagram VCC Figure 8. Differential Inputs Driven Differentially VIHDmax VCMmax CLK VILDmax CLK VCMR CLK GND VIHD CLK VIHmin Vthmin VCMmin VID = |VIHD(CLK) − VILD(CLK)| CLK VINPP = VIH(CLK) − VIL(CLK) CLK VIHDtyp VID = VIHD − VILD Q VILDtyp VOUTPP = VOH(Q) − VOL(Q) Q VIHDmin tPHL VILDmin tPLH Figure 9. VCMR Diagram Figure 10. AC Reference Measurement 50% 50% VOUTPP = VOH(Q) − VOL(Q) Q tPLH tPHL 50% 50% CLK R tRR(MIN) 50% Figure 11. AC Reference Measurement (Timing Diagram) www.onsemi.com 6 VINPP = VIH(CLK) − VIL(CLK) NB7V32M VCC VCC ZO = 50 W LVPECL Driver Vth ZO = 50 W VCC VCC ZO = 50 W CLK NB7V32M CLK 50 W VTCLK VTCLK VTCLK LVDS Driver VTCLK ZO = 50 W 50 W CLK 50 W 50 W CLK Vth = VCC − 2 V VEE NB7V32M GND VEE GND Figure 12. LVPECL Interface Figure 13. LVDS Interface VCC VCC ZO = 50 W CML Driver VCC CLK NB7V32M 50 W VTCLK VTCLK ZO = 50 W VT = VT = VCC 50 W CLK GND GND Figure 14. Standard 50 W Load CML Interface VCC VCC ZO = 50 W CLK Differential Driver Vth VTCLK VTCLK ZO = 50 W VCC VCC ZO = 50 W NB7V32M 50 W Single−Ended Driver 50 W Vth VTCLK VTCLK CLK NB7V32M 50 W 50 W CLK Vth = VREFAC GND CLK Vth = VREFAC GND GND GND Figure 16. Capacitor−Coupled Single−Ended Interface (VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) Figure 15. Capacitor−Coupled Differential Interface (VTCLK/VTCLK Connected to VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor) www.onsemi.com 7 NB7V32M NB7V32M Receiver VCC VCC (Receiver) 50 W 50 W Q 50 W 50 W Q 16 mA GND Figure 17. Typical CML Output Structure and Termination VCC 50 W Z = 50 W DUT Driver Device 50 W Q D Receiver Device Z = 50 W Q D Figure 18. Typical Termination for CML Output Driver and Device Evaluation ORDERING INFORMATION Device NB7V32MMNTXG Package Shipping† QFN−16 (Pb−free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. The products described herein (NB7V32M), may be covered by U.S. patents including 6,362,644. There may be other patents pending. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485G ISSUE G 1 SCALE 2:1 DATE 08 OCT 2021 GENERIC MARKING DIAGRAM* XXXXX XXXXX ALYWG G XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON04795D QFN16 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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