NB7V52M 1.8V / 2.5V Differential D Flip-Flop w/ Reset and CML Outputs
Multi−Level Inputs w/ Internal Termination
Description http://onsemi.com MARKING DIAGRAM*
1 1 QFN−16 MN SUFFIX CASE 485G 16 NB7V 52M ALYWG G
The NB7V52M is a 10 GHz differential D flip−flop with a differential asynchronous Reset. The differential D/D, CLK/CLK and R/R inputs incorporate dual internal 50 W termination resistors and will accept LVPECL, CML, LVDS logic levels. When Clock transitions from logic Low to High, Data will be transferred to the differential CML outputs. The differential Clock inputs allow the NB7V52M to also be used as a negative edge triggered device. The 16 mA differential CML outputs provide matching internal 50 W termination and produce 400 mV output swings when externally receiver terminated with a 50 W resistor to VCC. The NB7V52M is offered in a low profile 3 mm x 3 mm 16−pin QFN package. The NB7V52M is a member of the GigaComm™ family of high performance clock products. Application notes, models, and support documentation are available at www.onsemi.com.
Features
A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
• • • • • • • • • • •
Maximum Input Clock Frequency > 10 GHz Maximum Input Data Rate > 10 Gb/s Random Clock Jitter < 0.8 ps RMS, Max 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Differential CML Outputs, 400 mV Peak−to−Peak, Typical Operating Range: VCC = 1.71 V to 2.625 V with VEE = 0 V Internal 50 W Input Termination Resistors QFN−16 Package, 3mm x 3mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free Devices
VTD D D VTD
D Flip−Flop
VTCLK CLK CLK VTCLK VTR RR VTR
Q Q
RESET
Figure 1. Logic Diagram ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
September, 2009 − Rev. 3
1
Publication Order Number: NB7V52M/D
NB7V52M
VTR 16 VTD D D VTD 1 2 NB7V52M 3 4 5 VTCLK 6 7 8 10 9 Q VEE R 15 R 14 VTR 13 12 11 VCC Q Exposed Pad (EP)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
R H L L D x L H CLK x Z Z Q L L H
Z = LOW to HIGH Transition x = Don’t care
CLK CLK VTCLK
Figure 2. Pin Configuration (Top View) Table 1. Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 − Name VTD D D VTD VTCLK CLK CLK VTCLK VEE Q Q VCC VTR R R VTR EP I/O − LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − CML Output CML Output − − LVPECL, CML, LVDS Input LVPECL, CML, LVDS Input − − Internal 50 W Termination Pin for D Noninverted Differential Data Input. (Note 1) Inverted Differential Data Input. (Note 1) Internal 50 W Termination Pin for D Internal 50 W Termination Pin for CLK Noninverted Differential Clock Input. (Note 1) Inverted Differential Clock Input. (Note 1) Internal 50 W Termination Pin for CLK Negative Supply Voltage. (Note 2) Inverted Differential Output Noninverted Differential Output Positive Supply Voltage. (Note 2) Internal 50 W Termination Pin for R Noninverted Asynchronous Differential Reset Input. (Note 1) Inverted Asynchronous Differential Reset Input. (Note 1) Internal 50 W Termination Pin for R The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. Description
1. In the differential configuration when the input termination pins (VTx, VTx) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
2
NB7V52M
Table 2. ATTRIBUTES
Characteristics ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Human Body Model Machine Model 16−QFN Oxygen Index: 28 to 34 Value > 2 kV > 200 V Level 1 UL 94 V−0 @ 0.125 in 173
Table 3. MAXIMUM RATINGS
Symbol VCC VIO VINPP IOUT IIN TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input/Output Voltage Differential Input Voltage |CLK − CLK|, |D − D|, |R − R| Output Current Through RTOUT (50 W Resistor) Input Current Through RTIN (50 W Resistor) Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) (Note 3) Thermal Resistance (Junction−to−Case) (Note 3) Wave Solder Pb−Free 0 lfpm 500 lfpm QFN−16 QFN−16 QFN−16 Continuous Surge Condition 1 VEE = 0 V VEE = 0 V −0.5 v VIO v VCC + 0.5 Condition 2 Rating 3.0 −0.5 to VCC +0.5 1.89 34 40 $40 −40 to +85 −65 to +150 42 35 4 265 Unit V V V mA mA °C °C °C/W °C/W °C/W °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB7V52M
Table 4. DC CHARACTERISTICS, Multi−Level Inputs VCC = 1.71 V to 2.625 V, VEE = 0 V, TA = −40°C to +85°C (Note 4)
Symbol POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) VCC = 2.5 V VCC = 1.8 V 90 70 110 90 mA Characteristic Min Typ Max Unit
CML OUTPUTS VOH Output HIGH Voltage (Note 5) VCC = 2.5 V VCC = 1.8 V VCC = 2.5 V VCC = 1.8 V VCC – 30 2470 1770 VCC – 650 1850 VCC – 600 1200 VCC – 10 2490 1790 VCC – 500 2000 VCC – 450 1350 VCC 2500 1800 VCC – 400 2100 VCC – 350 1450 mV
VOL
Output LOW Voltage (Note 5)
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 7) Vth VIH VIL VISE VIHD VILD VID VCMR IIH IIL RTIN RTOUT Input Threshold Reference Voltage Range (Note 7) Single−Ended Input HIGH Voltage Single−Ended Input LOW Voltage Single−Ended Input Voltage (VIH − VIL) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD − VILD) Input Common Mode Range (Differential Configuration, Note 9) (Figure 10) Input HIGH Current (VTx/VTx Open) Input LOW Current (VTx/VTx Open) Internal Input Termination Resistor Internal Output Termination Resistor 1000 Vth + 100 VEE 200 VCC − 100 VCC Vth − 100 1200 mV mV mV mV
DIFFERENTIAL D/D, CLK/CLK, R/R INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) (Note 8) 1100 VEE 100 1050 −250 −250 VCC VCC − 100 1200 VCC − 50 250 250 mV mV mV mV mA mA
TERMINATION RESISTORS 45 45 50 50 55 55 W W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. 5. CML outputs loaded with 50 W to VCC for proper operation. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single−ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
http://onsemi.com
4
NB7V52M
Table 5. AC CHARACTERISTICS VCC = 1.71 V to 2.625 V; VEE = 0 V; TA = −40°C to 85°C (Note 10)
Symbol fMAX fDATA MAX VOUTPP tPLH, tPHL tS tH tRR tPW tJITTER VINPP tr,, tf Characteristic Maximum Input Clock Frequency Maximum Input Data Rate (PRBS23) Output Voltage Amplitude (@ VINPPmin) (See Figures 3 and 10, Note 11) Propagation Delay to Differential Outputs, @ 1 GHz, Measured at Differential Cross−point Setup Time (D to CLK) Hold Time (D to CLK) Reset Recovery Minimum Pulse Width RJ – Output Random Jitter (Note 12) Input Voltage Swing (Differential Configuration) (Note 13) Output Rise/Fall Times @ 1 GHz (20% − 80%), Q, Q R/R fin v 10 GHz 100 20 35 fin ≤ 7 GHz fin ≤ 10 GHz CLK/CLK to Q/Q R/R to Q/Q 40 50 275 1 0.2 0.8 1200 50 Min 10 10 300 250 Typ 12 12 400 400 200 300 15 20 200 350 600 Max Unit GHz Gbps mV ps ps ps ps ns ps RMS mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured using a 400 mV VINPP source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates w40 ps (20% − 80%). 11. Output voltage swing is a single−ended measurement operating in differential mode. 12. Additive RMS jitter with 50% duty cycle clock signal. 13. Input voltage swing is a single−ended measurement operating in differential mode. 500 OUTPUT VOLTAGE AMPLITUDE (mV) 450 Q/Q Output 400 D 350 I 300 250 200 D 50 W 0 1 2 3 4 5 6 7 8 9 10 11 12 VTD RTIN VTD 50 W RTIN RC RC VCC
fin, Clock Input Frequency (GHz)
Figure 3. Clock Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typ)
Figure 4. Simplified Input Structure
http://onsemi.com
5
NB7V52M
VIH Vth VIL CLK Vth CLK/D/R CLK CLK/D/R
Figure 5. Differential Input Driven Single−Ended
Figure 6. Differential Inputs Driven Differentially
VCC Vthmax
VIHmax VILmax VIH Vth VIL VIHmin VILmin VID = |VIHD(CLK) − VILD(CLK)| VIHD VILD
Vth Vthmin VEE
CLK
CLK CLK
Figure 7. Vth Diagram
Figure 8. Differential Inputs Driven Differentially
VCC VCMRmax CLK VCMR CLK VCMRmin VEE
VIHDmax VILDmax VIHDtyp VID = VIHD − VILD VILDtyp VIHDmin VILDmin CLK CLK Q Q tPLH VOUTPP = VOH(Q) − VOL(Q) tPHL VINPP = VIH(CLK) − VIL(CLK)
Figure 9. VCMR Diagram
Figure 10. AC Reference Measurement
http://onsemi.com
6
NB7V52M
NB7V52M VCC Receiver VCC
50 W RTOUT
50 W RTOUT
Q Q
50 W
50 W
16 mA VEE
Figure 11. Typical CML Output Structure and Termination
VCC
50 W Z = 50 W DUT Driver Device Q Z = 50 W Q
50 W D Receiver Device D
Figure 12. Typical Termination for CML Output Driver and Device Evaluation
http://onsemi.com
7
NB7V52M
VCC VCC VCC VCC
ZO = 50 W LVPECL Driver VTD VTD
D
NB7V52M 50 W
ZO = 50 W
D
NB7V52M 50 W 50 W
Vth ZO = 50 W
LVDS Driver
VTD ZO = 50 W VTD
50 W D
Vth = VCC − 2 V GND/VEE VEE GND
D VEE
Figure 13. LVPECL Interface
Figure 14. LVDS Interface
VCC
VCC
ZO = 50 W
D
NB7V52M 50 W 50 W
CML Driver
VCC ZO = 50 W VT = VT = VCC
VTD VTD
D VEE
GND
Figure 15. Standard 50 W Load CML Interface
VCC
VCC
VCC
VCC
ZO = 50 W
D
NB7V52M 50 W 50 W
ZO = 50 W
D
NB7V52M 50 W 50 W
Differential Driver
Vth ZO = 50 W
VTD VTD
Single−Ended Driver
Vth
VTD VTD
D Vth = External VREFAC GND/VEE VEE GND/VEE
D Vth = External VREFAC VEE
Figure 16. Capacitor−Coupled Differential Interface (VT/VT Connected to External VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor)
Figure 17. Capacitor−Coupled Single−Ended Interface (VT/VT Connected to External VREFAC; VREFAC Bypassed to Ground with 0.1 mF Capacitor)
http://onsemi.com
8
NB7V52M
ORDERING INFORMATION
Device NB7V52MMNG NB7V52MMNHTBG NB7V52MMNTXG Package QFN−16 (Pb−free) QFN−16 (Pb−free) QFN−16 (Pb−free) Shipping† 123 Units / Rail 100 / Tape & Reel 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
http://onsemi.com
9
NB7V52M
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G−01 ISSUE D
D A B L L1 DETAIL A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG
PIN 1 LOCATION
0.15 C 0.15 C
TOP VIEW
A1
0.10 C
DETAIL B
(A3) A
DETAIL B
ALTERNATE CONSTRUCTIONS
16 X
0.08 C SIDE VIEW A1 C
SEATING PLANE
16X
L
DETAIL A 5 4
D2
8
e
EXPOSED PAD 9
NOTE 5
0.575 0.022
16X
K
1 16 16X 13
E2
12
e 3.25 0.128 1.50 0.059
b BOTTOM VIEW 0.50 0.02 0.30 0.012
SCALE 10:1 mm inches
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NB7V52M), may be covered by U.S. patents including 6,362,644. There may be other patents pending. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Phone : 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
10
ÇÇ ÇÇ ÉÉ
ÉÉ ÉÉ ÉÉ
ÇÇÇ ÇÇÇ ÇÇÇ
E
EXPOSED Cu
ALTERNATE TERMINAL CONSTRUCTIONS
MOLD CMPD
A3
DIM A A1 A3 b D D2 E E2 e K L L1
MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15
SOLDERING FOOTPRINT*
3.25 0.128 0.30 0.012
EXPOSED PAD
NB7V52M/D
